view packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c @ 3247:6a85fd724dd8

* packages/hal/cortexm/stm32/stm32f4discovery/*: New STM32F4-Discovery platform HAL package. * packages/ecos.db: Add STM32F4-Discovery platform HAL package and target records. * doc/sgml/doclist: Add STM32F4-Discovery doc file.
author jld
date Wed, 12 Jun 2013 13:20:07 +0000
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//      stm32f4discovery_misc.c
//      Cortex-M4 STM32F4-Discovery HAL functions
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
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// eCos is free software; you can redistribute it and/or modify it under    
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// macros or inline functions from this file, or you compile this file      
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// this file does not by itself cause the resulting work to be covered by   
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// General Public License v2.                                               
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// Author(s):    jld
// Based on:     stm32x0g_eval misc setup by jlarmour
// Date:         2013-06-05
// Description:

#include <pkgconf/hal.h>
#include <pkgconf/hal_cortexm.h>
#include <pkgconf/hal_cortexm_stm32.h>
#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>

#include <cyg/infra/cyg_ass.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_if.h>


// We force a compilation error for this fatal condition since run-time asserts
// may not be enabled for the build.
#error "The CALL_IF_TABLE_SIZE pre-allocation in the linker scripts for this platform need to be updated"

// System init
// This is run to set up the basic system, including GPIO setting,
// clock feeds, power supply, and memory initialization. This code
// runs before the DATA is copied from ROM and the BSS cleared, hence
// it cannot make use of static variables or data tables.

__externC void hal_system_init( void )
    CYG_ADDRESS base;

    // Enable CCM clock and any required GPIO ports in RCC
    base = CYGHWR_HAL_STM32_RCC;
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) |
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) |
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) );

    // Set unused lines on enabled GPIO ports to input with pull down

    // GPIO Port A - setup PA0 for button, PA9 for LED, PA13,14 for SWD
    base = CYGHWR_HAL_STM32_GPIOA;
    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x28040000 );

    // GPIO Port C - setup PC10,11 for RS232 (UART4)
    base = CYGHWR_HAL_STM32_GPIOC;
    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00A00000 );

    // GPIO Port D - setup PD5,12,13,14,15 for LEDs
    base = CYGHWR_HAL_STM32_GPIOD;
    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x55000400 );

    // Enable flash prefetch buffer, cacheability and set latency to 2 wait states
    // Latency has to be set before clock is switched to a higher speed
        cyg_uint32 acr;

        base = CYGHWR_HAL_STM32_FLASH;

        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );


__externC void hal_platform_init( void )
    __externC char __sram_data_start[];

    // Check the number of VSRs matches the linker script. We can do this
    // because we intend the VV table to follow the VSR table with no gaps.
    CYG_ASSERT( (char*)&hal_virtual_vector_table[0] - (char*)&hal_vsr_table >= CYGNUM_HAL_VSR_COUNT*4,
                "VSR table size does not match" );
    // Now check the declared start of SRAM data follows the VV table end
    CYG_ASSERT( (__sram_data_start - (char*)&hal_virtual_vector_table[0]) >= CYGNUM_CALL_IF_TABLE_SIZE*4,
                "VV table size does not match sram space" );
    // Check the VSR table fits below declared start of SRAM data
    CYG_ASSERT( (__sram_data_start - (char*)&hal_vsr_table[0]) >= CYGNUM_HAL_VSR_COUNT*4,
                "VSR table size does not match" );

// EOF stm32f4discovery_misc.c