changeset 3273:04cc2ad81e4f

Add interrupt numbers for second eDMA controller. Add clock gating for ADC2. Add GPIO port F.
author vae
date Sun, 16 Feb 2014 08:30:33 +0000
parents a99daf62e693
children fc839db92b9c
files packages/hal/cortexm/kinetis/var/current/ChangeLog packages/hal/cortexm/kinetis/var/current/include/var_intr.h packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h
diffstat 4 files changed, 35 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/cortexm/kinetis/var/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog
@@ -1,3 +1,14 @@
+2014-02-13  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cortexm/kinetis/var/current/include/var_intr.h:
+	Add interrupt numbers for second eDMA controller.
+
+	* cortexm/kinetis/var/current/include/var_io_clkgat.h:
+	Add clock gating for ADC2
+
+	* cortexm/kinetis/var/current/include/var_io_gpio.h:
+	Add GPIO port F.
+
 2013-04-28  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* include/var_intr.h : Redefine CYGNUM_HAL_INTERRUPT_RTC_RTC because of
--- a/packages/hal/cortexm/kinetis/var/current/include/var_intr.h
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_intr.h
@@ -169,6 +169,25 @@ typedef enum {
     CYGNUM_HAL_INTERRUPT_I2S1_RX          // I2S1 receive interrupt
 } KinetisExtInterrupt_e;
 
+// DMA16..31 share interrupt vectors with DMA0..15 respectively.
+
+#define    CYGNUM_HAL_INTERRUPT_DMA16  CYGNUM_HAL_INTERRUPT_DMA0
+#define    CYGNUM_HAL_INTERRUPT_DMA17  CYGNUM_HAL_INTERRUPT_DMA1
+#define    CYGNUM_HAL_INTERRUPT_DMA18  CYGNUM_HAL_INTERRUPT_DMA2
+#define    CYGNUM_HAL_INTERRUPT_DMA19  CYGNUM_HAL_INTERRUPT_DMA3
+#define    CYGNUM_HAL_INTERRUPT_DMA20  CYGNUM_HAL_INTERRUPT_DMA4
+#define    CYGNUM_HAL_INTERRUPT_DMA21  CYGNUM_HAL_INTERRUPT_DMA5
+#define    CYGNUM_HAL_INTERRUPT_DMA22  CYGNUM_HAL_INTERRUPT_DMA6
+#define    CYGNUM_HAL_INTERRUPT_DMA23  CYGNUM_HAL_INTERRUPT_DMA7
+#define    CYGNUM_HAL_INTERRUPT_DMA34  CYGNUM_HAL_INTERRUPT_DMA8
+#define    CYGNUM_HAL_INTERRUPT_DMA25  CYGNUM_HAL_INTERRUPT_DMA9
+#define    CYGNUM_HAL_INTERRUPT_DMA26  CYGNUM_HAL_INTERRUPT_DMA10
+#define    CYGNUM_HAL_INTERRUPT_DMA27  CYGNUM_HAL_INTERRUPT_DMA11
+#define    CYGNUM_HAL_INTERRUPT_DMA28  CYGNUM_HAL_INTERRUPT_DMA12
+#define    CYGNUM_HAL_INTERRUPT_DMA29  CYGNUM_HAL_INTERRUPT_DMA13
+#define    CYGNUM_HAL_INTERRUPT_DMA30  CYGNUM_HAL_INTERRUPT_DMA14
+#define    CYGNUM_HAL_INTERRUPT_DMA31  CYGNUM_HAL_INTERRUPT_DMA15
+
 #define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_I2S1_RX)
 
 #define CYGNUM_HAL_ISR_MIN            0
--- a/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h
@@ -271,6 +271,8 @@
 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S            25
 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M            0x8000000
 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S            27
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_M            0x10000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_S            28
 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M             0x20000000
 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S             29
 
@@ -308,6 +310,8 @@
         CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S)
 #define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC0     \
         CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC2     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_S)
 #define CYGHWR_HAL_KINETIS_SIM_SCGC_RTC      \
         CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S)
 
--- a/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h
@@ -69,6 +69,7 @@ typedef volatile struct cyghwr_hal_kinet
 #define CYGHWR_HAL_KINETIS_GPIO_PORTC_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF080u)
 #define CYGHWR_HAL_KINETIS_GPIO_PORTD_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF0C0u)
 #define CYGHWR_HAL_KINETIS_GPIO_PORTE_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF100u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTF_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF140u)
 
 // GPIO register on a given port (register name is lower case)
 #define CYGHWR_HAL_KINETIS_GPIO(__port, __reg)           \