changeset 3220:1bdcb5fe31d1

Add clock gating enable.
author vae
date Sun, 07 Apr 2013 16:19:00 +0000
parents 2294cb4fd519
children fff0cdf83b21
files packages/devs/eth/freescale/enet/current/ChangeLog packages/devs/eth/freescale/enet/current/src/if_freescale_enet.c packages/devs/serial/freescale/uart/drv/current/ChangeLog packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_chan.inl packages/devs/serial/freescale/uart/drv/current/src/ser_freescale_uart.c packages/hal/misc/freescale/edma/current/ChangeLog packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c
diffstat 7 files changed, 43 insertions(+), 10 deletions(-) [+]
line wrap: on
line diff
--- a/packages/devs/eth/freescale/enet/current/ChangeLog
+++ b/packages/devs/eth/freescale/enet/current/ChangeLog
@@ -1,3 +1,7 @@
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/if_freescale_enet.c: Add clock gating enable. [ Bugzilla 1001814 ]
+
 2012-05-04  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* cdl/eth_freescale_enet.cdl:
--- a/packages/devs/eth/freescale/enet/current/src/if_freescale_enet.c
+++ b/packages/devs/eth/freescale/enet/current/src/if_freescale_enet.c
@@ -6,7 +6,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2011 Free Software Foundation, Inc.                        
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -319,6 +319,7 @@ typedef struct freescale_enet_priv_t {
     cyg_uint32 *txkey_head_p;             // Last Txkey entry
     cyg_uint32 *txkey_tail_p;             // Last Txkey released
 #endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    cyg_uint32 clock;                     // Clock gating
     const cyg_uint32 *pins_p;             // (R)MII pin configuration data
     cyg_uint8 *enaddr;                    // Default ethernet (MAC) address
     cyg_uint32 rx_intr_vector;
@@ -474,6 +475,7 @@ freescale_enet_priv_t enet0_eth0_priv = 
     .txbuf_size   = CYGNUM_DEVS_ETH_FREESCALE_ENET0_TXBUF_SIZE,
     .txbuf_p      = enet0_txbuf,
 #endif //  CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    .clock       = CYGHWR_IO_FREESCALE_ENET0_CLOCK,
     .pins_p      = enet0_pins,
     .pins_n      = sizeof(enet0_pins)/sizeof(enet0_pins[0]),
     .enaddr   = enet0_macaddr,
@@ -743,6 +745,9 @@ enet_eth_init(struct cyg_netdevtab_entry
 #ifdef CYGHWR_DEVS_ETH_FREESCALE_ENET_GET_ESA
     bool esa_ok = false;
 #endif
+    // Bring clock to the sevice
+    CYGHWR_IO_CLOCK_ENABLE(enet_priv_p->clock);
+    // Assign pins
     enet_cfg_pins(enet_priv_p);
 
     HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIMR, 0);
--- a/packages/devs/serial/freescale/uart/drv/current/ChangeLog
+++ b/packages/devs/serial/freescale/uart/drv/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/ser_freescale_uart_chan.inl. include/ser_freescale_uart.c:
+	Add clock gating enable. [ Bugzilla 1001814 ]
+
 2012-02-07  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* cdl/ser_freescale_uart.cdl:
--- a/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_chan.inl
+++ b/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_chan.inl
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2011 Free Software Foundation, Inc.                        
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -60,6 +60,7 @@ static uart_serial_info uart_serial_info
     uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE,
     interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR,
     interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART0_CLOCK,
     pins_p             : &uart0_pins
 };
 #if CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE > 0
@@ -114,6 +115,7 @@ static uart_serial_info uart_serial_info
     uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE,
     interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR,
     interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART1_CLOCK,
     pins_p             : &uart1_pins
 };
 #if CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE > 0
@@ -167,6 +169,7 @@ static uart_serial_info uart_serial_info
     uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE,
     interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR,
     interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART2_CLOCK,
     pins_p             : &uart2_pins
 };
 #if CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE > 0
@@ -221,6 +224,7 @@ static uart_serial_info uart_serial_info
     uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE,
     interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR,
     interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART3_CLOCK,
     pins_p             : &uart3_pins
 };
 #if CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE > 0
@@ -275,6 +279,7 @@ static uart_serial_info uart_serial_info
     uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE,
     interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR,
     interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART4_CLOCK,
     pins_p             : &uart4_pins
 };
 #if CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE > 0
@@ -329,6 +334,7 @@ static uart_serial_info uart_serial_info
     uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE,
     interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR,
     interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART5_CLOCK,
     pins_p             : &uart5_pins
 };
 #if CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE > 0
--- a/packages/devs/serial/freescale/uart/drv/current/src/ser_freescale_uart.c
+++ b/packages/devs/serial/freescale/uart/drv/current/src/ser_freescale_uart.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2011 Free Software Foundation, Inc.                        
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -76,7 +76,8 @@ typedef struct uart_serial_info {
     CYG_ADDRWORD   uart_base;          // Base address of the uart port
     CYG_WORD       interrupt_num;      // NVIC interrupt vector
     cyg_priority_t interrupt_priority; // NVIC interupt priority
-    const uart_pins_t *pins_p;
+    const uart_pins_t *pins_p;         // Rx, Tx, etc.
+    cyg_uint32     clock;              // Clock gate
     cyg_bool tx_active;
     cyg_interrupt  interrupt_obj;      // Interrupt object
     cyg_handle_t   interrupt_handle;   // Interrupt handle
@@ -147,7 +148,9 @@ uart_serial_config_port(serial_channel *
     cyg_uint32 baud_rate = select_baud[new_config->baud];
 
     if(!baud_rate) return false;    // Invalid baud rate selected
-
+    
+    // Bring clock to the sevice
+    CYGHWR_IO_CLOCK_ENABLE(uart_chan->clock);
     // Configure PORT pins
     CYGHWR_IO_FREESCALE_UART_PIN(uart_chan->pins_p->rx);
     CYGHWR_IO_FREESCALE_UART_PIN(uart_chan->pins_p->tx);
--- a/packages/hal/misc/freescale/edma/current/ChangeLog
+++ b/packages/hal/misc/freescale/edma/current/ChangeLog
@@ -1,8 +1,13 @@
-2013-02-06  Stefan Singer <stefan.singer@freescale.com> 
-		+ Ilija Kocho <ilijak@siva.com.mk>
+2013-04-01  Ilija Kocho <ilijak@siva.com.mk>
+
+	* src/hal_freescale_edma.c:	Add clock gating enable.
 
-	* enhanced endianness support for devices with big and little endian
-	* added support for MPC5xxx in addition to Kinetis
+2013-02-06  Stefan Singer <stefan.singer@freescale.com>
+		    Ilija Kocho <ilijak@siva.com.mk>
+
+	* include/freescale_edma.h src/hal_freescale_edma.c:	
+	enhanced endianness support for devices with big and little endian
+	added support for MPC5xxx in addition to Kinetis
 	(see Bugzilla 1001752).
 	
 2012-05-04  Ilija Kocho  <ilijak@siva.com.mk>
--- a/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c
+++ b/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c
@@ -215,7 +215,12 @@ void
 hal_freescale_edma_init(cyghwr_hal_freescale_edma_t *edma_p)
 {
     cyg_uint32 regval;
-
+    
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_IO_FREESCALE_EDMA0_CLK);
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_IO_FREESCALE_DMAMUX0_CLK);
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_IO_FREESCALE_DMAMUX1_CLK);
+#endif
     regval = edma_p->cr;
 #if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
     regval &= ~(FREESCALE_EDMA_GR_PRI(0, 3) | FREESCALE_EDMA_GR_PRI(1, 3));