changeset 3219:2294cb4fd519

Clock gating synchronised with variant.
author vae
date Sun, 07 Apr 2013 16:05:15 +0000
parents 1f92f3f7cf61
children 1bdcb5fe31d1
files packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c
diffstat 10 files changed, 123 insertions(+), 85 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/kwikstik_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
 2012-11-06  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* cdl/hal_cortexm_kinetis_kwikstik.cdl:
--- a/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2011 Free Software Foundation, Inc.
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -64,7 +64,7 @@
 #include <cyg/hal/hal_arch.h>           // HAL header
 #include <cyg/hal/hal_intr.h>           // HAL header
 
-static inline void hal_gpio_init(void);
+static inline void hal_misc_init(void);
 
 // DATA and BSS locations
 __externC cyg_uint32 __ram_data_start;
@@ -90,7 +90,7 @@ hal_system_init( void )
 {
 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
     hal_wdog_disable();
-    hal_gpio_init();
+    hal_misc_init();
     hal_start_clocks();
 #endif
 #if defined(CYG_HAL_STARTUP_SRAM) && !defined(CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED)
@@ -116,29 +116,29 @@ hal_system_init( void )
 }
 
 //===========================================================================
-// hal_gpio_init
+// hal_misc_init
 //===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
 static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
-hal_gpio_init(void)
+hal_misc_init(void)
 {
     cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
     cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
 
-    // Enable clocks on all ports.
-    sim_p->scgc1 = CYGHWR_HAL_KINETIS_SIM_SCGC1_ALL_M;
-    sim_p->scgc2 = CYGHWR_HAL_KINETIS_SIM_SCGC2_ALL_M;
-    sim_p->scgc3 = CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M;
-    sim_p->scgc4 = CYGHWR_HAL_KINETIS_SIM_SCGC4_ALL_M;
-    sim_p->scgc5 = CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M;
-    sim_p->scgc6 = CYGHWR_HAL_KINETIS_SIM_SCGC6_ALL_M;
-    sim_p->scgc7 = CYGHWR_HAL_KINETIS_SIM_SCGC7_ALL_M;
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
 
     // Disable MPU
     mpu_p->cesr = 0;
 }
 
-
-
 //==========================================================================
 
 __externC void hal_platform_init( void )
--- a/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k40x256_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
 2012-11-06  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
--- a/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2011 Free Software Foundation, Inc.                        
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -64,7 +64,7 @@
 #include <cyg/hal/hal_arch.h>           // HAL header
 #include <cyg/hal/hal_intr.h>           // HAL header
 
-static inline void hal_gpio_init(void);
+static inline void hal_misc_init(void);
 
 // DATA and BSS locations
 __externC cyg_uint32 __ram_data_start;
@@ -89,28 +89,30 @@ hal_system_init( void )
 {
 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
     hal_wdog_disable();
-    hal_gpio_init();
+    hal_misc_init();
     hal_start_clocks();
 #endif
 }
 
 //===========================================================================
-// hal_gpio_init
+// hal_misc_init
 //===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
 static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
-hal_gpio_init(void)
+hal_misc_init(void)
 {
     cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
     cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
 
-    // Enable clocks on all ports.
-    sim_p->scgc1 = CYGHWR_HAL_KINETIS_SIM_SCGC1_ALL_M;
-    sim_p->scgc2 = CYGHWR_HAL_KINETIS_SIM_SCGC2_ALL_M;
-    sim_p->scgc3 = CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M;
-    sim_p->scgc4 = CYGHWR_HAL_KINETIS_SIM_SCGC4_ALL_M;
-    sim_p->scgc5 = CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M;
-    sim_p->scgc6 = CYGHWR_HAL_KINETIS_SIM_SCGC6_ALL_M;
-    sim_p->scgc7 = CYGHWR_HAL_KINETIS_SIM_SCGC7_ALL_M;
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
 
     // Disable MPU
     mpu_p->cesr = 0;
--- a/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k60n512_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
 2012-10-25  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* src/twr_k60n512_misc.c: Initialization for separate SRAM regions
--- a/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2011 Free Software Foundation, Inc.                        
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -64,7 +64,7 @@
 #include <cyg/hal/hal_arch.h>           // HAL header
 #include <cyg/hal/hal_intr.h>           // HAL header
 
-static inline void hal_gpio_init(void);
+static inline void hal_misc_init(void);
 
 // DATA and BSS locations
 __externC cyg_uint32 __ram_data_start;
@@ -89,28 +89,30 @@ hal_system_init( void )
 {
 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
     hal_wdog_disable();
-    hal_gpio_init();
+    hal_misc_init();
     hal_start_clocks();
 #endif
 }
 
 //===========================================================================
-// hal_gpio_init
+// hal_misc_init
 //===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
 static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
-hal_gpio_init(void)
+hal_misc_init(void)
 {
     cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
     cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
 
-    // Enable clocks on all ports.
-    sim_p->scgc1 = CYGHWR_HAL_KINETIS_SIM_SCGC1_ALL_M;
-    sim_p->scgc2 = CYGHWR_HAL_KINETIS_SIM_SCGC2_ALL_M;
-    sim_p->scgc3 = CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M;
-    sim_p->scgc4 = CYGHWR_HAL_KINETIS_SIM_SCGC4_ALL_M;
-    sim_p->scgc5 = CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M;
-    sim_p->scgc6 = CYGHWR_HAL_KINETIS_SIM_SCGC6_ALL_M;
-    sim_p->scgc7 = CYGHWR_HAL_KINETIS_SIM_SCGC7_ALL_M;
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
 
     // Disable MPU
     mpu_p->cesr = 0;
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k60n512_fxm_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
 2012-11-06 Ilija Kocho  <ilijak@siva.com.mk>
 
 	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c
@@ -103,7 +103,7 @@
 
 #endif //  CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
 
-static inline void hal_gpio_init(void);
+static inline void hal_misc_init(void);
 static inline void hal_flexbus_init_initial(void);
 static inline void hal_flexbus_init_final(void);
 
@@ -130,7 +130,7 @@ hal_system_init( void )
 {
 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
     hal_wdog_disable();
-    hal_gpio_init();
+    hal_misc_init();
 # ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
     {
         // This delay is needed for Micron RAM wake-up.
@@ -154,22 +154,24 @@ hal_system_init( void )
 }
 
 //===========================================================================
-// hal_gpio_init
+// hal_misc_init
 //===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
 static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
-hal_gpio_init(void)
+hal_misc_init(void)
 {
     cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
     cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
 
-    // Enable clocks on all ports.
-    sim_p->scgc1 = CYGHWR_HAL_KINETIS_SIM_SCGC1_ALL_M;
-    sim_p->scgc2 = CYGHWR_HAL_KINETIS_SIM_SCGC2_ALL_M;
-    sim_p->scgc3 = CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M;
-    sim_p->scgc4 = CYGHWR_HAL_KINETIS_SIM_SCGC4_ALL_M;
-    sim_p->scgc5 = CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M;
-    sim_p->scgc6 = CYGHWR_HAL_KINETIS_SIM_SCGC6_ALL_M;
-    sim_p->scgc7 = CYGHWR_HAL_KINETIS_SIM_SCGC7_ALL_M;
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
 
     // Disable MPU
     mpu_p->cesr = 0;
@@ -248,6 +250,8 @@ hal_flexbus_init_initial(void)
 {
     cyghwr_hal_kinetis_fb_t *fb_p = CYGHWR_HAL_KINETIS_FB_P;
 
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXBUS);
+
 # ifdef CYGHWR_HAL_KINETIS_FB_CS0
     fb_p->csel[0] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS0_AR,
               CYGHWR_HAL_KINETIS_FB_CS0_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(0) };
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k70f120m_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
 2013-03-09  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* misc/redboot_K70_ROM_FPU.ecm: Add ECM file
@@ -11,8 +16,8 @@ 2012-11-30  Ilija Kocho  <ilijak@siva.co
 
 2012-11-04  Ilija Kocho  <ilijak@siva.com.mk>
 
-	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
-	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi:
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi:
 	Recognize 256 Bytes space for virtual vectors in sram.
 
 	* twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
@@ -20,16 +25,16 @@ 2012-11-04  Ilija Kocho  <ilijak@siva.co
 
 2012-09-28  Ilija Kocho  <ilijak@siva.com.mk>
 
-	* twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
-	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
-	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
-	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
-	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
-	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
-	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
-	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
-	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
-	* twr_k70f120m/current/src/twr_k70f120m_misc.c:
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
+	* current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
+	* current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
+	* current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
+	* src/twr_k70f120m_misc.c:
 	Synchronized with Kinetis variant changes to SDRAM controller support.
 	Memory layouts adapted to separate data and code cacing partitions.
 	                                            [Bugzilla 1001606]
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2012 Free Software Foundation, Inc.                        
+// Copyright (C) 2012, 2013 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -64,7 +64,7 @@
 #include <cyg/hal/hal_arch.h>           // HAL header
 #include <cyg/hal/hal_intr.h>           // HAL header
 
-static inline void hal_gpio_init(void);
+static inline void hal_misc_init(void);
 
 // DATA and BSS locations
 __externC cyg_uint32 __ram_data_start;
@@ -148,10 +148,17 @@ const cyg_uint32 kinetis_ddr_cfg[] = {
 __externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
 hal_system_init( void )
 {
-//#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
 #if !defined(CYG_HAL_STARTUP_RAM)
+    cyghwr_hal_kinetis_pmc_t *pmc_p = CYGHWR_HAL_KINETIS_PMC_P;
+
     hal_wdog_disable();
-    hal_gpio_init();
+    hal_misc_init();
+
+    // if ACKISO is set you must clear ackiso before calling pll_init
+    //    or pll init hangs waiting for OSC to initialize
+    if(pmc_p->regsc & CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M)
+        pmc_p->regsc |= CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M;
+
     hal_start_clocks();
 # ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
     HAL_CORTEXM_KINETIS_DDRMC_INIT( kinetis_ddr_cfg );
@@ -160,28 +167,26 @@ hal_system_init( void )
 }
 
 //===========================================================================
-// hal_gpio_init
+// hal_misc_init
 //===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M)
+
 static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
-hal_gpio_init(void)
+hal_misc_init(void)
 {
     cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
     cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
-    cyghwr_hal_kinetis_pmc_t *pmc_p = CYGHWR_HAL_KINETIS_PMC_P;
 
-    // Enable clocks on all ports.
-    sim_p->scgc1 = CYGHWR_HAL_KINETIS_SIM_SCGC1_ALL_M;
-    sim_p->scgc2 = CYGHWR_HAL_KINETIS_SIM_SCGC2_ALL_M;
-    sim_p->scgc3 = CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M;
-    sim_p->scgc4 = CYGHWR_HAL_KINETIS_SIM_SCGC4_ALL_M;
-    sim_p->scgc5 = CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M | CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M;
-    sim_p->scgc6 = CYGHWR_HAL_KINETIS_SIM_SCGC6_ALL_M | CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_M;
-    sim_p->scgc7 = CYGHWR_HAL_KINETIS_SIM_SCGC7_ALL_M;
-
-    // if ACKISO is set you must clear ackiso before calling pll_init
-    //    or pll init hangs waiting for OSC to initialize
-    if(pmc_p->regsc & CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M)
-        pmc_p->regsc |= CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M;
+    // Enable some peripherals' clocks.
+    sim_p->scgc1 |= CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M;
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
 
     // Disable MPU
     mpu_p->cesr = 0;