changeset 3224:4ef59b2cf8d3

Update ETH macros for F4 device.
author vae
date Sun, 14 Apr 2013 23:30:51 +0000
parents 4486b48763e2
children fdccb03963f6
files packages/hal/cortexm/stm32/var/current/ChangeLog packages/hal/cortexm/stm32/var/current/include/var_io.h packages/hal/cortexm/stm32/var/current/include/var_io_eth.h
diffstat 3 files changed, 60 insertions(+), 17 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/cortexm/stm32/var/current/ChangeLog
+++ b/packages/hal/cortexm/stm32/var/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-06  Jerzy Dyrda  <jerzdy@gmail.com>
+
+	* include/var_io_eth.h: 
+	* include/var_io.h: Update ETH macros for F4 device. [ Bugzilla 1001219 ]
+
 2013-01-19  John Dallaway  <john@dallaway.org.uk>
 
 	* include/var_io.h: Fix CYGHWR_HAL_STM32_UART6 definition.
--- a/packages/hal/cortexm/stm32/var/current/include/var_io.h
+++ b/packages/hal/cortexm/stm32/var/current/include/var_io.h
@@ -44,7 +44,7 @@
 // Author(s):   nickg
 // Date:        2008-07-30
 // Purpose:     STM32 variant specific registers
-// Description: 
+// Description:
 // Usage:       #include <cyg/hal/var_io.h>
 //
 //####DESCRIPTIONEND####
@@ -291,6 +291,7 @@
 #define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_XXX    VALUE_(14,3)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSI    0
 #define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSE    BIT_(16)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_PREDIV1 BIT_(16)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PLLXTPRE      BIT_(17)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PLLMUL(__x)   VALUE_(18,(__x)-2)
 #define CYGHWR_HAL_STM32_RCC_CFGR_USBPRE        BIT_(22)
@@ -304,6 +305,8 @@
 #define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL3_HALF VALUE_(24,9)
 #define CYGHWR_HAL_STM32_RCC_CFGR_MCO_XT1       VALUE_(24,10)
 #define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL3      VALUE_(24,11)
+#define CYGHWR_HAL_STM32_RCC_CR_PLL2ON          BIT_(26)
+#define CYGHWR_HAL_STM32_RCC_CR_PLL2RDY         BIT_(27)
 # endif
 #elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1       VALUE_(10,0)
@@ -356,6 +359,13 @@
 #define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMAC      (14)
 #define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMACTX    (15)
 #define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMACRX    (16)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_RCC_AHBRSTR_OTGFSRST   BIT_(12)
+#define CYGHWR_HAL_STM32_RCC_AHBRSTR_ETHMACRST  BIT_(14)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_AHB1RSTR_ETHMACRST BIT_(25)
+#endif
 #endif
 
 // Note that the following are bit numbers, not masks. They should
@@ -848,7 +858,7 @@
 #define CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x)  ( ((__x)&0x3) == 3 ? 22 : \
                                                ((__x)&0x3) == 2 ? 16 : \
                                                ((__x)&0x3) == 1 ? 6 : 0 )
-    
+
 #define CYGHWR_HAL_STM32_DMA_ISR_FEIF(__x)      BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) )
 #define CYGHWR_HAL_STM32_DMA_ISR_DMEIF(__x)     BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 2 )
 #define CYGHWR_HAL_STM32_DMA_ISR_TEIF(__x)      BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 3 )
@@ -1438,14 +1448,14 @@
 
 #if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 
-#define CYGHWR_HAL_STM32_USB_EP0R               0x00 
-#define CYGHWR_HAL_STM32_USB_EP1R               0x04 
-#define CYGHWR_HAL_STM32_USB_EP2R               0x08 
-#define CYGHWR_HAL_STM32_USB_EP3R               0x0C 
-#define CYGHWR_HAL_STM32_USB_EP4R               0x10 
-#define CYGHWR_HAL_STM32_USB_EP5R               0x14 
-#define CYGHWR_HAL_STM32_USB_EP6R               0x18 
-#define CYGHWR_HAL_STM32_USB_EP7R               0x1C 
+#define CYGHWR_HAL_STM32_USB_EP0R               0x00
+#define CYGHWR_HAL_STM32_USB_EP1R               0x04
+#define CYGHWR_HAL_STM32_USB_EP2R               0x08
+#define CYGHWR_HAL_STM32_USB_EP3R               0x0C
+#define CYGHWR_HAL_STM32_USB_EP4R               0x10
+#define CYGHWR_HAL_STM32_USB_EP5R               0x14
+#define CYGHWR_HAL_STM32_USB_EP6R               0x18
+#define CYGHWR_HAL_STM32_USB_EP7R               0x1C
 
 #define CYGHWR_HAL_STM32_USB_CNTR               0x40
 #define CYGHWR_HAL_STM32_USB_ISTR               0x44
--- a/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h
+++ b/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h
@@ -44,7 +44,7 @@
 // Author(s):   nickg, jlarmour
 // Date:        2008-07-30
 // Purpose:     STM32 variant ETH specific registers
-// Description: 
+// Description:
 // Usage:       Do not include this header file directly. Instead:
 //              #include <cyg/hal/var_io.h>
 //
@@ -177,7 +177,7 @@
 #define CYGHWR_HAL_STM32_ETH_MACMIIAR_MB        BIT_(0)
 #define CYGHWR_HAL_STM32_ETH_MACMIIAR_MW        BIT_(1)
 #define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(__x)   VALUE_(2,__x)
-#define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MASK   MASK_(2,3)
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MASK   MASK_(2,4)
 
 #if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 # define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 72)
@@ -190,6 +190,7 @@
 // irrelevance for >72Mhz speed, but that's checked above) but it's
 // foreseeable that this could change for future products.
 # define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ(_mhz)  (          \
+  ((_mhz) >= 150) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(4) :       \
   ((_mhz) >= 100) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(1) :       \
   ((_mhz) >= 60)  ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(0) :       \
   ((_mhz) >= 35)  ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(3) :       \
@@ -321,6 +322,20 @@
 
 // Transmit descriptor fields
 
+/*
+-----------------------------------------------------------------------
+TDES0|OWN(31)|CTRL[30:26]|Res[25:24]|CTRL[23:20]|Res[19:17]|Stat[16:0]|
+-----------------------------------------------------------------------
+TDES1|Res[31:29]| Buffer2 Len[28:16] | Res[15:13] | Buffer1 Len[12:0] |
+-----------------------------------------------------------------------
+TDES2|               Buffer1 Address [31:0]                           |
+-----------------------------------------------------------------------
+TDES3|               Buffer2 Address [31:0]                           |
+-----------------------------------------------------------------------
+*/
+
+// TDES0 register: DMA Tx descriptor status
+
 #define CYGHWR_HAL_STM32_ETH_TDES0_DB           BIT_(0)
 #define CYGHWR_HAL_STM32_ETH_TDES0_UF           BIT_(1)
 #define CYGHWR_HAL_STM32_ETH_TDES0_ED           BIT_(2)
@@ -350,11 +365,25 @@
 #define CYGHWR_HAL_STM32_ETH_TDES0_IC           BIT_(30)
 #define CYGHWR_HAL_STM32_ETH_TDES0_OWN          BIT_(31)
 
-#define CYGHWR_HAL_STM32_ETH_TDES1_TBS1(__x)    VALUE_(0,__x)
-#define CYGHWR_HAL_STM32_ETH_TDES1_TBS2(__x)    VALUE_(16,__x)
+#define CYGHWR_HAL_STM32_ETH_TDES1_TBS1(__x)    (VALUE_(0,__x)&0x00001FFF)
+#define CYGHWR_HAL_STM32_ETH_TDES1_TBS2(__x)    (VALUE_(16,__x)&0x1FFF0000)
 
 // Receive descriptor fields
 
+/*
+-----------------------------------------------------------------------
+RDES0| OWN(31) |                Status [30:0]                         |
+-----------------------------------------------------------------------
+RDES1|DIC(31)|Res[30:29]|Not Used|CTRL[15:14]|Res(13)|Buffer Len[12:0]|
+-----------------------------------------------------------------------
+RDES2|                Buffer1 Address [31:0]                          |
+-----------------------------------------------------------------------
+RDES3|                      Not Used                                  |
+-----------------------------------------------------------------------
+*/
+
+// RDES0 register: DMA Rx descriptor status
+
 #define CYGHWR_HAL_STM32_ETH_RDES0_PCE          BIT_(0)
 #define CYGHWR_HAL_STM32_ETH_RDES0_CE           BIT_(1)
 #define CYGHWR_HAL_STM32_ETH_RDES0_DE           BIT_(2)
@@ -375,6 +404,8 @@
 #define CYGHWR_HAL_STM32_ETH_RDES0_AFM          BIT_(30)
 #define CYGHWR_HAL_STM32_ETH_RDES0_OWN          BIT_(31)
 
+// RDES1 register : DMA Rx descriptor control and buffer length
+
 #define CYGHWR_HAL_STM32_ETH_RDES1_RBS1(__x)    VALUE_(0,__x)
 #define CYGHWR_HAL_STM32_ETH_RDES1_RCH          BIT_(14)
 #define CYGHWR_HAL_STM32_ETH_RDES1_RER          BIT_(15)
@@ -414,9 +445,6 @@
 #define CYGHWR_HAL_STM32_ETH_RMII_MDC           CYGHWR_HAL_STM32_ETH_MII_MDC
 #define CYGHWR_HAL_STM32_ETH_RMII_REF_CLK       CYGHWR_HAL_STM32_ETH_MII_RX_CLK
 #define CYGHWR_HAL_STM32_ETH_RMII_MDIO          CYGHWR_HAL_STM32_ETH_MII_MDIO
-#define CYGHWR_HAL_STM32_ETH_RMII_CRS_DV        CYGHWR_HAL_STM32_ETH_MII_RX_DV
-#define CYGHWR_HAL_STM32_ETH_RMII_RXD0          CYGHWR_HAL_STM32_ETH_MII_RXD0
-#define CYGHWR_HAL_STM32_ETH_RMII_RXD1          CYGHWR_HAL_STM32_ETH_MII_RXD1
 #define CYGHWR_HAL_STM32_ETH_RMII_TX_EN         CYGHWR_HAL_STM32_ETH_MII_TX_EN
 #define CYGHWR_HAL_STM32_ETH_RMII_TXD0          CYGHWR_HAL_STM32_ETH_MII_TXD0
 #define CYGHWR_HAL_STM32_ETH_RMII_TXD1          CYGHWR_HAL_STM32_ETH_MII_TXD1