changeset 3247:6a85fd724dd8

* packages/hal/cortexm/stm32/stm32f4discovery/*: New STM32F4-Discovery platform HAL package. * packages/ecos.db: Add STM32F4-Discovery platform HAL package and target records. * doc/sgml/doclist: Add STM32F4-Discovery doc file.
author jld
date Wed, 12 Jun 2013 13:20:07 +0000
parents 0e1564740f6b
children 04f96179ad68
files doc/ChangeLog doc/sgml/doclist packages/ChangeLog packages/NEWS packages/ecos.db packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c
diffstat 19 files changed, 1232 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/doc/ChangeLog
+++ b/doc/ChangeLog
@@ -1,3 +1,7 @@
+2013-06-12  John Dallaway  <john@dallaway.org.uk>
+
+	* sgml/doclist: Add STM32F4-Discovery documentation.
+
 2013-05-09  John Dallaway  <john@dallaway.org.uk>
 
 	* sgml/makemakefile: Update copyright dates.
--- a/doc/sgml/doclist
+++ b/doc/sgml/doclist
@@ -55,6 +55,7 @@ hal/cortexm/kinetis/twr_k40x256/current/
 hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml
 hal/cortexm/a2fxxx/a2f200_eval/current/doc/a2f200e.sgml
 hal/cortexm/lm3s/ek_lm3s811/current/doc/ek_lm3s811.sgml
+hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml
 hal/sh/sh4_202_md/current/doc/sh4_202_md.sgml
 devs/usb/sa11x0/current/doc/usbs_sa11x0.sgml
 devs/usb/nec_upd985xx/current/doc/usbs_upd985xx.sgml
--- a/packages/ChangeLog
+++ b/packages/ChangeLog
@@ -1,3 +1,8 @@
+2013-06-12  John Dallaway  <john@dallaway.org.uk>
+
+	* ecos.db: Add STM32F4-Discovery platform HAL package and target
+	records.
+
 2013-05-2013  Uwe Kindler  <uwe_kindler@web.de>
 
 	* ecos.db: Add CAN driver entry for olcpe2294 target (Olimex
--- a/packages/NEWS
+++ b/packages/NEWS
@@ -1,3 +1,4 @@
+* STMicroelectronics STM32F4-Discovery platform HAL by John Dallaway.
 * Cortex-M STM32 F2 processor support with board support for STM3220G-EVAL
   and STM3240G-EVAL, along with many STM32 improvements. Contributed
   by eCosCentric Limited.
--- a/packages/ecos.db
+++ b/packages/ecos.db
@@ -7110,6 +7110,16 @@ package CYGPKG_HAL_CORTEXM_STM32_STM32X0
         eCos on the ST STM3220G-EVAL and STM3240G-EVAL boards."
 }
 
+package CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY {
+        alias		{ "STMicroelectronics STM32F4-Discovery HAL" hal_cortexm_stm32f4discovery }
+        directory	hal/cortexm/stm32/stm32f4discovery
+        script		hal_cortexm_stm32_stm32f4discovery.cdl
+        hardware
+        description "
+            The STM32F4-Discovery HAL package provides the platform support needed to run
+            eCos on the STMicroelectronics STM32F4-Discovery board."
+}
+
 package CYGPKG_IO_SERIAL_CORTEXM_STM32 {
         alias           { "ST STM32 serial device drivers"
                           devs_serial_cortexm_stm32 stm32_serial_driver }
@@ -7233,6 +7243,19 @@ target stm3240g_eval {
         to run eCos on the STM3240G-EVAL board."
 }
 
+target stm32f4discovery {
+        alias { "STMicroelectronics STM32F4-Discovery board" }
+        packages {
+                CYGPKG_HAL_CORTEXM
+                CYGPKG_HAL_CORTEXM_STM32
+                CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY
+                CYGPKG_DEVS_FLASH_STM32
+                CYGPKG_IO_SERIAL_CORTEXM_STM32
+        }
+        description "The stm32f4discovery target provides the packages needed
+        to run eCos on the STMicroelectronics STM32F4-Discovery board."
+}
+
 target ek-lm3s811 {
         alias      { "Stellaris EK-LM3S811 board" }
         packages   { CYGPKG_HAL_CORTEXM
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog
@@ -0,0 +1,36 @@
+2013-06-09  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_stm32_stm32f4discovery.cdl,
+	include/plf_arch.h, include/plf_intr.h, include/plf_io.h,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi,
+	src/stm32f4discovery_flash.c, src/stm32f4discovery_misc.c,
+	tests/gpio.c, misc/openocd-misc.cfg, doc/stm32f4discovery.sgml:
+	New STM32F4-Discovery platform HAL package. Derived from
+	STM32x0G-EVAL platform HAL package.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl
@@ -0,0 +1,289 @@
+##==========================================================================
+##
+##      hal_cortexm_stm32_stm32f4discovery.cdl
+##
+##      Cortex-M STM32F4-Discovery platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2013 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    jld
+## Based on:     stm32x0g_eval CDL by jlarmour
+## Date:         2013-06-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY {
+    display       "STMicroelectronics STM32F4-Discovery board HAL"
+    parent        CYGPKG_HAL_CORTEXM_STM32
+
+    requires      { CYGHWR_HAL_CORTEXM == "M4" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_F4 == "F407VG" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSE" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 8 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 336 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 2 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 7 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 1 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 4 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 2 }
+
+    include_dir   cyg/hal
+    hardware
+    doc           ref/hal-cortexm-stm32f4discovery-part.html
+    description   "
+        The STM32F4-Discovery HAL package provides the support needed to run
+        eCos on the STMicroelectronics STM32F4-Discovery board."
+
+    compile       stm32f4discovery_misc.c
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_stm32.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"STMicroelectronics STM32F4-Discovery\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    # use UART4 at PC10,11 for diagnostic I/O (named UART3 in the STM32 variant HAL)
+    implements CYGINT_HAL_STM32_UART3
+
+    implements CYGINT_HAL_FPV4_SP_D16
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"JTAG"}
+        legal_values  {"JTAG" "ROM"}
+        no_define
+        define -file system.h CYG_HAL_STARTUP
+        description   "
+            Select 'JTAG' when building applications to download into on-chip RAM
+            using the on-board ST-LINK/V2 serial wire debugging interface. Select
+            'ROM' when building an application which will be written to on-chip
+            Flash memory for immediate execution on system reset."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated    { (CYG_HAL_STARTUP == "ROM"    ) ? "cortexm_stm32f4discovery_rom"      :
+                        (CYG_HAL_STARTUP == "JTAG"   ) ? "cortexm_stm32f4discovery_jtag"     :
+                                                         "undefined" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+                display "Memory layout linker script fragment"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+                display "Memory layout header file"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_H
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    cdl_option CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK {
+        display         "Input clock frequency"
+        flavor          data
+        default_value   8000000
+        legal_values    0 to 1000000000
+        description     "Main clock input."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES {
+        display         "Flash read wait states"
+        flavor          data
+        default_value   5
+        legal_values    0 to 7
+        description     "
+            This option gives the number of wait states to use for accessing
+            the flash for reads. The correct setting for this value depends
+            on both the CPU clock (HCLK) frequency and the voltage. Consult
+            the STM32 Flash programming manual (PM0059) for appropriate
+            values for different clock speeds or voltages. The default of
+            5 reflects a supply voltage of 3.3V and HCLK of 168MHz."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH {
+        display         "Flash driver support"
+        parent          CYGPKG_IO_FLASH
+        active_if       CYGPKG_IO_FLASH
+        compile         -library=libextras.a stm32f4discovery_flash.c
+        default_value   1
+        description     "Control flash device support for STM32F4-Discovery board."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        calculated       0
+        description      "
+            The STM32F4-Discovery board has one serial port enabled. This option
+            informs the rest of the system which port will be used to connect
+            to a host running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         calculated       0
+         description      "
+            The STM32F4-Discovery board has one serial port enabled. This option
+            informs the rest of the system which port will be used for
+            diagnostic output."
+     }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option controls the default baud rate used for the
+            console connection."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "Debug serial port baud rate"
+        flavor        data
+        calculated    CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+            Global build options including control over
+            compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_OPTIONS {
+        display "STM32F4-Discovery HAL build options"
+        flavor  none
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building this HAL package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "-Werror" }
+            description   "
+                This option modifies the set of compiler flags
+                for building this HAL. These flags are used
+                in addition to the set of global flags."
+        }
+        cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags
+                for building this HAL. These flags are
+                removed from the set of global flags if
+                present."
+        }
+    }
+
+    cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_TESTS {
+        display "STM32F4-Discovery tests"
+        flavor  data
+        no_define
+        calculated { "tests/gpio" }
+        description   "
+            This option specifies the set of tests for the STM32F4-Discovery HAL."
+    }
+
+}
+
+# EOF hal_cortexm_stm32_stm32f4discovery.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml
@@ -0,0 +1,215 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     stm32f4discovery.sgml                                       -->
+<!--                                                                 -->
+<!--     STM32F4-Discovery platform HAL documentation                -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2003, 2004, 2008, 2013 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   jld                                                -->
+<!-- Based on:    M5272C3 documentation by bartv                     -->
+<!-- Date:        2013-06-07                                         -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<part id="hal-cortexm-stm32f4discovery-part"><title>STMicroelectronics STM32F4-Discovery Board Support</title>
+
+<refentry id="cortexm-stm32f4discovery">
+  <refmeta>
+    <refentrytitle>Overview</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>eCos Support for the STMicroelectronics STM32F4-Discovery Board</refname>
+    <refpurpose>Overview</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="cortexm-stm32f4discovery-description"><title>Description</title>
+    <para>
+The STMicroelectronics STM32F4-Discovery board has an STM32F407VGT6 Cortex-M4F processor,
+192KiB of on-chip SRAM, 1MiB of on-chip flash memory, plus motion and audio sensors, an
+audio DAC and a connector for the on-chip USB peripheral. The board also
+features an ST-LINK/V2 serial wire debug (SWD) interface.
+    </para>
+    <para>
+For typical eCos development the ST-LINK/V2 interface is connected via USB to a host
+computer running the OpenOCD on-chip debug tool. OpenOCD provides a GDB server enabling
+the download and debuging of eCos applications via the GDB debugger.
+    </para>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-hardware"><title>Supported Hardware</title>
+    <para>
+By default, eCos will use the 128KiB of contiguous on-chip SRAM, accessible
+at location 0x20000000. On-chip flash memory at 0x08000000 can be optionally
+used for bootable application code. A further 64KiB of core coupled memory (CCM)
+is mapped to location 0x10000000. This memory is not used by eCos but may be used
+for application-defined static data structures such as thread stacks which require no
+initialization other than that performed during eCos startup and application
+execution. Data structures may be assigned to the <varname>.ccm</varname> section
+within CCM memory using the eCos <varname>CYGBLD_ATTRIB_SECTION</varname> macro. For example:
+    </para>
+    <programlisting>char thread_stack[4096] CYGBLD_ATTRIB_SECTION(".ccm");</programlisting>
+    <para>
+There is a serial driver <varname>CYGPKG_IO_SERIAL_CORTEXM_STM32</varname>
+which supports all on-chip UARTs. However, there are no RS232 drivers or
+serial connectors on the board. STM32 UART4 (named UART3 in the eCos serial driver) is
+enabled for use as a diagnostics channel.
+    </para>
+    <para>
+The GPIO ports are enabled and manipulated only as needed
+to access UART4, the LEDs and the push button. eCos does not
+enable the remaining on-chip peripherals.
+    </para>
+  </refsect1>
+  <refsect1 id="cortexm-stm32f4discovery-tools"><title>Tools</title>
+    <para>
+The STM32F4-Discovery board port is intended to work with GNU tools
+configured for an arm-eabi target. The original porting work was performed using
+binutils 2.18.50.20080513, arm-eabi-gcc 4.3.2, arm-eabi-gdb 7.4.1 and OpenOCD 0.6.1.
+    </para>
+  </refsect1>
+</refentry>
+
+<refentry id="cortexm-stm32f4discovery-setup">
+  <refmeta>
+    <refentrytitle>Setup</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>Setup</refname>
+    <refpurpose>Preparing for eCos Development with the STM32F4-Discovery board</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="cortexm-stm32f4discovery-overview"><title>Overview</title>
+    <para>
+In a typical development environment the STM32F4-Discovery board is halted
+on reset using OpenOCD communicating via the ST-LINK/V2 SWD interface. eCos
+applications are configured for JTAG startup, then downloaded to the board
+and executed via the arm-eabi-gdb debugger.
+    </para>
+    <para>
+OpenOCD may be configured for use with the STM32F4-Discovery board using the
+board configuration script <filename>stm32f4discovery.cfg</filename> provided with the tool.
+It is also necessary to define a handler for GDB attach events which will halt the board. A
+suitable OpenOCD script is provided at <filename>misc/openocd-misc.cfg</filename> in the
+STM32F4-Discovery platform HAL package. Both scripts may be specified on the OpenOCD
+command line.
+    </para>
+  </refsect1>
+  <refsect1 id="cortexm-stm32f4discovery-config-diagnostic"><title>Diagnostic output</title>
+    <para>
+For diagnostic output, a SparkFun FTDI 3.3v Basic Breakout board or similar
+may be connected to UART4 of the STM32F4-Discovery board using jumper wires as follows:
+    </para>
+    <informaltable frame="all">
+        <tgroup cols="3" colsep="1" rowsep="1" align="left">
+            <thead>
+	        <row>
+                    <entry>Function</entry>
+                    <entry>STM32F4-Discovery header</entry>
+                    <entry>SparkFun FTDI breakout board socket</entry>
+                </row>
+            </thead>
+            <tbody>
+	        <row>
+                    <entry>UART4 Tx</entry>
+                    <entry>PC10</entry>
+                    <entry>RXI</entry>
+                </row>
+                <row>
+                    <entry>Ground</entry>
+                    <entry>GND</entry>
+                    <entry>GND</entry>
+                </row>
+            </tbody>
+        </tgroup>
+    </informaltable>
+    <para>
+The UART is configured at 115200 baud by default and runs with 8 bits,
+no parity, and 1 stop bit. The baud rate can be changed via the
+configuration option <varname>CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD</varname>.
+    </para>
+  </refsect1>
+</refentry>
+
+<refentry id="cortexm-stm32f4discovery-config">
+  <refmeta>
+    <refentrytitle>Configuration</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>Configuration</refname>
+    <refpurpose>Platform-specific Configuration Options</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-overview"><title>Overview</title>
+    <para>
+The STM32F4-Discovery platform HAL package is loaded automatically when eCos is
+configured for an STM32F4-Discovery target. It should never be necessary to load
+this package explicitly. Unloading of the package should only occur as a result
+of switching target hardware.
+    </para>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-startup"><title>Startup</title>
+    <para>
+The STM32F4-Discovery platform HAL package supports two startup types which may be
+selected using the configuration option <varname>CYG_HAL_STARTUP</varname>:
+    </para>
+    <variablelist>
+      <varlistentry>
+        <term>JTAG</term>
+        <listitem><para>
+This is the startup type which is normally used during application
+development. <application>arm-eabi-gdb</application> is used to download a JTAG
+startup application into memory via OpenOCD and the ST-LINK/V2 SWD debug interface.
+eCos startup code will perform all necessary hardware initialization.
+        </para></listitem>
+      </varlistentry>
+      <varlistentry>
+        <term>ROM</term>
+        <listitem><para>
+This startup type can be used for finished applications which will
+be programmed into flash at location 0x08000000. It can also be used for
+debugging larger applications which do not fit in available SRAM. The
+application must be programmed to flash using the ST-LINK tool before debugging commences.
+eCos startup code will perform all necessary hardware initialization.
+        </para></listitem>
+      </varlistentry>
+    </variablelist>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-flash"><title>Flash Driver</title>
+    <para>
+The platform HAL package contains flash driver support. This support may be
+activated by loading the eCos flash I/O infrastructure package <varname>CYGPKG_IO_FLASH</varname>.
+    </para>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-clock"><title>System Clock</title>
+    <para>
+By default the system clock interrupts once every 10ms, corresponding
+to a 100Hz clock. This period can be modified using the configuration option
+<varname>CYGNUM_HAL_RTC_PERIOD</varname>.
+    </para>
+  </refsect1>
+</refentry>
+
+</part>
+
+<!-- EOF stm32f4discovery.sgml -->
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi
@@ -0,0 +1,43 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram   : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    USER_SECTION (ccm, ccm, 0x10000000, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, hal_virtual_vector_table_end, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi
@@ -0,0 +1,43 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram   : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    USER_SECTION (ccm, ccm, 0x10000000, LMA_EQ_VMA)
+    SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, hal_virtual_vector_table_end, FOLLOWING (.got))
+    SECTION_data (ram, ALIGN( 0x8), FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jld
+// Based on:    stm32x0g_eval overrides by nickg
+// Date:        2013-06-06
+// Purpose:     STM32F4-Discovery platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jld
+// Based on:    stm32x0g_eval overrides by nickg
+// Date:        2013-06-06
+// Purpose:     STM32F4-Discovery platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h
@@ -0,0 +1,67 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jld
+// Date:        2013-06-06
+// Purpose:     STM32F4-Discovery platform specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+// User LEDs and button
+
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED1 CYGHWR_HAL_STM32_PIN_OUT( D, 12, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED2 CYGHWR_HAL_STM32_PIN_OUT( D, 13, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED3 CYGHWR_HAL_STM32_PIN_OUT( D, 14, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED4 CYGHWR_HAL_STM32_PIN_OUT( D, 15, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_BTN1 CYGHWR_HAL_STM32_PIN_IN( A, 0, NONE )
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg
@@ -0,0 +1,54 @@
+##==========================================================================
+##
+##      openocd-misc.cfg
+##
+##      Cortex-M STM32F4-Discovery OpenOCD miscellaneous definitions
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2013 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    jld
+## Date:         2013-06-09
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+gdb_memory_map disable
+stm32f4x.cpu configure -event gdb-attach {
+    reset init
+}
+
+# EOF openocd-misc.cfg
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c
@@ -0,0 +1,65 @@
+/*==========================================================================
+//
+//      stm32f4discovery_flash.c
+//
+//      Cortex-M4 STM32F4-Discovery Flash setup
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jld
+// Based on:     stm32x0g_eval flash setup by jlarmour
+// Date:         2013-06-06
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <cyg/io/flash_dev.h>
+#include <cyg/io/stm32_flash.h>
+
+CYG_FLASH_DRIVER(hal_stm32_flash,
+                 &cyg_stm32_flash_funs,
+                 0,
+                 0x08000000,
+                 0,
+                 0,
+                 0,
+                 &hal_stm32_flash_priv
+);
+
+//--------------------------------------------------------------------------
+// EOF stm32f4discovery_flash.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c
@@ -0,0 +1,147 @@
+/*==========================================================================
+//
+//      stm32f4discovery_misc.c
+//
+//      Cortex-M4 STM32F4-Discovery HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011, 2012, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jld
+// Based on:     stm32x0g_eval misc setup by jlarmour
+// Date:         2013-06-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_if.h>
+
+//==========================================================================
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+#if (CYGNUM_CALL_IF_TABLE_SIZE > 64)
+// We force a compilation error for this fatal condition since run-time asserts
+// may not be enabled for the build.
+#error "The CALL_IF_TABLE_SIZE pre-allocation in the linker scripts for this platform need to be updated"
+#endif
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void hal_system_init( void )
+{
+    CYG_ADDRESS base;
+
+    // Enable CCM clock and any required GPIO ports in RCC
+    base = CYGHWR_HAL_STM32_RCC;
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB1ENR,
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) );
+
+    // Set unused lines on enabled GPIO ports to input with pull down
+
+    // GPIO Port A - setup PA0 for button, PA9 for LED, PA13,14 for SWD
+    base = CYGHWR_HAL_STM32_GPIOA;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x82A8AAA8 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x28040000 );
+
+    // GPIO Port C - setup PC10,11 for RS232 (UART4)
+    base = CYGHWR_HAL_STM32_GPIOC;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAA0AAAAA );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00A00000 );
+
+    // GPIO Port D - setup PD5,12,13,14,15 for LEDs
+    base = CYGHWR_HAL_STM32_GPIOD;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00AAA2AA );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x55000400 );
+
+    // Enable flash prefetch buffer, cacheability and set latency to 2 wait states
+    // Latency has to be set before clock is switched to a higher speed
+    {
+        cyg_uint32 acr;
+
+        base = CYGHWR_HAL_STM32_FLASH;
+
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES);
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+    }
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+#ifdef CYGDBG_USE_ASSERTS
+    __externC char __sram_data_start[];
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    // Check the number of VSRs matches the linker script. We can do this
+    // because we intend the VV table to follow the VSR table with no gaps.
+    CYG_ASSERT( (char*)&hal_virtual_vector_table[0] - (char*)&hal_vsr_table >= CYGNUM_HAL_VSR_COUNT*4,
+                "VSR table size does not match" );
+    // Now check the declared start of SRAM data follows the VV table end
+    CYG_ASSERT( (__sram_data_start - (char*)&hal_virtual_vector_table[0]) >= CYGNUM_CALL_IF_TABLE_SIZE*4,
+                "VV table size does not match sram space" );
+#else
+    // Check the VSR table fits below declared start of SRAM data
+    CYG_ASSERT( (__sram_data_start - (char*)&hal_vsr_table[0]) >= CYGNUM_HAL_VSR_COUNT*4,
+                "VSR table size does not match" );
+#endif
+}
+
+//==========================================================================
+// EOF stm32f4discovery_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c
@@ -0,0 +1,73 @@
+/*=============================================================================
+//
+//      gpio.c
+//
+//      Test for STM32F4-Discovery GPIO
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jld
+// Date:         2013-06-07
+//              
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <cyg/infra/testcase.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/var_io.h>
+
+externC void cyg_start(void) {
+    int b, n;
+    CYG_TEST_INIT();
+    CYG_TEST_INFO( "Starting STM32F4-Discovery GPIO test" );
+    CYG_TEST_INFO( "Press and hold user button for slow LED count" );
+    for ( n = 0; n < 0x100; n++ ) {
+    	// display least significant 4 bits of count on user LEDs
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED1, 0 != (n & 0x1) );
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED2, 0 != (n & 0x2) );
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED3, 0 != (n & 0x4) );
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED4, 0 != (n & 0x8) );
+        // extend delay from 125ms to 500ms when user button pressed
+        CYGHWR_HAL_STM32_GPIO_IN( CYGHWR_HAL_STM32F4DISCOVERY_BTN1, &b );
+        HAL_DELAY_US( 125000 * (1 + ( (b & 1) * 3) ) );
+    }
+    CYG_TEST_PASS_FAIL( 1, "STM32F4-Discovery GPIO test" );
+    CYG_TEST_FINISH( "STM32F4-Discovery GPIO test" );
+}
+
+//=============================================================================
+// EOF gpio.c