changeset 3202:b1adab1ffd9b

Add CYGBLD_ATTRIB_NO_INLINE (suggested by Jifl)
author vae
date Fri, 22 Feb 2013 19:38:44 +0000
parents f5d2adaa8595
children 28a7b8d2b8fe
files packages/devs/spi/freescale/dspi/current/ChangeLog packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl packages/devs/spi/freescale/dspi/current/tests/spi_loopback.c packages/hal/misc/freescale/edma/current/ChangeLog packages/hal/misc/freescale/edma/current/include/freescale_edma.h packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c packages/infra/current/ChangeLog packages/infra/current/include/cyg_type.h
diffstat 9 files changed, 536 insertions(+), 400 deletions(-) [+]
line wrap: on
line diff
--- a/packages/devs/spi/freescale/dspi/current/ChangeLog
+++ b/packages/devs/spi/freescale/dspi/current/ChangeLog
@@ -1,3 +1,11 @@
+2013-02-06  Stefan Singer <stefan.singer@freescale.com>
+		+ Ilija Kocho <ilijak@siva.com.mk>
+
+	* enhanced endianness support for devices with big and little endian
+	* added support for MPC5xxx in addition to Kinetis
+	* extended support for up to 8 DSPIs
+	(see Bugzilla 1001752).
+
 2012-12-28  Ilija Kocho <ilijak@siva.com.mk>
 
 	* cdl/spi_freescale_dspi.cdl, src/spi_freescale_dspi.c:
--- a/packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl
+++ b/packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl
@@ -55,7 +55,7 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS
 
     parent        CYGPKG_IO_SPI
     active_if     CYGPKG_IO_SPI
-    requires      CYGPKG_HAL_CORTEXM_KINETIS
+    requires      CYGPKG_HAL_CORTEXM_KINETIS || CYGPKG_HAL_POWERPC_MPC5xxx
 
     hardware
     include_dir   cyg/io
@@ -115,7 +115,7 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS
     }
 
 
-    for { set ::spibus 0 } { $::spibus < 3 } { incr ::spibus } {
+    for { set ::spibus 0 } { $::spibus < 8 } { incr ::spibus } {
 
         cdl_interface CYGINT_DEVS_SPI_FREESCALE_DSPI[set ::spibus] {
             display "Number of devices using DSPI bus [set ::spibus]"
@@ -126,6 +126,7 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS
             description "Enable DSPI bus [set :: spibus]."
             flavor bool
             default_value CYGINT_DEVS_SPI_FREESCALE_DSPI[set ::spibus]
+            active_if CYGINT_DEVS_SPI_FREESCALE_DSPI[set ::spibus]
 
             implements CYGINT_HAL_DMA
             requires   CYGPKG_HAL_FREESCALE_EDMA
@@ -295,7 +296,7 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS
                 flavor data
                 requires CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_ISR_PRI_SP
                 calculated CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_ISR_PRI_SP
-                description "Interrupt priority set-point is provtded bu HAL"
+                description "Interrupt priority set-point is provided by HAL"
             }
         }
     }
--- a/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl
+++ b/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2011 Free Software Foundation, Inc.
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -56,29 +56,151 @@
 //-----------------------------------------------------------------------------
 // Instantiate the bus state data structures.
 
+// Some auxiliary macros
 
-// DSPI0 BUS =================================================================
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+#define EDMA_TCD_SADDR(__bus) \
+        .saddr = (void *)(((unsigned int)&CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P->popr) + 3)
+#else // AKA Little endian
+#define EDMA_TCD_SADDR(__bus) \
+        .saddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P->popr
+#endif
+
+#define DSPI_EDMA_CHAN_SET(__bus) \
+static volatile cyg_uint32 \
+dspi ## __bus ## _pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _PUSHQUE_SIZE+4] \
+PUSHQUE_ALIGN EDMA_RAM_BUF_SECTION;                                                   \
+                                                                                      \
+static const cyghwr_hal_freescale_dma_chan_set_t dspi ## __bus ## _dma_chan[2] = \
+{                                                                                \
+    {                                                                            \
+        .dma_src = FREESCALE_DMAMUX_SRC_SPI ## __bus ## _TX                      \
+        | FREESCALE_DMAMUX_CHCFG_ENBL_M,                                         \
+        .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _TX_DMA_CHAN,   \
+        .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _TX_DMA_PRI,      \
+    },                                                                           \
+    {                                                                            \
+        .dma_src = FREESCALE_DMAMUX_SRC_SPI ## __bus ## _RX                      \
+        | FREESCALE_DMAMUX_CHCFG_ENBL_M,                                         \
+        .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _RX_DMA_CHAN,   \
+        .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _RX_DMA_PRI,      \
+    }                                                                            \
+};                                                                               \
+                                                                                 \
+static cyghwr_hal_freescale_dma_set_t dspi ## __bus ## _dma_set = {              \
+    .chan_p = dspi ## __bus ## _dma_chan,                                        \
+    .chan_n = 2                                                                  \
+};                                                                               \
+                                                                                 \
+static const cyghwr_hal_freescale_edma_tcd_t dspi ## __bus ## _dma_tcd_tx_ini =  \
+{                                                                                \
+        .saddr =  (cyg_uint32 *) dspi ## __bus ## _pushque,                      \
+        .soff = 4,                                                               \
+        .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |         \
+                FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |         \
+                FREESCALE_EDMA_ATTR_SMOD(0) |                                    \
+                FREESCALE_EDMA_ATTR_DMOD(0),                                     \
+        .daddr = (cyg_uint32 *)                                                  \
+                 &CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P->pushr,           \
+        .doff = 0,                                                               \
+        .nbytes.mlno = 4,                                                        \
+        .slast = 0,                                                              \
+        .citer.elinkno = 1,                                                      \
+        .dlast_sga.dlast = 0,                                                    \
+        .biter.elinkno = 1,                                                      \
+        .csr = DSPI_DMA_BANDWIDTH                                                \
+};                                                                               \
+                                                                                 \
+static const cyghwr_hal_freescale_edma_tcd_t dspi ## __bus ## _dma_tcd_rx_ini =  \
+{                                                                                \
+       EDMA_TCD_SADDR(__bus),                                                    \
+        .soff = 0,                                                               \
+        .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |         \
+                FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |         \
+                FREESCALE_EDMA_ATTR_SMOD(0) |                                    \
+                FREESCALE_EDMA_ATTR_DMOD(0),                                     \
+        .daddr = NULL,                                                           \
+        .doff = 4,                                                               \
+        .nbytes.mlno = 4,                                                        \
+        .slast = 0,                                                              \
+        .citer.elinkno = 1,                                                      \
+        .dlast_sga.dlast = 0,                                                    \
+        .biter.elinkno = 1,                                                      \
+        .csr = DSPI_DMA_BANDWIDTH                                                \
+}
+
+#define DSPI_EDMA_SET_P_YES(__bus)  .dma_set_p = &dspi ## __bus ## _dma_set
+#define DSPI_EDMA_SET_P_NULL(__bus)  .dma_set_p = NULL
+
+#define DSPI_EDMA_TCD_YES(__bus)                                      \
+    .tx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P->                    \
+        tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _TX_DMA_CHAN], \
+    .rx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P->                    \
+    tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _RX_DMA_CHAN],     \
+    .tx_dma_tcd_ini_p = &dspi ## __bus ## _dma_tcd_tx_ini,            \
+    .rx_dma_tcd_ini_p = &dspi ## __bus ## _dma_tcd_rx_ini,            \
+    .pushque_p = dspi ## __bus ## _pushque
+
+#define DSPI_EDMA_TCD_NULL(__bus) \
+    .tx_dma_tcd_p = NULL,         \
+    .rx_dma_tcd_p = NULL,         \
+    .tx_dma_tcd_ini_p = NULL,     \
+    .rx_dma_tcd_ini_p = NULL,     \
+    .pushque_p = NULL
+
+// End DSPI_EDMA
+
+#define DSPI_BUS_SETUP(__bus) \
+static const cyg_spi_freescale_dspi_bus_setup_t dspi ## __bus ## _setup = {   \
+    .dspi_p          = CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P,          \
+    .intr_num        = CYGNUM_HAL_INTERRUPT_SPI ## __bus,                     \
+    .intr_prio       = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _ISR_PRI,   \
+    .spi_pin_list_p  = spi ## __bus ## _pins,                                 \
+    .cs_pin_list_p   = spi ## __bus ## _cs_pins,                              \
+    .cs_pin_num      = sizeof(spi ## __bus ## _cs_pins)/                      \
+                       sizeof(spi ## __bus ## _cs_pins[0]),                   \
+    .mcr_opt         = CYGHWR_FREESCALE_DSPI ## __bus ## _MCR_PCSSE |         \
+                       FREESCALE_DSPI_MCR_PCSIS(                              \
+                          CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _PCSIS), \
+    DSPI ## __bus ## _EDMA_SET_P                                              \
+}
+
+#define DSPI_BUS(__bus) \
+cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus ## __bus = {                 \
+    .spi_bus.spi_transaction_begin    = dspi_transaction_begin,            \
+    .spi_bus.spi_transaction_transfer = dspi_transaction_transfer,         \
+    .spi_bus.spi_transaction_tick     = dspi_transaction_tick,             \
+    .spi_bus.spi_transaction_end      = dspi_transaction_end,              \
+    .spi_bus.spi_get_config           = dspi_get_config,                   \
+    .spi_bus.spi_set_config           = dspi_set_config,                   \
+    .setup_p                          = &dspi ## __bus ## _setup,          \
+    DSPI ## __bus ## _EDMA_TCD,                                            \
+    .pushque_n = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _PUSHQUE_SIZE, \
+    .txfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE,                  \
+    .rxfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE                   \
+}
+
+#define DSPI_BUS_PINS(__bus) \
+static const cyg_uint32 spi ## __bus ## _pins[] = { \
+    CYGHWR_IO_FREESCALE_SPI ## __bus ## _PIN_SIN,   \
+    CYGHWR_IO_FREESCALE_SPI ## __bus ## _PIN_SOUT,  \
+    CYGHWR_IO_FREESCALE_SPI ## __bus ## _PIN_SCK    \
+}
+
+// DSPI BUS Instances =======================================================
+
+// DSPI BUS 0 ================================================================
 #ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI0
 
 #define  CYGBLD_DSPI0_TCD_SECTION \
     CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI0_TCD_SECTION)
 
-extern cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus0;
-
-// Pinonomy -------------------------------------------------------------------
-
 #ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI0_PCSS
 #define CYGHWR_FREESCALE_DSPI0_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
 #else
 #define CYGHWR_FREESCALE_DSPI0_MCR_PCSSE 0
 #endif
 
-static const cyg_uint32 spi0_pins[] = {
-    CYGHWR_IO_FREESCALE_SPI0_PIN_SIN,
-    CYGHWR_IO_FREESCALE_SPI0_PIN_SOUT,
-    CYGHWR_IO_FREESCALE_SPI0_PIN_SCK
-};
-
 // SPI chip select pins.
 static const cyg_uint32 spi0_cs_pins[] = {
 #ifdef CYGHWR_FREESCALE_DSPI0_CS0
@@ -102,136 +224,32 @@ static const cyg_uint32 spi0_cs_pins[] =
 };
 
 #ifdef CYGINT_DEVS_SPI_DSPI0_USES_DMA
-static volatile
-cyg_uint32 dspi0_pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI0_PUSHQUE_SIZE+4] PUSHQUE_ALIGN;
-
-static cyghwr_hal_freescale_dma_chan_set_t dspi0_dma_chan[] =
-{
-    {
-        .dma_src = FREESCALE_DMAMUX_SRC_SPI0_TX
-        | FREESCALE_DMAMUX_CHCFG_ENBL_M,
-        .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI0_TX_DMA_CHAN,
-        .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI0_TX_DMA_PRI,
-    },
-    {
-        .dma_src = FREESCALE_DMAMUX_SRC_SPI0_RX
-        | FREESCALE_DMAMUX_CHCFG_ENBL_M,
-        .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI0_RX_DMA_CHAN,
-        .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI0_RX_DMA_PRI,
-    }
-};
-
-static cyghwr_hal_freescale_dma_set_t dspi0_dma_set = {
-    .chan_p = dspi0_dma_chan,
-    .chan_n = 2
-};
-
-static const cyghwr_hal_freescale_edma_tcd_t dspi0_dma_tcd_tx_ini =
-{
-        .saddr =  (cyg_uint32 *) dspi0_pushque,
-        .soff = 4,
-        .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_SMOD(0) |
-                FREESCALE_EDMA_ATTR_DMOD(0),
-        .daddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI0_P->pushr,
-        .doff = 0,
-        .nbytes.mlno = 4,
-        .slast = 0,
-        .citer.elinkno = 1,
-        {.dlast = 0},
-        .biter.elinkno = 1,
-        .csr = DSPI_DMA_BANDWIDTH
-};
-
-
-static const cyghwr_hal_freescale_edma_tcd_t dspi0_dma_tcd_rx_ini =
-{
-        .saddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI0_P->popr,
-        .soff = 0,
-        .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_SMOD(0) |
-                FREESCALE_EDMA_ATTR_DMOD(0),
-        .daddr = NULL,
-        .doff = 4,
-        .nbytes.mlno = 4,
-        .slast = 0,
-        .citer.elinkno = 1,
-        {.dlast = 0},
-        .biter.elinkno = 1,
-        .csr = DSPI_DMA_BANDWIDTH
-};
-
+  DSPI_EDMA_CHAN_SET(0);
+# define DSPI0_EDMA_SET_P DSPI_EDMA_SET_P_YES(0)
+# define DSPI0_EDMA_TCD DSPI_EDMA_TCD_YES(0)
+#else
+# define DSPI0_EDMA_SET_P DSPI_EDMA_SET_P_NULL(0)
+# define DSPI0_EDMA_TCD DSPI_EDMA_TCD_NULL(0)
 #endif // CYGINT_DEVS_SPI_DSPI0_USES_DMA
 
-static const cyg_spi_freescale_dspi_bus_setup_t dspi0_setup = {
-    .dspi_p          = CYGADDR_IO_SPI_FREESCALE_DSPI0_P,
-#ifdef CYGINT_DEVS_SPI_DSPI0_USES_DMA
-    .dma_set_p       = &dspi0_dma_set,
-#else
-    .dma_set_p       = NULL,
-#endif
-    .intr_num        = CYGNUM_HAL_INTERRUPT_SPI0,
-    .intr_prio       = CYGNUM_DEVS_SPI_FREESCALE_DSPI0_ISR_PRI,
-    .spi_pin_list_p  = spi0_pins,
-    .cs_pin_list_p   = spi0_cs_pins,
-    .cs_pin_num      = sizeof(spi0_cs_pins)/sizeof(spi0_cs_pins[0]),
-    .mcr_opt         = CYGHWR_FREESCALE_DSPI0_MCR_PCSSE |
-                       FREESCALE_DSPI_MCR_PCSIS(CYGHWR_DEVS_SPI_FREESCALE_DSPI0_PCSIS)
-};
+DSPI_BUS_PINS(0);
+DSPI_BUS_SETUP(0);
+DSPI_BUS(0);
 
-cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus0 = {
-    .spi_bus.spi_transaction_begin    = dspi_transaction_begin,
-    .spi_bus.spi_transaction_transfer = dspi_transaction_transfer,
-    .spi_bus.spi_transaction_tick     = dspi_transaction_tick,
-    .spi_bus.spi_transaction_end      = dspi_transaction_end,
-    .spi_bus.spi_get_config           = dspi_get_config,
-    .spi_bus.spi_set_config           = dspi_set_config,
-    .setup_p                          = &dspi0_setup,
-#ifdef CYGINT_DEVS_SPI_DSPI0_USES_DMA
-    .tx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P->
-                     tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI0_TX_DMA_CHAN],
-    .rx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P->
-    tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI0_RX_DMA_CHAN],
-    .tx_dma_tcd_ini_p = &dspi0_dma_tcd_tx_ini,
-    .rx_dma_tcd_ini_p = &dspi0_dma_tcd_rx_ini,
-    .pushque_p = dspi0_pushque,
-#else // CYGINT_DEVS_SPI_DSPI0_USES_DMA
-    .tx_dma_tcd_p = NULL,
-    .rx_dma_tcd_p = NULL,
-    .tx_dma_tcd_ini_p = NULL,
-    .rx_dma_tcd_ini_p = NULL,
-    .pushque_p = NULL,
-#endif // CYGINT_DEVS_SPI_DSPI0_USES_DMA
-    .pushque_n = CYGNUM_DEVS_SPI_FREESCALE_DSPI0_PUSHQUE_SIZE,
-    .txfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE,
-    .rxfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE
-};
-#endif
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI0
 
-// DSPI1 BUS =================================================================
+// DSPI BUS 1 ================================================================
 #ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI1
 
 #define  CYGBLD_DSPI1_TCD_SECTION \
     CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI1_TCD_SECTION)
 
-extern cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1;
-
-// Pinonomy -------------------------------------------------------------------
-
 #ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI1_PCSS
 #define CYGHWR_FREESCALE_DSPI1_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
 #else
 #define CYGHWR_FREESCALE_DSPI1_MCR_PCSSE 0
 #endif
 
-static const cyg_uint32 spi1_pins[] = {
-    CYGHWR_IO_FREESCALE_SPI1_PIN_SIN,
-    CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT,
-    CYGHWR_IO_FREESCALE_SPI1_PIN_SCK
-};
-
 // SPI chip select pins.
 static const cyg_uint32 spi1_cs_pins[] = {
 #ifdef CYGHWR_FREESCALE_DSPI1_CS0
@@ -255,137 +273,32 @@ static const cyg_uint32 spi1_cs_pins[] =
 };
 
 #ifdef CYGINT_DEVS_SPI_DSPI1_USES_DMA
-static volatile
-cyg_uint32 dspi1_pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI1_PUSHQUE_SIZE+4]
-           PUSHQUE_ALIGN EDMA_RAM_BUF_SECTION;
-
-static const cyghwr_hal_freescale_dma_chan_set_t dspi1_dma_chan[2] =
-{
-    {
-        .dma_src = FREESCALE_DMAMUX_SRC_SPI1_TX
-        | FREESCALE_DMAMUX_CHCFG_ENBL_M,
-        .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI1_TX_DMA_CHAN,
-        .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI1_TX_DMA_PRI,
-    },
-    {
-        .dma_src = FREESCALE_DMAMUX_SRC_SPI1_RX
-        | FREESCALE_DMAMUX_CHCFG_ENBL_M,
-        .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI1_RX_DMA_CHAN,
-        .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI1_RX_DMA_PRI,
-    }
-};
-
-static cyghwr_hal_freescale_dma_set_t dspi1_dma_set = {
-    .chan_p = dspi1_dma_chan,
-    .chan_n = 2
-};
-
-static const cyghwr_hal_freescale_edma_tcd_t dspi1_dma_tcd_tx_ini =
-{
-        .saddr =  (cyg_uint32 *) dspi1_pushque,
-        .soff = 4,
-        .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_SMOD(0) |
-                FREESCALE_EDMA_ATTR_DMOD(0),
-        .daddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI1_P->pushr,
-        .doff = 0,
-        .nbytes.mlno = 4,
-        .slast = 0,
-        .citer.elinkno = 1,
-        {.dlast = 0},
-        .biter.elinkno = 1,
-        .csr = DSPI_DMA_BANDWIDTH
-};
-
-
-static const cyghwr_hal_freescale_edma_tcd_t dspi1_dma_tcd_rx_ini =
-{
-        .saddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI1_P->popr,
-        .soff = 0,
-        .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_SMOD(0) |
-                FREESCALE_EDMA_ATTR_DMOD(0),
-        .daddr = NULL,
-        .doff = 4,
-        .nbytes.mlno = 4,
-        .slast = 0,
-        .citer.elinkno = 1,
-        {.dlast = 0},
-        .biter.elinkno = 1,
-        .csr = DSPI_DMA_BANDWIDTH
-};
-
+  DSPI_EDMA_CHAN_SET(1);
+# define DSPI1_EDMA_SET_P DSPI_EDMA_SET_P_YES(1)
+# define DSPI1_EDMA_TCD DSPI_EDMA_TCD_YES(1)
+#else
+# define DSPI1_EDMA_SET_P DSPI_EDMA_SET_P_NULL(1)
+# define DSPI1_EDMA_TCD DSPI_EDMA_TCD_NULL(1)
 #endif // CYGINT_DEVS_SPI_DSPI1_USES_DMA
 
-static const cyg_spi_freescale_dspi_bus_setup_t dspi1_setup = {
-    .dspi_p          = CYGADDR_IO_SPI_FREESCALE_DSPI1_P,
-#ifdef CYGINT_DEVS_SPI_DSPI1_USES_DMA
-    .dma_set_p       = &dspi1_dma_set,
-#else
-    .dma_set_p       = NULL,
-#endif
-    .intr_num        = CYGNUM_HAL_INTERRUPT_SPI1,
-    .intr_prio       = CYGNUM_DEVS_SPI_FREESCALE_DSPI1_ISR_PRI,
-    .spi_pin_list_p  = spi1_pins,
-    .cs_pin_list_p   = spi1_cs_pins,
-    .cs_pin_num      = sizeof(spi1_cs_pins)/sizeof(spi1_cs_pins[0]),
-    .mcr_opt         = CYGHWR_FREESCALE_DSPI1_MCR_PCSSE |
-                       FREESCALE_DSPI_MCR_PCSIS(CYGHWR_DEVS_SPI_FREESCALE_DSPI1_PCSIS)
-};
+DSPI_BUS_PINS(1);
+DSPI_BUS_SETUP(1);
+DSPI_BUS(1);
 
-cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1 = {
-    .spi_bus.spi_transaction_begin    = dspi_transaction_begin,
-    .spi_bus.spi_transaction_transfer = dspi_transaction_transfer,
-    .spi_bus.spi_transaction_tick     = dspi_transaction_tick,
-    .spi_bus.spi_transaction_end      = dspi_transaction_end,
-    .spi_bus.spi_get_config           = dspi_get_config,
-    .spi_bus.spi_set_config           = dspi_set_config,
-    .setup_p                          = &dspi1_setup,
-#ifdef CYGINT_DEVS_SPI_DSPI1_USES_DMA
-    .tx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P->
-                     tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI1_TX_DMA_CHAN],
-    .rx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P->
-    tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI1_RX_DMA_CHAN],
-    .tx_dma_tcd_ini_p = &dspi1_dma_tcd_tx_ini,
-    .rx_dma_tcd_ini_p = &dspi1_dma_tcd_rx_ini,
-    .pushque_p = dspi1_pushque,
-#else // CYGINT_DEVS_SPI_DSPI1_USES_DMA
-    .tx_dma_tcd_p = NULL,
-    .rx_dma_tcd_p = NULL,
-    .tx_dma_tcd_ini_p = NULL,
-    .rx_dma_tcd_ini_p = NULL,
-    .pushque_p = NULL,
-#endif // CYGINT_DEVS_SPI_DSPI1_USES_DMA
-    .pushque_n = CYGNUM_DEVS_SPI_FREESCALE_DSPI1_PUSHQUE_SIZE,
-    .txfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE,
-    .rxfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE
-};
-#endif
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI1
 
-// DSPI2 BUS =================================================================
+// DSPI BUS 2 ================================================================
 #ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI2
 
 #define  CYGBLD_DSPI2_TCD_SECTION \
     CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI2_TCD_SECTION)
 
-extern cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus2;
-
-// Pinonomy -------------------------------------------------------------------
-
 #ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI2_PCSS
 #define CYGHWR_FREESCALE_DSPI2_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
 #else
 #define CYGHWR_FREESCALE_DSPI2_MCR_PCSSE 0
 #endif
 
-static const cyg_uint32 spi2_pins[] = {
-    CYGHWR_IO_FREESCALE_SPI2_PIN_SIN,
-    CYGHWR_IO_FREESCALE_SPI2_PIN_SOUT,
-    CYGHWR_IO_FREESCALE_SPI2_PIN_SCK
-};
-
 // SPI chip select pins.
 static const cyg_uint32 spi2_cs_pins[] = {
 #ifdef CYGHWR_FREESCALE_DSPI2_CS0
@@ -409,114 +322,264 @@ static const cyg_uint32 spi2_cs_pins[] =
 };
 
 #ifdef CYGINT_DEVS_SPI_DSPI2_USES_DMA
-static volatile
-cyg_uint32 dspi2_pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI2_PUSHQUE_SIZE+4] PUSHQUE_ALIGN;
+  DSPI_EDMA_CHAN_SET(2);
+# define DSPI2_EDMA_SET_P DSPI_EDMA_SET_P_YES(2)
+# define DSPI2_EDMA_TCD DSPI_EDMA_TCD_YES(2)
+#else
+# define DSPI2_EDMA_SET_P DSPI_EDMA_SET_P_NULL(2)
+# define DSPI2_EDMA_TCD DSPI_EDMA_TCD_NULL(2)
+#endif // CYGINT_DEVS_SPI_DSPI2_USES_DMA
+
+DSPI_BUS_PINS(2);
+DSPI_BUS_SETUP(2);
+DSPI_BUS(2);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI2
+
+// DSPI BUS 3 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI3
+
+#define  CYGBLD_DSPI3_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI3_TCD_SECTION)
 
-static const cyghwr_hal_freescale_dma_chan_set_t dspi2_dma_chan[] =
-{
-    {
-        .dma_src = FREESCALE_DMAMUX_SRC_SPI2_TX
-        | FREESCALE_DMAMUX_CHCFG_ENBL_M,
-        .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI2_TX_DMA_CHAN,
-        .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI2_TX_DMA_PRI,
-    },
-    {
-        .dma_src = FREESCALE_DMAMUX_SRC_SPI2_RX
-        | FREESCALE_DMAMUX_CHCFG_ENBL_M,
-        .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI2_RX_DMA_CHAN,
-        .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI2_RX_DMA_PRI,
-    }
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI3_PCSS
+#define CYGHWR_FREESCALE_DSPI3_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI3_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi3_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI3_CS0
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI3_CS1
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI3_CS2
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI3_CS3
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI3_CS4
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI3_CS5
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS5
+#endif
 };
 
-static cyghwr_hal_freescale_dma_set_t dspi2_dma_set = {
-    .chan_p = dspi2_dma_chan,
-    .chan_n = 2
-};
+#ifdef CYGINT_DEVS_SPI_DSPI3_USES_DMA
+  DSPI_EDMA_CHAN_SET(3);
+# define DSPI3_EDMA_SET_P DSPI_EDMA_SET_P_YES(3)
+# define DSPI3_EDMA_TCD DSPI_EDMA_TCD_YES(3)
+#else
+# define DSPI3_EDMA_SET_P DSPI_EDMA_SET_P_NULL(3)
+# define DSPI3_EDMA_TCD DSPI_EDMA_TCD_NULL(3)
+#endif // CYGINT_DEVS_SPI_DSPI3_USES_DMA
+
+DSPI_BUS_PINS(3);
+DSPI_BUS_SETUP(3);
+DSPI_BUS(3);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI3
+
+// DSPI BUS 4 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI4
+
+#define  CYGBLD_DSPI4_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI4_TCD_SECTION)
 
-static const cyghwr_hal_freescale_edma_tcd_t dspi2_dma_tcd_tx_ini =
-{
-        .saddr =  (cyg_uint32 *) dspi2_pushque,
-        .soff = 4,
-        .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_SMOD(0) |
-                FREESCALE_EDMA_ATTR_DMOD(0),
-        .daddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI2_P->pushr,
-        .doff = 0,
-        .nbytes.mlno = 4,
-        .slast = 0,
-        .citer.elinkno = 1,
-        {.dlast = 0},
-        .biter.elinkno = 1,
-        .csr = DSPI_DMA_BANDWIDTH
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI4_PCSS
+#define CYGHWR_FREESCALE_DSPI4_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI4_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi4_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI4_CS0
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI4_CS1
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI4_CS2
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI4_CS3
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI4_CS4
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI4_CS5
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS5
+#endif
 };
 
+#ifdef CYGINT_DEVS_SPI_DSPI4_USES_DMA
+  DSPI_EDMA_CHAN_SET(4);
+# define DSPI4_EDMA_SET_P DSPI_EDMA_SET_P_YES(4)
+# define DSPI4_EDMA_TCD DSPI_EDMA_TCD_YES(4)
+#else
+# define DSPI4_EDMA_SET_P DSPI_EDMA_SET_P_NULL(4)
+# define DSPI4_EDMA_TCD DSPI_EDMA_TCD_NULL(4)
+#endif // CYGINT_DEVS_SPI_DSPI4_USES_DMA
 
-static const cyghwr_hal_freescale_edma_tcd_t dspi2_dma_tcd_rx_ini =
-{
-        .saddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI2_P->popr,
-        .soff = 0,
-        .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |
-                FREESCALE_EDMA_ATTR_SMOD(0) |
-                FREESCALE_EDMA_ATTR_DMOD(0),
-        .daddr = NULL,
-        .doff = 4,
-        .nbytes.mlno = 4,
-        .slast = 0,
-        .citer.elinkno = 1,
-        {.dlast = 0},
-        .biter.elinkno = 1,
-        .csr = DSPI_DMA_BANDWIDTH
+DSPI_BUS_PINS(4);
+DSPI_BUS_SETUP(4);
+DSPI_BUS(4);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI4
+
+// DSPI BUS 5 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI5
+
+#define  CYGBLD_DSPI5_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI5_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI5_PCSS
+#define CYGHWR_FREESCALE_DSPI5_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI5_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi5_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI5_CS0
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI5_CS1
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI5_CS2
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI5_CS3
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI5_CS4
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI5_CS5
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS5
+#endif
 };
 
-#endif // CYGINT_DEVS_SPI_DSPI2_USES_DMA
+#ifdef CYGINT_DEVS_SPI_DSPI5_USES_DMA
+  DSPI_EDMA_CHAN_SET(5);
+# define DSPI5_EDMA_SET_P DSPI_EDMA_SET_P_YES(5)
+# define DSPI5_EDMA_TCD DSPI_EDMA_TCD_YES(5)
+#else
+# define DSPI5_EDMA_SET_P DSPI_EDMA_SET_P_NULL(5)
+# define DSPI5_EDMA_TCD DSPI_EDMA_TCD_NULL(5)
+#endif // CYGINT_DEVS_SPI_DSPI5_USES_DMA
 
-static const cyg_spi_freescale_dspi_bus_setup_t dspi2_setup = {
-    .dspi_p          = CYGADDR_IO_SPI_FREESCALE_DSPI2_P,
-#ifdef CYGINT_DEVS_SPI_DSPI2_USES_DMA
-    .dma_set_p       = &dspi2_dma_set,
+DSPI_BUS_PINS(5);
+DSPI_BUS_SETUP(5);
+DSPI_BUS(5);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI5
+
+// DSPI BUS 6 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI6
+
+#define  CYGBLD_DSPI6_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI6_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI6_PCSS
+#define CYGHWR_FREESCALE_DSPI6_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
 #else
-    .dma_set_p       = NULL,
+#define CYGHWR_FREESCALE_DSPI6_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi6_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI6_CS0
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI6_CS1
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS1,
 #endif
-    .intr_num        = CYGNUM_HAL_INTERRUPT_SPI2,
-    .intr_prio       = CYGNUM_DEVS_SPI_FREESCALE_DSPI2_ISR_PRI,
-    .spi_pin_list_p  = spi2_pins,
-    .cs_pin_list_p   = spi2_cs_pins,
-    .cs_pin_num      = sizeof(spi2_cs_pins)/sizeof(spi2_cs_pins[0]),
-    .mcr_opt         = CYGHWR_FREESCALE_DSPI2_MCR_PCSSE |
-                       FREESCALE_DSPI_MCR_PCSIS(CYGHWR_DEVS_SPI_FREESCALE_DSPI2_PCSIS)
+#ifdef CYGHWR_FREESCALE_DSPI6_CS2
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI6_CS3
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI6_CS4
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI6_CS5
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS5
+#endif
 };
 
-cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus2 = {
-    .spi_bus.spi_transaction_begin    = dspi_transaction_begin,
-    .spi_bus.spi_transaction_transfer = dspi_transaction_transfer,
-    .spi_bus.spi_transaction_tick     = dspi_transaction_tick,
-    .spi_bus.spi_transaction_end      = dspi_transaction_end,
-    .spi_bus.spi_get_config           = dspi_get_config,
-    .spi_bus.spi_set_config           = dspi_set_config,
-    .setup_p                          = &dspi2_setup,
-#ifdef CYGINT_DEVS_SPI_DSPI2_USES_DMA
-    .tx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P->
-                     tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI2_TX_DMA_CHAN],
-    .rx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P->
-    tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI2_RX_DMA_CHAN],
-    .tx_dma_tcd_ini_p = &dspi2_dma_tcd_tx_ini,
-    .rx_dma_tcd_ini_p = &dspi2_dma_tcd_rx_ini,
-    .pushque_p = dspi2_pushque,
-#else // CYGINT_DEVS_SPI_DSPI2_USES_DMA
-    .tx_dma_tcd_p = NULL,
-    .rx_dma_tcd_p = NULL,
-    .tx_dma_tcd_ini_p = NULL,
-    .rx_dma_tcd_ini_p = NULL,
-    .pushque_p = NULL,
-#endif // CYGINT_DEVS_SPI_DSPI2_USES_DMA
-    .pushque_n = CYGNUM_DEVS_SPI_FREESCALE_DSPI2_PUSHQUE_SIZE,
-    .txfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE,
-    .rxfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE
-};
+#ifdef CYGINT_DEVS_SPI_DSPI6_USES_DMA
+  DSPI_EDMA_CHAN_SET(6);
+# define DSPI6_EDMA_SET_P DSPI_EDMA_SET_P_YES(6)
+# define DSPI6_EDMA_TCD DSPI_EDMA_TCD_YES(6)
+#else
+# define DSPI6_EDMA_SET_P DSPI_EDMA_SET_P_NULL(6)
+# define DSPI6_EDMA_TCD DSPI_EDMA_TCD_NULL(6)
+#endif // CYGINT_DEVS_SPI_DSPI6_USES_DMA
+
+DSPI_BUS_PINS(6);
+DSPI_BUS_SETUP(6);
+DSPI_BUS(6);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI6
+
+// DSPI BUS 7 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI7
+
+#define  CYGBLD_DSPI7_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI7_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI7_PCSS
+#define CYGHWR_FREESCALE_DSPI7_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI7_MCR_PCSSE 0
 #endif
 
+// SPI chip select pins.
+static const cyg_uint32 spi7_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI7_CS0
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI7_CS1
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI7_CS2
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI7_CS3
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI7_CS4
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI7_CS5
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS5
+#endif
+};
+
+#ifdef CYGINT_DEVS_SPI_DSPI7_USES_DMA
+  DSPI_EDMA_CHAN_SET(7);
+# define DSPI7_EDMA_SET_P DSPI_EDMA_SET_P_YES(7)
+# define DSPI7_EDMA_TCD DSPI_EDMA_TCD_YES(7)
+#else
+# define DSPI7_EDMA_SET_P DSPI_EDMA_SET_P_NULL(7)
+# define DSPI7_EDMA_TCD DSPI_EDMA_TCD_NULL(7)
+#endif // CYGINT_DEVS_SPI_DSPI7_USES_DMA
+
+DSPI_BUS_PINS(7);
+DSPI_BUS_SETUP(7);
+DSPI_BUS(7);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI7
 
 //=============================================================================
 #endif // SPI_FREESCALE_DSPI_BUSES_INL
--- a/packages/devs/spi/freescale/dspi/current/tests/spi_loopback.c
+++ b/packages/devs/spi/freescale/dspi/current/tests/spi_loopback.c
@@ -239,7 +239,7 @@ void run_test_4 (cyg_bool polled)
 void run_tests (void)
 {
     bool polled = true;
-    diag_printf ("Running Kinetis SPI driver loopback tests.\n");
+    diag_printf ("Running Freescale Kinetis/MPC5xxx DSPI driver loopback tests.\n");
 
     diag_printf ("\nPolled\n");
     run_test_tick (polled, 1024);
--- a/packages/hal/misc/freescale/edma/current/ChangeLog
+++ b/packages/hal/misc/freescale/edma/current/ChangeLog
@@ -1,3 +1,10 @@
+2013-02-06  Stefan Singer <stefan.singer@freescale.com> 
+		+ Ilija Kocho <ilijak@siva.com.mk>
+
+	* enhanced endianness support for devices with big and little endian
+	* added support for MPC5xxx in addition to Kinetis
+	(see Bugzilla 1001752).
+	
 2012-05-04  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* cdl/hal_freescale_edma.cdl
--- a/packages/hal/misc/freescale/edma/current/include/freescale_edma.h
+++ b/packages/hal/misc/freescale/edma/current/include/freescale_edma.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2011 Free Software Foundation, Inc.                        
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -89,37 +89,21 @@ typedef volatile struct cyghwr_hal_frees
 //---------------------------------------------------------------------------
 // eDMA
 
-// Indices for cyghwr_hal_freescale_edma_t::dchpri[]
-enum {
-    FREESCALE_DMA_PRI_CH3,  FREESCALE_DMA_PRI_CH2,
-    FREESCALE_DMA_PRI_CH1,  FREESCALE_DMA_PRI_CH0,
-    FREESCALE_DMA_PRI_CH7,  FREESCALE_DMA_PRI_CH6,
-    FREESCALE_DMA_PRI_CH5,  FREESCALE_DMA_PRI_CH4,
-    FREESCALE_DMA_PRI_CH11, FREESCALE_DMA_PRI_CH10,
-    FREESCALE_DMA_PRI_CH9,  FREESCALE_DMA_PRI_CH8,
-    FREESCALE_DMA_PRI_CH15, FREESCALE_DMA_PRI_CH14,
-    FREESCALE_DMA_PRI_CH13, FREESCALE_DMA_PRI_CH12
-#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
-    ,
-    FREESCALE_DMA_PRI_CH19, FREESCALE_DMA_PRI_CH18,
-    FREESCALE_DMA_PRI_CH17, FREESCALE_DMA_PRI_CH16,
-    FREESCALE_DMA_PRI_CH23, FREESCALE_DMA_PRI_CH22,
-    FREESCALE_DMA_PRI_CH21, FREESCALE_DMA_PRI_CH20,
-    FREESCALE_DMA_PRI_CH27, FREESCALE_DMA_PRI_CH26,
-    FREESCALE_DMA_PRI_CH25, FREESCALE_DMA_PRI_CH24,
-    FREESCALE_DMA_PRI_CH31, FREESCALE_DMA_PRI_CH30,
-    FREESCALE_DMA_PRI_CH29, FREESCALE_DMA_PRI_CH28
-#endif
-};
-
 // Transfer control descriptor
 typedef volatile struct cyghwr_hal_freescale_edma_tcd_s
                            cyghwr_hal_freescale_edma_tcd_t;
 #define CYGBLD_FREESCALE_EDMA_TCD_ALIGN CYGBLD_ATTRIB_ALIGN(32)
 struct cyghwr_hal_freescale_edma_tcd_s {
     volatile void* saddr;             //  Source Address
+
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+    cyg_uint16 attr;         //  Transfer Attributes
+    cyg_uint16 soff;         //  Signed Source Address Offset
+#else // AKA Little endian
     cyg_uint16 soff;         //  Signed Source Address Offset
     cyg_uint16 attr;         //  Transfer Attributes
+#endif
+
     union {
         cyg_uint32 mlno;     //  Minor Byte Count (Minor Loop Dis)
         //  Signed Minor Loop Off:
@@ -128,44 +112,75 @@ struct cyghwr_hal_freescale_edma_tcd_s {
     } nbytes;
     cyg_uint32 slast;         //  Last Source Address Adjustment
     volatile void *daddr;              //  Destination Address
+
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+
+    union {                   //  Current Minor Loop Link:
+        cyg_uint16 elinkyes;  //  Major Loop Count (Ch Lnkng Ena)
+        cyg_uint16 elinkno;   //  Major Loop Count (Ch Lnkng Dis)
+    } citer;
+    cyg_uint16 doff;          //  Signed Destination Address Offset
+#else // AKA Little endian
     cyg_uint16 doff;          //  Signed Destination Address Offset
     union {                   //  Current Minor Loop Link:
         cyg_uint16 elinkyes;  //  Major Loop Count (Ch Lnkng Ena)
         cyg_uint16 elinkno;   //  Major Loop Count (Ch Lnkng Dis)
     } citer;
+#endif
+
     union {
         cyg_uint32 dlast;     //  Last Dst Addr Adj/Scat Gath Addr
         cyghwr_hal_freescale_edma_tcd_t *sga;  //  Last Dst Addr Adj/Scat Gath Addr
-    };
+    } dlast_sga;
+
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+    union {                   //  Beginning Minor Loop Link:
+        cyg_uint16 elinkno;   //  Major Loop Cnt (Ch Lnkng Dis)
+        cyg_uint16 elinkyes;  //  Major Loop Cnt (Ch Lnkng Ena)
+    } biter;
+    cyg_uint16 csr;           //  Control and Status
+#else // AKA Little endian
     cyg_uint16 csr;           //  Control and Status
     union {                   //  Beginning Minor Loop Link:
         cyg_uint16 elinkno;   //  Major Loop Cnt (Ch Lnkng Dis)
         cyg_uint16 elinkyes;  //  Major Loop Cnt (Ch Lnkng Ena)
     } biter;
+#endif
 };
 
 // DMA - Peripheral register structure
 typedef volatile struct cyghwr_hal_freescale_edma_s {
-    cyg_uint32 cr;                   // Control Register
-    cyg_uint32 es;                   // Error Status Register
-    cyg_uint32 reserved_0;
-    cyg_uint32 erq;                  // Enable Request Register
-    cyg_uint32 reserved_1;
-    cyg_uint32 eei;                  // Enable Error Interrupt Register
-    cyg_uint8  ceei;                 // Clear Enable Error Interrupt Register
-    cyg_uint8  seei;                 // Set Enable Error Interrupt Register
-    cyg_uint8  cerq;                 // Clear Enable Request Register
-    cyg_uint8  serq;                 // Set Enable Request Register
-    cyg_uint8  cdne;                 // Clear DONE Status Bit Register
-    cyg_uint8  ssrt;                 // Set START Bit Register
-    cyg_uint8  cerr;                 // Clear Error Register
-    cyg_uint8  cint;                 // Clear Interrupt Request Register
-    cyg_uint32 reserved_2;
-    cyg_uint32 irq;                  // Interrupt Request Register
-    cyg_uint32 reserved_3;
-    cyg_uint32 err;                  // Error Register
-    cyg_uint32 reserved_4;
-    cyg_uint32 hrs;                  // Hardware Request Status Register
+    cyg_uint32 cr;                   // Control Register			// 0x0000
+    cyg_uint32 es;                   // Error Status Register			// 0x0004
+    cyg_uint32 reserved_0;							// 0x0008
+    cyg_uint32 erq;                  // Enable Request Register			// 0x000C
+    cyg_uint32 reserved_1;							// 0x0010
+    cyg_uint32 eei;                  // Enable Error Interrupt Register		// 0x0014
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+    cyg_uint8  serq;                 // Set Enable Request Register		// 0x0018
+    cyg_uint8  cerq;                 // Clear Enable Request Register		// 0x0019
+    cyg_uint8  seei;                 // Set Enable Error Interrupt Register	// 0x001A  
+    cyg_uint8  ceei;                 // Clear Enable Error Interrupt Register	// 0x001B
+    cyg_uint8  cint;                 // Clear Interrupt Request Register	// 0x001C
+    cyg_uint8  cerr;                 // Clear Error Register			// 0x001D
+    cyg_uint8  ssrt;                 // Set START Bit Register			// 0x001E
+    cyg_uint8  cdne;                 // Clear DONE Status Bit Register		// 0x001F
+#else // AKA Little endian
+    cyg_uint8  ceei;                 // Clear Enable Error Interrupt Register	
+    cyg_uint8  seei;                 // Set Enable Error Interrupt Register	
+    cyg_uint8  cerq;                 // Clear Enable Request Register		
+    cyg_uint8  serq;                 // Set Enable Request Register		
+    cyg_uint8  cdne;                 // Clear DONE Status Bit Register		
+    cyg_uint8  ssrt;                 // Set START Bit Register			
+    cyg_uint8  cerr;                 // Clear Error Register			
+    cyg_uint8  cint;                 // Clear Interrupt Request Register	
+#endif    
+    cyg_uint32 reserved_2;							// 0x0020
+    cyg_uint32 irq;                  // Interrupt Request Register		// 0x0024
+    cyg_uint32 reserved_3;							// 0x0028
+    cyg_uint32 err;                  // Error Register				// 0x002C
+    cyg_uint32 reserved_4;							// 0x0030
+    cyg_uint32 hrs;                  // Hardware Request Status Register	// 0x0034
     cyg_uint8  reserved_5[0x8100 - (0x8034 + 4)];
     cyg_uint8  dchpri[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; // Priorities
     cyg_uint8  reserved_6[0x9000 - 0x8100 - CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM];
@@ -460,56 +475,56 @@ hal_freescale_edma_tcd_diag(cyghwr_hal_f
 hal_freescale_edma_transfer_diag (cyghwr_hal_freescale_edma_t *edma_p,
                                   cyg_uint8 chan_i, cyg_bool recurse);
 
-__externC inline void
+CYGBLD_FORCE_INLINE void
 hal_freescale_edma_erq_enable(cyghwr_hal_freescale_edma_t *edma_p,
                               cyg_uint8 chan_i)
 {
     edma_p->serq = chan_i;
 }
 
-__externC inline void
+CYGBLD_FORCE_INLINE void
 hal_freescale_edma_erq_disable(cyghwr_hal_freescale_edma_t *edma_p,
                                cyg_uint8 chan_i)
 {
     edma_p->cerq = chan_i;
 }
 
-__externC inline void
+CYGBLD_FORCE_INLINE void
 hal_freescale_edma_cleardone(cyghwr_hal_freescale_edma_t *edma_p,
                               cyg_uint8 chan_i)
 {
     edma_p->cdne = chan_i;
 }
 
-__externC inline void
+CYGBLD_FORCE_INLINE void
 hal_freescale_edma_irq_enable(cyghwr_hal_freescale_edma_t *edma_p,
                               cyg_uint8 chan_i)
 {
     edma_p->seei = chan_i;
 }
 
-__externC inline void
+CYGBLD_FORCE_INLINE void
 hal_freescale_edma_irq_disable(cyghwr_hal_freescale_edma_t *edma_p,
                                cyg_uint8 chan_i)
 {
     edma_p->ceei = chan_i;
 }
 
-__externC inline void
+CYGBLD_FORCE_INLINE void
 hal_freescale_edma_irq_clear(cyghwr_hal_freescale_edma_t *edma_p,
                                cyg_uint8 chan_i)
 {
     edma_p->cint = chan_i;
 }
 
-__externC inline void
+CYGBLD_FORCE_INLINE void
 hal_freescale_edma_transfer_clear(cyghwr_hal_freescale_edma_t *edma_p,
                                   cyg_uint8 chan_i)
 {
     edma_p->tcd[chan_i].csr &= ~FREESCALE_EDMA_CSR_DONE_M;
 }
 
-__externC inline void
+CYGBLD_FORCE_INLINE void
 hal_freescale_edma_transfer_start(cyghwr_hal_freescale_edma_t *edma_p,
                                   cyg_uint8 chan_i)
 {
--- a/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c
+++ b/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2011 Free Software Foundation, Inc.                        
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -64,7 +64,35 @@
 #include <cyg/hal/hal_if.h>             // HAL header
 #include <cyg/hal/freescale_edma.h>     // Freescale eDMA defs
 
-// Channel priority register index
+// Channel priority register indexing
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+
+#define EDMA_CHAN_PRIORITY_I(__chan_i) (__chan_i)
+
+#else  // AKA Big endian
+// Indices for cyghwr_hal_freescale_edma_t::dchpri[]
+enum {
+    FREESCALE_DMA_PRI_CH3,  FREESCALE_DMA_PRI_CH2,
+    FREESCALE_DMA_PRI_CH1,  FREESCALE_DMA_PRI_CH0,
+    FREESCALE_DMA_PRI_CH7,  FREESCALE_DMA_PRI_CH6,
+    FREESCALE_DMA_PRI_CH5,  FREESCALE_DMA_PRI_CH4,
+    FREESCALE_DMA_PRI_CH11, FREESCALE_DMA_PRI_CH10,
+    FREESCALE_DMA_PRI_CH9,  FREESCALE_DMA_PRI_CH8,
+    FREESCALE_DMA_PRI_CH15, FREESCALE_DMA_PRI_CH14,
+    FREESCALE_DMA_PRI_CH13, FREESCALE_DMA_PRI_CH12
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
+    ,
+    FREESCALE_DMA_PRI_CH19, FREESCALE_DMA_PRI_CH18,
+    FREESCALE_DMA_PRI_CH17, FREESCALE_DMA_PRI_CH16,
+    FREESCALE_DMA_PRI_CH23, FREESCALE_DMA_PRI_CH22,
+    FREESCALE_DMA_PRI_CH21, FREESCALE_DMA_PRI_CH20,
+    FREESCALE_DMA_PRI_CH27, FREESCALE_DMA_PRI_CH26,
+    FREESCALE_DMA_PRI_CH25, FREESCALE_DMA_PRI_CH24,
+    FREESCALE_DMA_PRI_CH31, FREESCALE_DMA_PRI_CH30,
+    FREESCALE_DMA_PRI_CH29, FREESCALE_DMA_PRI_CH28
+#endif
+};
+
 const cyg_uint8 const PRICHAN_I[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM] =
 {
     FREESCALE_DMA_PRI_CH0,  FREESCALE_DMA_PRI_CH1,
@@ -88,6 +116,10 @@ const cyg_uint8 const PRICHAN_I[CYGNUM_H
 #endif
 };
 
+#define EDMA_CHAN_PRIORITY_I(__chan_i) (PRICHAN_I[__chan_i])
+
+#endif
+
 // Find an eDMA channel with given priority
 static volatile cyg_uint8*
 hal_freescale_edma_find_chan_with_pri(cyghwr_hal_freescale_edma_t *edma_p,
@@ -145,14 +177,14 @@ hal_freescale_edma_init_1chan(
     }
 
     if((chan_p->dma_prio != FREESCALE_EDMA_DCHPRI_ASIS) &&
-       (edma_p->dchpri[PRICHAN_I[chan_p->dma_chan_i]] != chan_p->dma_prio))
+       (edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_p->dma_chan_i)] != chan_p->dma_prio))
     {
         group_i = chan_p->dma_chan_i >= CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE ? 1 : 0;
         if((prev_ch_reqprio_p =
             hal_freescale_edma_find_chan_with_pri(edma_p, chan_p->dma_prio, group_i)))
         {
-            oldprio = edma_p->dchpri[PRICHAN_I[chan_p->dma_chan_i]];
-            edma_p->dchpri[PRICHAN_I[chan_p->dma_chan_i]] = chan_p->dma_prio;
+            oldprio = edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_p->dma_chan_i)];
+            edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_p->dma_chan_i)] = chan_p->dma_prio;
             *prev_ch_reqprio_p = oldprio;
         }
     }
@@ -249,7 +281,7 @@ hal_freescale_edma_diag(const cyghwr_hal
             diag_printf("Chan %2d: CHCFG=0x%02x (%2d) DCHPRI=0x%02x dmamux[%c]=%p", chan_i,
                         dmamux_p->chcfg[chan_i % 16],
                         FREESCALE_DMAMUX_CHCFG_SOURCE(dmamux_p->chcfg[chan_i % 16]),
-                        edma_p->dchpri[PRICHAN_I[chan_i]],
+                        edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_i)],
                         CYGHWR_IO_FREESCALE_DMAMUX0_P == dmamux_p ? '0' : (
 #if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
                         CYGHWR_IO_FREESCALE_DMAMUX1_P == dmamux_p ? '1' :
@@ -298,7 +330,7 @@ void hal_freescale_edma_tcd_diag(cyghwr_
                     tcd_p->slast, tcd_p->slast);
         diag_printf("%s    %s=%d [%p]\n", prefix,
                     (tcd_p->csr & FREESCALE_EDMA_CSR_ESG_M) ? "sga" : "dlast",
-                    tcd_p->dlast, tcd_p->sga);
+                    tcd_p->dlast_sga.dlast, tcd_p->dlast_sga.sga);
         diag_printf("%s    biter = %d, citer = %d\n", prefix,
                     tcd_p->biter.elinkno, tcd_p->citer.elinkno);
         diag_printf("%s    CSR=0x%04x\n", prefix, tcd_p->csr);
@@ -311,7 +343,7 @@ void hal_freescale_edma_transfer_diag(cy
     cyghwr_hal_freescale_edma_tcd_t *tcd_p;
     const char *prefix = "";
 
-    for(tcd_p = &edma_p->tcd[chan_i]; tcd_p; tcd_p = tcd_p->sga){
+    for(tcd_p = &edma_p->tcd[chan_i]; tcd_p; tcd_p = tcd_p->dlast_sga.sga){
         hal_freescale_edma_tcd_diag(tcd_p, chan_i, prefix);
         if(!(recurse && (tcd_p->csr & FREESCALE_EDMA_CSR_ESG_M)))
             break;
--- a/packages/infra/current/ChangeLog
+++ b/packages/infra/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-02-20  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/cyg_type.h: Add CYGBLD_ATTRIB_NO_INLINE (suggested by Jifl)
+	[ Bugzilla 1001768 ]
+
 2013-02-09  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* include/cyg_type.h: Add CYGBLD_FORCE_INLINE macro to be used
--- a/packages/infra/current/include/cyg_type.h
+++ b/packages/infra/current/include/cyg_type.h
@@ -475,6 +475,9 @@ typedef cyg_haladdrword CYG_ADDRWORD;
 #  define CYGBLD_FORCE_INLINE __externC inline __attribute((gnu_inline)) __attribute((always_inline))
 # endif
 
+// Suppress function inlining
+#define CYGBLD_ATTRIB_NO_INLINE __attribute__((noinline))
+
 #else // non-GNU
 
 # define CYGBLD_ATTRIB_UNUSED  /* nothing */
@@ -508,6 +511,8 @@ typedef cyg_haladdrword CYG_ADDRWORD;
 
 #define CYGBLD_FORCE_INLINE
 
+#define CYGBLD_ATTRIB_NO_INLINE
+
 #endif
 
 // How to define weak aliases. Currently this is simply a mixture of the