Mercurial > ecos
changeset 3205:b3af38677ed2
Enhanced endianness support for devices with big and little endian, added support for MPC5xxx in addition to Kinetis, extended support for up to 8 DSPIs.
| author | vae |
|---|---|
| date | Fri, 22 Feb 2013 19:38:45 +0000 |
| parents | 382872a76fa5 |
| children | 1f3f5c905da8 |
| files | packages/devs/spi/freescale/dspi/current/ChangeLog packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl packages/devs/spi/freescale/dspi/current/tests/spi_loopback.c |
| diffstat | 4 files changed, 411 insertions(+), 339 deletions(-) [+] |
line wrap: on
line diff
--- a/packages/devs/spi/freescale/dspi/current/ChangeLog +++ b/packages/devs/spi/freescale/dspi/current/ChangeLog @@ -1,3 +1,11 @@ +2013-02-06 Stefan Singer <stefan.singer@freescale.com> + + Ilija Kocho <ilijak@siva.com.mk> + + * enhanced endianness support for devices with big and little endian + * added support for MPC5xxx in addition to Kinetis + * extended support for up to 8 DSPIs + (see Bugzilla 1001752). + 2012-12-28 Ilija Kocho <ilijak@siva.com.mk> * cdl/spi_freescale_dspi.cdl, src/spi_freescale_dspi.c:
--- a/packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl +++ b/packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl @@ -55,7 +55,7 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS parent CYGPKG_IO_SPI active_if CYGPKG_IO_SPI - requires CYGPKG_HAL_CORTEXM_KINETIS + requires CYGPKG_HAL_CORTEXM_KINETIS || CYGPKG_HAL_POWERPC_MPC5xxx hardware include_dir cyg/io @@ -115,7 +115,7 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS } - for { set ::spibus 0 } { $::spibus < 3 } { incr ::spibus } { + for { set ::spibus 0 } { $::spibus < 8 } { incr ::spibus } { cdl_interface CYGINT_DEVS_SPI_FREESCALE_DSPI[set ::spibus] { display "Number of devices using DSPI bus [set ::spibus]" @@ -126,6 +126,7 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS description "Enable DSPI bus [set :: spibus]." flavor bool default_value CYGINT_DEVS_SPI_FREESCALE_DSPI[set ::spibus] + active_if CYGINT_DEVS_SPI_FREESCALE_DSPI[set ::spibus] implements CYGINT_HAL_DMA requires CYGPKG_HAL_FREESCALE_EDMA @@ -295,7 +296,7 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS flavor data requires CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_ISR_PRI_SP calculated CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_ISR_PRI_SP - description "Interrupt priority set-point is provtded bu HAL" + description "Interrupt priority set-point is provided by HAL" } } }
--- a/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl +++ b/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl @@ -10,7 +10,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2011 Free Software Foundation, Inc. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -56,29 +56,151 @@ //----------------------------------------------------------------------------- // Instantiate the bus state data structures. +// Some auxiliary macros -// DSPI0 BUS ================================================================= +#if (CYG_BYTEORDER == CYG_MSBFIRST) // AKA Big endian +#define EDMA_TCD_SADDR(__bus) \ + .saddr = (void *)(((unsigned int)&CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P->popr) + 3) +#else // AKA Little endian +#define EDMA_TCD_SADDR(__bus) \ + .saddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P->popr +#endif + +#define DSPI_EDMA_CHAN_SET(__bus) \ +static volatile cyg_uint32 \ +dspi ## __bus ## _pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _PUSHQUE_SIZE+4] \ +PUSHQUE_ALIGN EDMA_RAM_BUF_SECTION; \ + \ +static const cyghwr_hal_freescale_dma_chan_set_t dspi ## __bus ## _dma_chan[2] = \ +{ \ + { \ + .dma_src = FREESCALE_DMAMUX_SRC_SPI ## __bus ## _TX \ + | FREESCALE_DMAMUX_CHCFG_ENBL_M, \ + .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _TX_DMA_CHAN, \ + .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _TX_DMA_PRI, \ + }, \ + { \ + .dma_src = FREESCALE_DMAMUX_SRC_SPI ## __bus ## _RX \ + | FREESCALE_DMAMUX_CHCFG_ENBL_M, \ + .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _RX_DMA_CHAN, \ + .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _RX_DMA_PRI, \ + } \ +}; \ + \ +static cyghwr_hal_freescale_dma_set_t dspi ## __bus ## _dma_set = { \ + .chan_p = dspi ## __bus ## _dma_chan, \ + .chan_n = 2 \ +}; \ + \ +static const cyghwr_hal_freescale_edma_tcd_t dspi ## __bus ## _dma_tcd_tx_ini = \ +{ \ + .saddr = (cyg_uint32 *) dspi ## __bus ## _pushque, \ + .soff = 4, \ + .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | \ + FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | \ + FREESCALE_EDMA_ATTR_SMOD(0) | \ + FREESCALE_EDMA_ATTR_DMOD(0), \ + .daddr = (cyg_uint32 *) \ + &CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P->pushr, \ + .doff = 0, \ + .nbytes.mlno = 4, \ + .slast = 0, \ + .citer.elinkno = 1, \ + .dlast_sga.dlast = 0, \ + .biter.elinkno = 1, \ + .csr = DSPI_DMA_BANDWIDTH \ +}; \ + \ +static const cyghwr_hal_freescale_edma_tcd_t dspi ## __bus ## _dma_tcd_rx_ini = \ +{ \ + EDMA_TCD_SADDR(__bus), \ + .soff = 0, \ + .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | \ + FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | \ + FREESCALE_EDMA_ATTR_SMOD(0) | \ + FREESCALE_EDMA_ATTR_DMOD(0), \ + .daddr = NULL, \ + .doff = 4, \ + .nbytes.mlno = 4, \ + .slast = 0, \ + .citer.elinkno = 1, \ + .dlast_sga.dlast = 0, \ + .biter.elinkno = 1, \ + .csr = DSPI_DMA_BANDWIDTH \ +} + +#define DSPI_EDMA_SET_P_YES(__bus) .dma_set_p = &dspi ## __bus ## _dma_set +#define DSPI_EDMA_SET_P_NULL(__bus) .dma_set_p = NULL + +#define DSPI_EDMA_TCD_YES(__bus) \ + .tx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P-> \ + tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _TX_DMA_CHAN], \ + .rx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P-> \ + tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _RX_DMA_CHAN], \ + .tx_dma_tcd_ini_p = &dspi ## __bus ## _dma_tcd_tx_ini, \ + .rx_dma_tcd_ini_p = &dspi ## __bus ## _dma_tcd_rx_ini, \ + .pushque_p = dspi ## __bus ## _pushque + +#define DSPI_EDMA_TCD_NULL(__bus) \ + .tx_dma_tcd_p = NULL, \ + .rx_dma_tcd_p = NULL, \ + .tx_dma_tcd_ini_p = NULL, \ + .rx_dma_tcd_ini_p = NULL, \ + .pushque_p = NULL + +// End DSPI_EDMA + +#define DSPI_BUS_SETUP(__bus) \ +static const cyg_spi_freescale_dspi_bus_setup_t dspi ## __bus ## _setup = { \ + .dspi_p = CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P, \ + .intr_num = CYGNUM_HAL_INTERRUPT_SPI ## __bus, \ + .intr_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _ISR_PRI, \ + .spi_pin_list_p = spi ## __bus ## _pins, \ + .cs_pin_list_p = spi ## __bus ## _cs_pins, \ + .cs_pin_num = sizeof(spi ## __bus ## _cs_pins)/ \ + sizeof(spi ## __bus ## _cs_pins[0]), \ + .mcr_opt = CYGHWR_FREESCALE_DSPI ## __bus ## _MCR_PCSSE | \ + FREESCALE_DSPI_MCR_PCSIS( \ + CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _PCSIS), \ + DSPI ## __bus ## _EDMA_SET_P \ +} + +#define DSPI_BUS(__bus) \ +cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus ## __bus = { \ + .spi_bus.spi_transaction_begin = dspi_transaction_begin, \ + .spi_bus.spi_transaction_transfer = dspi_transaction_transfer, \ + .spi_bus.spi_transaction_tick = dspi_transaction_tick, \ + .spi_bus.spi_transaction_end = dspi_transaction_end, \ + .spi_bus.spi_get_config = dspi_get_config, \ + .spi_bus.spi_set_config = dspi_set_config, \ + .setup_p = &dspi ## __bus ## _setup, \ + DSPI ## __bus ## _EDMA_TCD, \ + .pushque_n = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _PUSHQUE_SIZE, \ + .txfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE, \ + .rxfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE \ +} + +#define DSPI_BUS_PINS(__bus) \ +static const cyg_uint32 spi ## __bus ## _pins[] = { \ + CYGHWR_IO_FREESCALE_SPI ## __bus ## _PIN_SIN, \ + CYGHWR_IO_FREESCALE_SPI ## __bus ## _PIN_SOUT, \ + CYGHWR_IO_FREESCALE_SPI ## __bus ## _PIN_SCK \ +} + +// DSPI BUS Instances ======================================================= + +// DSPI BUS 0 ================================================================ #ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI0 #define CYGBLD_DSPI0_TCD_SECTION \ CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI0_TCD_SECTION) -extern cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus0; - -// Pinonomy ------------------------------------------------------------------- - #ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI0_PCSS #define CYGHWR_FREESCALE_DSPI0_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M #else #define CYGHWR_FREESCALE_DSPI0_MCR_PCSSE 0 #endif -static const cyg_uint32 spi0_pins[] = { - CYGHWR_IO_FREESCALE_SPI0_PIN_SIN, - CYGHWR_IO_FREESCALE_SPI0_PIN_SOUT, - CYGHWR_IO_FREESCALE_SPI0_PIN_SCK -}; - // SPI chip select pins. static const cyg_uint32 spi0_cs_pins[] = { #ifdef CYGHWR_FREESCALE_DSPI0_CS0 @@ -102,136 +224,32 @@ static const cyg_uint32 spi0_cs_pins[] = }; #ifdef CYGINT_DEVS_SPI_DSPI0_USES_DMA -static volatile -cyg_uint32 dspi0_pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI0_PUSHQUE_SIZE+4] PUSHQUE_ALIGN; - -static cyghwr_hal_freescale_dma_chan_set_t dspi0_dma_chan[] = -{ - { - .dma_src = FREESCALE_DMAMUX_SRC_SPI0_TX - | FREESCALE_DMAMUX_CHCFG_ENBL_M, - .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI0_TX_DMA_CHAN, - .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI0_TX_DMA_PRI, - }, - { - .dma_src = FREESCALE_DMAMUX_SRC_SPI0_RX - | FREESCALE_DMAMUX_CHCFG_ENBL_M, - .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI0_RX_DMA_CHAN, - .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI0_RX_DMA_PRI, - } -}; - -static cyghwr_hal_freescale_dma_set_t dspi0_dma_set = { - .chan_p = dspi0_dma_chan, - .chan_n = 2 -}; - -static const cyghwr_hal_freescale_edma_tcd_t dspi0_dma_tcd_tx_ini = -{ - .saddr = (cyg_uint32 *) dspi0_pushque, - .soff = 4, - .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_SMOD(0) | - FREESCALE_EDMA_ATTR_DMOD(0), - .daddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI0_P->pushr, - .doff = 0, - .nbytes.mlno = 4, - .slast = 0, - .citer.elinkno = 1, - {.dlast = 0}, - .biter.elinkno = 1, - .csr = DSPI_DMA_BANDWIDTH -}; - - -static const cyghwr_hal_freescale_edma_tcd_t dspi0_dma_tcd_rx_ini = -{ - .saddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI0_P->popr, - .soff = 0, - .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_SMOD(0) | - FREESCALE_EDMA_ATTR_DMOD(0), - .daddr = NULL, - .doff = 4, - .nbytes.mlno = 4, - .slast = 0, - .citer.elinkno = 1, - {.dlast = 0}, - .biter.elinkno = 1, - .csr = DSPI_DMA_BANDWIDTH -}; - + DSPI_EDMA_CHAN_SET(0); +# define DSPI0_EDMA_SET_P DSPI_EDMA_SET_P_YES(0) +# define DSPI0_EDMA_TCD DSPI_EDMA_TCD_YES(0) +#else +# define DSPI0_EDMA_SET_P DSPI_EDMA_SET_P_NULL(0) +# define DSPI0_EDMA_TCD DSPI_EDMA_TCD_NULL(0) #endif // CYGINT_DEVS_SPI_DSPI0_USES_DMA -static const cyg_spi_freescale_dspi_bus_setup_t dspi0_setup = { - .dspi_p = CYGADDR_IO_SPI_FREESCALE_DSPI0_P, -#ifdef CYGINT_DEVS_SPI_DSPI0_USES_DMA - .dma_set_p = &dspi0_dma_set, -#else - .dma_set_p = NULL, -#endif - .intr_num = CYGNUM_HAL_INTERRUPT_SPI0, - .intr_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI0_ISR_PRI, - .spi_pin_list_p = spi0_pins, - .cs_pin_list_p = spi0_cs_pins, - .cs_pin_num = sizeof(spi0_cs_pins)/sizeof(spi0_cs_pins[0]), - .mcr_opt = CYGHWR_FREESCALE_DSPI0_MCR_PCSSE | - FREESCALE_DSPI_MCR_PCSIS(CYGHWR_DEVS_SPI_FREESCALE_DSPI0_PCSIS) -}; +DSPI_BUS_PINS(0); +DSPI_BUS_SETUP(0); +DSPI_BUS(0); -cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus0 = { - .spi_bus.spi_transaction_begin = dspi_transaction_begin, - .spi_bus.spi_transaction_transfer = dspi_transaction_transfer, - .spi_bus.spi_transaction_tick = dspi_transaction_tick, - .spi_bus.spi_transaction_end = dspi_transaction_end, - .spi_bus.spi_get_config = dspi_get_config, - .spi_bus.spi_set_config = dspi_set_config, - .setup_p = &dspi0_setup, -#ifdef CYGINT_DEVS_SPI_DSPI0_USES_DMA - .tx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P-> - tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI0_TX_DMA_CHAN], - .rx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P-> - tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI0_RX_DMA_CHAN], - .tx_dma_tcd_ini_p = &dspi0_dma_tcd_tx_ini, - .rx_dma_tcd_ini_p = &dspi0_dma_tcd_rx_ini, - .pushque_p = dspi0_pushque, -#else // CYGINT_DEVS_SPI_DSPI0_USES_DMA - .tx_dma_tcd_p = NULL, - .rx_dma_tcd_p = NULL, - .tx_dma_tcd_ini_p = NULL, - .rx_dma_tcd_ini_p = NULL, - .pushque_p = NULL, -#endif // CYGINT_DEVS_SPI_DSPI0_USES_DMA - .pushque_n = CYGNUM_DEVS_SPI_FREESCALE_DSPI0_PUSHQUE_SIZE, - .txfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE, - .rxfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE -}; -#endif +#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI0 -// DSPI1 BUS ================================================================= +// DSPI BUS 1 ================================================================ #ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI1 #define CYGBLD_DSPI1_TCD_SECTION \ CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI1_TCD_SECTION) -extern cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1; - -// Pinonomy ------------------------------------------------------------------- - #ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI1_PCSS #define CYGHWR_FREESCALE_DSPI1_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M #else #define CYGHWR_FREESCALE_DSPI1_MCR_PCSSE 0 #endif -static const cyg_uint32 spi1_pins[] = { - CYGHWR_IO_FREESCALE_SPI1_PIN_SIN, - CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT, - CYGHWR_IO_FREESCALE_SPI1_PIN_SCK -}; - // SPI chip select pins. static const cyg_uint32 spi1_cs_pins[] = { #ifdef CYGHWR_FREESCALE_DSPI1_CS0 @@ -255,137 +273,32 @@ static const cyg_uint32 spi1_cs_pins[] = }; #ifdef CYGINT_DEVS_SPI_DSPI1_USES_DMA -static volatile -cyg_uint32 dspi1_pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI1_PUSHQUE_SIZE+4] - PUSHQUE_ALIGN EDMA_RAM_BUF_SECTION; - -static const cyghwr_hal_freescale_dma_chan_set_t dspi1_dma_chan[2] = -{ - { - .dma_src = FREESCALE_DMAMUX_SRC_SPI1_TX - | FREESCALE_DMAMUX_CHCFG_ENBL_M, - .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI1_TX_DMA_CHAN, - .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI1_TX_DMA_PRI, - }, - { - .dma_src = FREESCALE_DMAMUX_SRC_SPI1_RX - | FREESCALE_DMAMUX_CHCFG_ENBL_M, - .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI1_RX_DMA_CHAN, - .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI1_RX_DMA_PRI, - } -}; - -static cyghwr_hal_freescale_dma_set_t dspi1_dma_set = { - .chan_p = dspi1_dma_chan, - .chan_n = 2 -}; - -static const cyghwr_hal_freescale_edma_tcd_t dspi1_dma_tcd_tx_ini = -{ - .saddr = (cyg_uint32 *) dspi1_pushque, - .soff = 4, - .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_SMOD(0) | - FREESCALE_EDMA_ATTR_DMOD(0), - .daddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI1_P->pushr, - .doff = 0, - .nbytes.mlno = 4, - .slast = 0, - .citer.elinkno = 1, - {.dlast = 0}, - .biter.elinkno = 1, - .csr = DSPI_DMA_BANDWIDTH -}; - - -static const cyghwr_hal_freescale_edma_tcd_t dspi1_dma_tcd_rx_ini = -{ - .saddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI1_P->popr, - .soff = 0, - .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_SMOD(0) | - FREESCALE_EDMA_ATTR_DMOD(0), - .daddr = NULL, - .doff = 4, - .nbytes.mlno = 4, - .slast = 0, - .citer.elinkno = 1, - {.dlast = 0}, - .biter.elinkno = 1, - .csr = DSPI_DMA_BANDWIDTH -}; - + DSPI_EDMA_CHAN_SET(1); +# define DSPI1_EDMA_SET_P DSPI_EDMA_SET_P_YES(1) +# define DSPI1_EDMA_TCD DSPI_EDMA_TCD_YES(1) +#else +# define DSPI1_EDMA_SET_P DSPI_EDMA_SET_P_NULL(1) +# define DSPI1_EDMA_TCD DSPI_EDMA_TCD_NULL(1) #endif // CYGINT_DEVS_SPI_DSPI1_USES_DMA -static const cyg_spi_freescale_dspi_bus_setup_t dspi1_setup = { - .dspi_p = CYGADDR_IO_SPI_FREESCALE_DSPI1_P, -#ifdef CYGINT_DEVS_SPI_DSPI1_USES_DMA - .dma_set_p = &dspi1_dma_set, -#else - .dma_set_p = NULL, -#endif - .intr_num = CYGNUM_HAL_INTERRUPT_SPI1, - .intr_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI1_ISR_PRI, - .spi_pin_list_p = spi1_pins, - .cs_pin_list_p = spi1_cs_pins, - .cs_pin_num = sizeof(spi1_cs_pins)/sizeof(spi1_cs_pins[0]), - .mcr_opt = CYGHWR_FREESCALE_DSPI1_MCR_PCSSE | - FREESCALE_DSPI_MCR_PCSIS(CYGHWR_DEVS_SPI_FREESCALE_DSPI1_PCSIS) -}; +DSPI_BUS_PINS(1); +DSPI_BUS_SETUP(1); +DSPI_BUS(1); -cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1 = { - .spi_bus.spi_transaction_begin = dspi_transaction_begin, - .spi_bus.spi_transaction_transfer = dspi_transaction_transfer, - .spi_bus.spi_transaction_tick = dspi_transaction_tick, - .spi_bus.spi_transaction_end = dspi_transaction_end, - .spi_bus.spi_get_config = dspi_get_config, - .spi_bus.spi_set_config = dspi_set_config, - .setup_p = &dspi1_setup, -#ifdef CYGINT_DEVS_SPI_DSPI1_USES_DMA - .tx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P-> - tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI1_TX_DMA_CHAN], - .rx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P-> - tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI1_RX_DMA_CHAN], - .tx_dma_tcd_ini_p = &dspi1_dma_tcd_tx_ini, - .rx_dma_tcd_ini_p = &dspi1_dma_tcd_rx_ini, - .pushque_p = dspi1_pushque, -#else // CYGINT_DEVS_SPI_DSPI1_USES_DMA - .tx_dma_tcd_p = NULL, - .rx_dma_tcd_p = NULL, - .tx_dma_tcd_ini_p = NULL, - .rx_dma_tcd_ini_p = NULL, - .pushque_p = NULL, -#endif // CYGINT_DEVS_SPI_DSPI1_USES_DMA - .pushque_n = CYGNUM_DEVS_SPI_FREESCALE_DSPI1_PUSHQUE_SIZE, - .txfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE, - .rxfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE -}; -#endif +#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI1 -// DSPI2 BUS ================================================================= +// DSPI BUS 2 ================================================================ #ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI2 #define CYGBLD_DSPI2_TCD_SECTION \ CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI2_TCD_SECTION) -extern cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus2; - -// Pinonomy ------------------------------------------------------------------- - #ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI2_PCSS #define CYGHWR_FREESCALE_DSPI2_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M #else #define CYGHWR_FREESCALE_DSPI2_MCR_PCSSE 0 #endif -static const cyg_uint32 spi2_pins[] = { - CYGHWR_IO_FREESCALE_SPI2_PIN_SIN, - CYGHWR_IO_FREESCALE_SPI2_PIN_SOUT, - CYGHWR_IO_FREESCALE_SPI2_PIN_SCK -}; - // SPI chip select pins. static const cyg_uint32 spi2_cs_pins[] = { #ifdef CYGHWR_FREESCALE_DSPI2_CS0 @@ -409,114 +322,264 @@ static const cyg_uint32 spi2_cs_pins[] = }; #ifdef CYGINT_DEVS_SPI_DSPI2_USES_DMA -static volatile -cyg_uint32 dspi2_pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI2_PUSHQUE_SIZE+4] PUSHQUE_ALIGN; + DSPI_EDMA_CHAN_SET(2); +# define DSPI2_EDMA_SET_P DSPI_EDMA_SET_P_YES(2) +# define DSPI2_EDMA_TCD DSPI_EDMA_TCD_YES(2) +#else +# define DSPI2_EDMA_SET_P DSPI_EDMA_SET_P_NULL(2) +# define DSPI2_EDMA_TCD DSPI_EDMA_TCD_NULL(2) +#endif // CYGINT_DEVS_SPI_DSPI2_USES_DMA + +DSPI_BUS_PINS(2); +DSPI_BUS_SETUP(2); +DSPI_BUS(2); + +#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI2 + +// DSPI BUS 3 ================================================================ +#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI3 + +#define CYGBLD_DSPI3_TCD_SECTION \ + CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI3_TCD_SECTION) -static const cyghwr_hal_freescale_dma_chan_set_t dspi2_dma_chan[] = -{ - { - .dma_src = FREESCALE_DMAMUX_SRC_SPI2_TX - | FREESCALE_DMAMUX_CHCFG_ENBL_M, - .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI2_TX_DMA_CHAN, - .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI2_TX_DMA_PRI, - }, - { - .dma_src = FREESCALE_DMAMUX_SRC_SPI2_RX - | FREESCALE_DMAMUX_CHCFG_ENBL_M, - .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI2_RX_DMA_CHAN, - .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI2_RX_DMA_PRI, - } +#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI3_PCSS +#define CYGHWR_FREESCALE_DSPI3_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M +#else +#define CYGHWR_FREESCALE_DSPI3_MCR_PCSSE 0 +#endif + +// SPI chip select pins. +static const cyg_uint32 spi3_cs_pins[] = { +#ifdef CYGHWR_FREESCALE_DSPI3_CS0 + CYGHWR_IO_FREESCALE_SPI3_PIN_CS0, +#endif +#ifdef CYGHWR_FREESCALE_DSPI3_CS1 + CYGHWR_IO_FREESCALE_SPI3_PIN_CS1, +#endif +#ifdef CYGHWR_FREESCALE_DSPI3_CS2 + CYGHWR_IO_FREESCALE_SPI3_PIN_CS2, +#endif +#ifdef CYGHWR_FREESCALE_DSPI3_CS3 + CYGHWR_IO_FREESCALE_SPI3_PIN_CS3, +#endif +#ifdef CYGHWR_FREESCALE_DSPI3_CS4 + CYGHWR_IO_FREESCALE_SPI3_PIN_CS4, +#endif +#ifdef CYGHWR_FREESCALE_DSPI3_CS5 + CYGHWR_IO_FREESCALE_SPI3_PIN_CS5 +#endif }; -static cyghwr_hal_freescale_dma_set_t dspi2_dma_set = { - .chan_p = dspi2_dma_chan, - .chan_n = 2 -}; +#ifdef CYGINT_DEVS_SPI_DSPI3_USES_DMA + DSPI_EDMA_CHAN_SET(3); +# define DSPI3_EDMA_SET_P DSPI_EDMA_SET_P_YES(3) +# define DSPI3_EDMA_TCD DSPI_EDMA_TCD_YES(3) +#else +# define DSPI3_EDMA_SET_P DSPI_EDMA_SET_P_NULL(3) +# define DSPI3_EDMA_TCD DSPI_EDMA_TCD_NULL(3) +#endif // CYGINT_DEVS_SPI_DSPI3_USES_DMA + +DSPI_BUS_PINS(3); +DSPI_BUS_SETUP(3); +DSPI_BUS(3); + +#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI3 + +// DSPI BUS 4 ================================================================ +#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI4 + +#define CYGBLD_DSPI4_TCD_SECTION \ + CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI4_TCD_SECTION) -static const cyghwr_hal_freescale_edma_tcd_t dspi2_dma_tcd_tx_ini = -{ - .saddr = (cyg_uint32 *) dspi2_pushque, - .soff = 4, - .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_SMOD(0) | - FREESCALE_EDMA_ATTR_DMOD(0), - .daddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI2_P->pushr, - .doff = 0, - .nbytes.mlno = 4, - .slast = 0, - .citer.elinkno = 1, - {.dlast = 0}, - .biter.elinkno = 1, - .csr = DSPI_DMA_BANDWIDTH +#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI4_PCSS +#define CYGHWR_FREESCALE_DSPI4_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M +#else +#define CYGHWR_FREESCALE_DSPI4_MCR_PCSSE 0 +#endif + +// SPI chip select pins. +static const cyg_uint32 spi4_cs_pins[] = { +#ifdef CYGHWR_FREESCALE_DSPI4_CS0 + CYGHWR_IO_FREESCALE_SPI4_PIN_CS0, +#endif +#ifdef CYGHWR_FREESCALE_DSPI4_CS1 + CYGHWR_IO_FREESCALE_SPI4_PIN_CS1, +#endif +#ifdef CYGHWR_FREESCALE_DSPI4_CS2 + CYGHWR_IO_FREESCALE_SPI4_PIN_CS2, +#endif +#ifdef CYGHWR_FREESCALE_DSPI4_CS3 + CYGHWR_IO_FREESCALE_SPI4_PIN_CS3, +#endif +#ifdef CYGHWR_FREESCALE_DSPI4_CS4 + CYGHWR_IO_FREESCALE_SPI4_PIN_CS4, +#endif +#ifdef CYGHWR_FREESCALE_DSPI4_CS5 + CYGHWR_IO_FREESCALE_SPI4_PIN_CS5 +#endif }; +#ifdef CYGINT_DEVS_SPI_DSPI4_USES_DMA + DSPI_EDMA_CHAN_SET(4); +# define DSPI4_EDMA_SET_P DSPI_EDMA_SET_P_YES(4) +# define DSPI4_EDMA_TCD DSPI_EDMA_TCD_YES(4) +#else +# define DSPI4_EDMA_SET_P DSPI_EDMA_SET_P_NULL(4) +# define DSPI4_EDMA_TCD DSPI_EDMA_TCD_NULL(4) +#endif // CYGINT_DEVS_SPI_DSPI4_USES_DMA -static const cyghwr_hal_freescale_edma_tcd_t dspi2_dma_tcd_rx_ini = -{ - .saddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI2_P->popr, - .soff = 0, - .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) | - FREESCALE_EDMA_ATTR_SMOD(0) | - FREESCALE_EDMA_ATTR_DMOD(0), - .daddr = NULL, - .doff = 4, - .nbytes.mlno = 4, - .slast = 0, - .citer.elinkno = 1, - {.dlast = 0}, - .biter.elinkno = 1, - .csr = DSPI_DMA_BANDWIDTH +DSPI_BUS_PINS(4); +DSPI_BUS_SETUP(4); +DSPI_BUS(4); + +#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI4 + +// DSPI BUS 5 ================================================================ +#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI5 + +#define CYGBLD_DSPI5_TCD_SECTION \ + CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI5_TCD_SECTION) + +#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI5_PCSS +#define CYGHWR_FREESCALE_DSPI5_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M +#else +#define CYGHWR_FREESCALE_DSPI5_MCR_PCSSE 0 +#endif + +// SPI chip select pins. +static const cyg_uint32 spi5_cs_pins[] = { +#ifdef CYGHWR_FREESCALE_DSPI5_CS0 + CYGHWR_IO_FREESCALE_SPI5_PIN_CS0, +#endif +#ifdef CYGHWR_FREESCALE_DSPI5_CS1 + CYGHWR_IO_FREESCALE_SPI5_PIN_CS1, +#endif +#ifdef CYGHWR_FREESCALE_DSPI5_CS2 + CYGHWR_IO_FREESCALE_SPI5_PIN_CS2, +#endif +#ifdef CYGHWR_FREESCALE_DSPI5_CS3 + CYGHWR_IO_FREESCALE_SPI5_PIN_CS3, +#endif +#ifdef CYGHWR_FREESCALE_DSPI5_CS4 + CYGHWR_IO_FREESCALE_SPI5_PIN_CS4, +#endif +#ifdef CYGHWR_FREESCALE_DSPI5_CS5 + CYGHWR_IO_FREESCALE_SPI5_PIN_CS5 +#endif }; -#endif // CYGINT_DEVS_SPI_DSPI2_USES_DMA +#ifdef CYGINT_DEVS_SPI_DSPI5_USES_DMA + DSPI_EDMA_CHAN_SET(5); +# define DSPI5_EDMA_SET_P DSPI_EDMA_SET_P_YES(5) +# define DSPI5_EDMA_TCD DSPI_EDMA_TCD_YES(5) +#else +# define DSPI5_EDMA_SET_P DSPI_EDMA_SET_P_NULL(5) +# define DSPI5_EDMA_TCD DSPI_EDMA_TCD_NULL(5) +#endif // CYGINT_DEVS_SPI_DSPI5_USES_DMA -static const cyg_spi_freescale_dspi_bus_setup_t dspi2_setup = { - .dspi_p = CYGADDR_IO_SPI_FREESCALE_DSPI2_P, -#ifdef CYGINT_DEVS_SPI_DSPI2_USES_DMA - .dma_set_p = &dspi2_dma_set, +DSPI_BUS_PINS(5); +DSPI_BUS_SETUP(5); +DSPI_BUS(5); + +#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI5 + +// DSPI BUS 6 ================================================================ +#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI6 + +#define CYGBLD_DSPI6_TCD_SECTION \ + CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI6_TCD_SECTION) + +#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI6_PCSS +#define CYGHWR_FREESCALE_DSPI6_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M #else - .dma_set_p = NULL, +#define CYGHWR_FREESCALE_DSPI6_MCR_PCSSE 0 +#endif + +// SPI chip select pins. +static const cyg_uint32 spi6_cs_pins[] = { +#ifdef CYGHWR_FREESCALE_DSPI6_CS0 + CYGHWR_IO_FREESCALE_SPI6_PIN_CS0, +#endif +#ifdef CYGHWR_FREESCALE_DSPI6_CS1 + CYGHWR_IO_FREESCALE_SPI6_PIN_CS1, #endif - .intr_num = CYGNUM_HAL_INTERRUPT_SPI2, - .intr_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI2_ISR_PRI, - .spi_pin_list_p = spi2_pins, - .cs_pin_list_p = spi2_cs_pins, - .cs_pin_num = sizeof(spi2_cs_pins)/sizeof(spi2_cs_pins[0]), - .mcr_opt = CYGHWR_FREESCALE_DSPI2_MCR_PCSSE | - FREESCALE_DSPI_MCR_PCSIS(CYGHWR_DEVS_SPI_FREESCALE_DSPI2_PCSIS) +#ifdef CYGHWR_FREESCALE_DSPI6_CS2 + CYGHWR_IO_FREESCALE_SPI6_PIN_CS2, +#endif +#ifdef CYGHWR_FREESCALE_DSPI6_CS3 + CYGHWR_IO_FREESCALE_SPI6_PIN_CS3, +#endif +#ifdef CYGHWR_FREESCALE_DSPI6_CS4 + CYGHWR_IO_FREESCALE_SPI6_PIN_CS4, +#endif +#ifdef CYGHWR_FREESCALE_DSPI6_CS5 + CYGHWR_IO_FREESCALE_SPI6_PIN_CS5 +#endif }; -cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus2 = { - .spi_bus.spi_transaction_begin = dspi_transaction_begin, - .spi_bus.spi_transaction_transfer = dspi_transaction_transfer, - .spi_bus.spi_transaction_tick = dspi_transaction_tick, - .spi_bus.spi_transaction_end = dspi_transaction_end, - .spi_bus.spi_get_config = dspi_get_config, - .spi_bus.spi_set_config = dspi_set_config, - .setup_p = &dspi2_setup, -#ifdef CYGINT_DEVS_SPI_DSPI2_USES_DMA - .tx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P-> - tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI2_TX_DMA_CHAN], - .rx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P-> - tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI2_RX_DMA_CHAN], - .tx_dma_tcd_ini_p = &dspi2_dma_tcd_tx_ini, - .rx_dma_tcd_ini_p = &dspi2_dma_tcd_rx_ini, - .pushque_p = dspi2_pushque, -#else // CYGINT_DEVS_SPI_DSPI2_USES_DMA - .tx_dma_tcd_p = NULL, - .rx_dma_tcd_p = NULL, - .tx_dma_tcd_ini_p = NULL, - .rx_dma_tcd_ini_p = NULL, - .pushque_p = NULL, -#endif // CYGINT_DEVS_SPI_DSPI2_USES_DMA - .pushque_n = CYGNUM_DEVS_SPI_FREESCALE_DSPI2_PUSHQUE_SIZE, - .txfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE, - .rxfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE -}; +#ifdef CYGINT_DEVS_SPI_DSPI6_USES_DMA + DSPI_EDMA_CHAN_SET(6); +# define DSPI6_EDMA_SET_P DSPI_EDMA_SET_P_YES(6) +# define DSPI6_EDMA_TCD DSPI_EDMA_TCD_YES(6) +#else +# define DSPI6_EDMA_SET_P DSPI_EDMA_SET_P_NULL(6) +# define DSPI6_EDMA_TCD DSPI_EDMA_TCD_NULL(6) +#endif // CYGINT_DEVS_SPI_DSPI6_USES_DMA + +DSPI_BUS_PINS(6); +DSPI_BUS_SETUP(6); +DSPI_BUS(6); + +#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI6 + +// DSPI BUS 7 ================================================================ +#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI7 + +#define CYGBLD_DSPI7_TCD_SECTION \ + CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI7_TCD_SECTION) + +#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI7_PCSS +#define CYGHWR_FREESCALE_DSPI7_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M +#else +#define CYGHWR_FREESCALE_DSPI7_MCR_PCSSE 0 #endif +// SPI chip select pins. +static const cyg_uint32 spi7_cs_pins[] = { +#ifdef CYGHWR_FREESCALE_DSPI7_CS0 + CYGHWR_IO_FREESCALE_SPI7_PIN_CS0, +#endif +#ifdef CYGHWR_FREESCALE_DSPI7_CS1 + CYGHWR_IO_FREESCALE_SPI7_PIN_CS1, +#endif +#ifdef CYGHWR_FREESCALE_DSPI7_CS2 + CYGHWR_IO_FREESCALE_SPI7_PIN_CS2, +#endif +#ifdef CYGHWR_FREESCALE_DSPI7_CS3 + CYGHWR_IO_FREESCALE_SPI7_PIN_CS3, +#endif +#ifdef CYGHWR_FREESCALE_DSPI7_CS4 + CYGHWR_IO_FREESCALE_SPI7_PIN_CS4, +#endif +#ifdef CYGHWR_FREESCALE_DSPI7_CS5 + CYGHWR_IO_FREESCALE_SPI7_PIN_CS5 +#endif +}; + +#ifdef CYGINT_DEVS_SPI_DSPI7_USES_DMA + DSPI_EDMA_CHAN_SET(7); +# define DSPI7_EDMA_SET_P DSPI_EDMA_SET_P_YES(7) +# define DSPI7_EDMA_TCD DSPI_EDMA_TCD_YES(7) +#else +# define DSPI7_EDMA_SET_P DSPI_EDMA_SET_P_NULL(7) +# define DSPI7_EDMA_TCD DSPI_EDMA_TCD_NULL(7) +#endif // CYGINT_DEVS_SPI_DSPI7_USES_DMA + +DSPI_BUS_PINS(7); +DSPI_BUS_SETUP(7); +DSPI_BUS(7); + +#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI7 //============================================================================= #endif // SPI_FREESCALE_DSPI_BUSES_INL
--- a/packages/devs/spi/freescale/dspi/current/tests/spi_loopback.c +++ b/packages/devs/spi/freescale/dspi/current/tests/spi_loopback.c @@ -239,7 +239,7 @@ void run_test_4 (cyg_bool polled) void run_tests (void) { bool polled = true; - diag_printf ("Running Kinetis SPI driver loopback tests.\n"); + diag_printf ("Running Freescale Kinetis/MPC5xxx DSPI driver loopback tests.\n"); diag_printf ("\nPolled\n"); run_test_tick (polled, 1024);