changeset 287:e514771dd548

(IQ80321) Fix problem with BIOS timeout on some motherboards.
author msalter
date Mon, 12 Aug 2002 15:31:54 +0000
parents 845276b93eaa
children 9d1f104153ba
files packages/hal/arm/xscale/iq80321/current/ChangeLog packages/hal/arm/xscale/iq80321/current/include/hal_platform_setup.h packages/hal/arm/xscale/iq80321/current/src/iq80321_pci.c
diffstat 3 files changed, 61 insertions(+), 28 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/arm/xscale/iq80321/current/ChangeLog
+++ b/packages/hal/arm/xscale/iq80321/current/ChangeLog
@@ -1,3 +1,14 @@
+2002-08-12  Mark Salter  <msalter@redhat.com>
+
+	* include/hal_platform_setup.h: Do some ATU initialization
+	before scrubbing, so PC BIOS can continue booting during
+	time consuming scrub.
+
+	* src/iq80321_pci.c (cyg_hal_plf_pci_init): Always set ATUCMD
+	register. Moved some ATU initialization to hal_platform_setup.h.
+	(cyg_hal_plf_wait_for_bios): Moved some ATU initialization to
+	hal_platform_setup.h.
+
 2002-07-15  Mark Salter  <msalter@redhat.com>
 
 	* include/pkgconf/mlt_arm_xscale_iq80321_rom.mlt: Add mmu_tables section.
--- a/packages/hal/arm/xscale/iq80321/current/include/hal_platform_setup.h
+++ b/packages/hal/arm/xscale/iq80321/current/include/hal_platform_setup.h
@@ -756,6 +756,33 @@ 1:
 
   no_ecc1:
 
+#ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
+	// Minimally setup ATU and release "retry" bit.
+	ldr     r1, =ATU_IATVR2
+	mov     r0, #SDRAM_PHYS_BASE
+	str     r0, [r1]
+	ldr	r0, =0xffffffff
+	sub	r1, r4, #1
+	sub	r0, r0, r1
+	bic	r0, r0, #0x3f
+	ldr	r1, =ATU_IALR2
+	str     r0, [r1]
+	ldr     r0, =((0xFFFFFFFF - ((64 * 1024 * 1024) - 1)) & 0xFFFFFFC0)
+        ldr     r1, =ATU_IALR1
+	str     r0, [r1]
+	mov	r0, #0xc
+        ldr     r1, =ATU_IABAR1
+	str     r0, [r1]
+	mov	r0, #0
+        ldr     r1, =ATU_IAUBAR1
+	str     r0, [r1]
+        ldr     r1, =ATU_PCSR
+	ldr	r0, [r1]
+	and	r13, r0, #4     // save retry bit for later
+	bic	r0, r0, #4
+	str	r0, [r1]
+#endif
+	
         // scrub init
 	mov	r12, r4		// size of memory to scrub
 	mov	r8, r4		// save DRAM size
@@ -843,6 +870,12 @@ 1:
         ldr     r1, =hal_dram_size  /* [see hal_intr.h] */
 	str	r8, [r1]
 
+#ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
+	// Save boot time retry flag.
+        ldr     r1, =hal_pcsr_cfg_retry
+	str	r13, [r1]
+#endif
+
 	// Move mmu tables into RAM so page table walks by the cpu
 	// don't interfere with FLASH programming.
 	ldr	r0, =mmu_table
@@ -909,6 +942,8 @@ 1:
 
 #define PLATFORM_VECTORS         _platform_vectors
         .macro  _platform_vectors
+        .globl  hal_pcsr_cfg_retry
+hal_pcsr_cfg_retry:   .long   0  // Boot-time value of PCSR Retry bit.
         .endm                                        
 
 /*---------------------------------------------------------------------------*/
--- a/packages/hal/arm/xscale/iq80321/current/src/iq80321_pci.c
+++ b/packages/hal/arm/xscale/iq80321/current/src/iq80321_pci.c
@@ -91,7 +91,11 @@ cyg_uint32 hal_pci_inbound_window_mask;
 //
 
 
+#ifdef CYG_HAL_STARTUP_ROM
 #ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
+// state of retry bit in PCSR prior to bit being cleared at sdram scrub time.
+extern int hal_pcsr_cfg_retry;
+
 // Wait for BIOS to configure Verde PCI.
 // Returns true if BIOS done, false if timeout
 bool
@@ -99,13 +103,6 @@ cyg_hal_plf_wait_for_bios(void)
 {
     int delay = 200;  // 20 seconds, tops
 
-    // 64-bit prefetchable
-    *ATU_IABAR1 = CYG_PRI_CFG_BAR_MEM_TYPE_64 | CYG_PRI_CFG_BAR_MEM_PREFETCH;
-    *ATU_IAUBAR1 = 0;
-
-    // clear RETRY
-    *ATU_PCSR &= ~PCSR_CFG_RETRY;
-
     while (delay-- > 0) {
 	if (*ATU_ATUCMD & CYG_PCI_CFG_COMMAND_MEMORY)
 	    return true;
@@ -114,6 +111,7 @@ cyg_hal_plf_wait_for_bios(void)
     return false;
 }
 #endif // CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
+#endif // CYG_HAL_STARTUP_ROM
 
 void
 cyg_hal_plf_pci_init(void)
@@ -125,25 +123,13 @@ cyg_hal_plf_pci_init(void)
     *GPIO_GPOE &= ~(1 << IQ80321_GBE_GPIO_PIN);
     *GPIO_GPOD |= (1 << IQ80321_GBE_GPIO_PIN);
 
-    // Inbound window 2 is used for SDRAM access.
-    // set inbound ATU translate value register to base of local DRAM
-    *ATU_IATVR2 = SDRAM_PHYS_BASE;
-
-    //  set inbound ATU limit register to include all of installed DRAM.
-    //  This value used as a mask.
-    //  Allow pci access to all memory
-    *ATU_IALR2 = dram_limit;
-
     hal_pci_inbound_window_mask = ~dram_limit;
 
-    //  set inbound ATU limit 1  to reserve 64MB for outbound window 0.
-    *ATU_IALR1 = (0xFFFFFFFF - ((64 * 1024 * 1024) - 1)) & 0xFFFFFFC0;
-
+#ifdef CYG_HAL_STARTUP_ROM
 #ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
-    if (!(*ATU_PCSR & PCSR_CFG_RETRY) || !cyg_hal_plf_wait_for_bios())
+    if (!hal_pcsr_cfg_retry || !cyg_hal_plf_wait_for_bios())
 #endif  // CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
     {
-#ifdef CYG_HAL_STARTUP_ROM
 	// 64-bit prefetchable
 	*ATU_IABAR2 = SDRAM_PHYS_BASE | \
                       CYG_PRI_CFG_BAR_MEM_TYPE_64 | \
@@ -156,14 +142,15 @@ cyg_hal_plf_pci_init(void)
 	              CYG_PRI_CFG_BAR_MEM_TYPE_64 | \
                       CYG_PRI_CFG_BAR_MEM_PREFETCH;
 
-	// allow ATU to act as a bus master, respond to PCI memory accesses,
-	// and assert S_SERR#
-	*ATU_ATUCMD = (CYG_PCI_CFG_COMMAND_SERR   | \
-		       CYG_PCI_CFG_COMMAND_PARITY | \
-		       CYG_PCI_CFG_COMMAND_MASTER | \
-		       CYG_PCI_CFG_COMMAND_MEMORY);
+    }
 #endif  // CYG_HAL_STARTUP_ROM
-    }
+
+    // allow ATU to act as a bus master, respond to PCI memory accesses,
+    // and assert S_SERR#
+    *ATU_ATUCMD = (CYG_PCI_CFG_COMMAND_SERR   | \
+		   CYG_PCI_CFG_COMMAND_PARITY | \
+		   CYG_PCI_CFG_COMMAND_MASTER | \
+		   CYG_PCI_CFG_COMMAND_MEMORY);
 
     hal_pci_alloc_base_memory = *ATU_IABAR1 & CYG_PRI_CFG_BAR_MEM_MASK;
     hal_pci_alloc_base_io = _PCI_IO_BASE;