Mercurial > ecos
changeset 3244:f6140ea7e34d
Rich memory layout for FlexBus RAM with support for caching. Remove redundant MLT files. [ Bugzilla 1001837 ]
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--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog @@ -1,3 +1,22 @@ +2013-04-28 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl: + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h: (New) + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi: (New) + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h: + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi: + * include/pkgconf/mlt_kinetis_flash_sram2s_ram.h: (Remove) + * include/pkgconf/mlt_kinetis_flash_sram2s_ram.ldi: (Remove) + * include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h: + * include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi: + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h: + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi: + * include/plf_io.h: + * misc/redboot_K60_FXM_SST25XX_ROM.ecm: (New) + * src/twr_k60n512_fxm_misc.c: + Rich memory layout for FlexBus RAM with support for caching. + Remove redundant MLT files. [ Bugzilla 1001837 ] + 2013-04-09 Ilija Kocho <ilijak@siva.com.mk> * cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl @@ -56,6 +56,8 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T implements CYGINT_HAL_CORTEXM_KINETIS_RTC implements CYGINT_IO_FREESCALE_I2C0 + implements CYGINT_IO_SERIAL_FREESCALE_UART4 + implements CYGINT_HAL_FREESCALE_UART4 description " The Freescale TWR K60N512 FXM Platform package provides the support @@ -102,30 +104,42 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T parent CYG_HAL_STARTUP_ENV default_value { "ROM" } legal_values { "ByVariant" "ROM" "RAM" } + requires { CYG_HAL_STARTUP_PLF != "ByVariant" implies + CYGPKG_HAL_CORTEXM_KINETIS_FBRAM == 1 } + description " - Startup tupes provided by the platform, in addition to variant startup - types. - If 'ByVariant' is selected, then startup type shall be selected from - the variant (CYG_HAL_STARTUP_VAR). Platform's 'ROM' startup builds - application similar to Variant's 'ROM' but using external RAM (FlexBus). - 'RAM' startup builds application intended for loading by RedBoot into - external RAM." + Startup tupes provided by the platform, in addition to variant + startup types. + If 'ByVariant' is selected, then startup type shall be selected from + the variant (CYG_HAL_STARTUP_VAR). Platform's 'ROM' startup builds + application similar to Variant's 'ROM' but using external RAM (FlexBus). + 'RAM' startup builds application intended for loading by RedBoot into + external RAM." } - cdl_option CYGHWR_MEMORY_LAYOUT_PLF { + cdl_component CYGHWR_MEMORY_LAYOUT_PLF { display "Memory layout by platform" flavor data no_define + active_if { CYG_HAL_STARTUP_PLF != "ByVariant" } + implements CYGINT_HAL_CORTEXM_KINETIS_FBRAM parent CYGHWR_MEMORY_LAYOUT calculated { - (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? 0 : + (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" : (CYG_HAL_STARTUP == "RAM") ? "kinetis_" . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_extram_ram" : (CYG_HAL_STARTUP == "ROM") ? "kinetis_" . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_extram_rom" : - "undefined_by_PLF" } + "Error!" } description "Combination of 'Startup type' and 'Kinetis member in use' produces the memory layout." + + cdl_option CYGHWR_MEMORY_RAM_RESERVED { + display "Reserved RAM space \[Bytes\]" + flavor data + legal_values 0 to 0x40000 + default_value 0x20000 + } } cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ { @@ -153,34 +167,6 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 } } - cdl_option CYGOPT_HAL_KINETIS_UART3_IMPLEMENT { - display "Use UART3" - flavor bool - default_value { CYGHWR_HAL_KINETIS_FB_CS0_SIZE <= 0x00040000 } - active_if { CYGHWR_HAL_KINETIS_FB_CS0_SIZE <= 0x00040000 } - implements CYGINT_IO_SERIAL_FREESCALE_UART3 - implements CYGINT_HAL_FREESCALE_UART3 - description " - FlexBus lines AD19 and AD18 are multiplxed with UART Rx and Tx - so we can't use UART3 if external RAM is larger than 1MiB. - If external RAM is less than 1MiB we use UART3 which - is compatible with single chip configuration." - } - - cdl_option CYGOPT_HAL_KINETIS_UART4_IMPLEMENT { - display "Use UART4" - flavor bool -# calculated !CYGOPT_HAL_KINETIS_UART3_IMPLEMENT - default_value { CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000 } -# active_if { CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000 } - implements CYGINT_IO_SERIAL_FREESCALE_UART4 - implements CYGINT_HAL_FREESCALE_UART4 - description " - FlexBus lines AD19 and AD18 are multiplxed with UART Rx and Tx - so we can't use UART3 if external RAM is larger than 1MiB. - Instead we use UART4" - } - cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { display "Number of communication channels on the board" flavor data @@ -302,20 +288,22 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T # CS0 Implementation implements CYGINT_HAL_KINETIS_FB_CS0 implements CYGINT_DEVS_RAM0_MICRON_CELLULAR + requires { is_active(CYGPKG_HAL_CORTEXM_KINETIS_FBRAM) implies + CYGHWR_HAL_KINETIS_FBR_SIZE == CYGHWR_HAL_KINETIS_FB_CS0_SIZE } cdl_option CYGHWR_HAL_KINETIS_FB_CS0_AR { display "Base address" flavor data parent CYGHWR_HAL_KINETIS_FB_CS0 - default_value 0x68000000 + default_value 0x60000000 } cdl_option CYGHWR_HAL_KINETIS_FB_CS0_SIZE { display "Size \[Bytes\]" flavor data - legal_values { 0x00040000 0x00400000 CYGHWR_RAM0_MICRON_CELLULAR_SIZE } - parent CYGHWR_HAL_KINETIS_FB_CS0 - default_value 0x00040000 + legal_values { 0x00040000 0x00400000 CYGHWR_RAM0_MICRON_CELLULAR_SIZE } + parent CYGHWR_HAL_KINETIS_FB_CS0 + default_value CYGHWR_RAM0_MICRON_CELLULAR_SIZE } cdl_option CYGHWR_HAL_KINETIS_FB_CS0_BASE {
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi @@ -0,0 +1,41 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; +
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h @@ -9,18 +9,30 @@ #define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) #define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) -#define CYGMEM_REGION_sram_u (0x20000000) -#define CYGMEM_REGION_sram_u_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) -#define CYGMEM_REGION_sram_u_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) #define CYGMEM_REGION_flash (0x00000000) #define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) #define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) -#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE) -#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE) +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_BASE) +//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) +//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + #ifndef __ASSEMBLER__ extern char CYG_LABEL_NAME (__heap1) []; #endif
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi @@ -6,9 +6,11 @@ MEMORY { sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE - sram_u : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE - ram : ORIGIN = CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE, LENGTH = CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE } SECTIONS @@ -34,10 +36,11 @@ SECTIONS SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) - USER_SECTION (data_sram, sram_u, 0x20000000 (NOLOAD), LMA_EQ_VMA) - SECTION_data (ram, CYGHWR_HAL_KINETIS_FB_CS0_AR, FOLLOWING (.got)) + SECTION_sram (sram, 0x20000000, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram)) SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) SECTIONS_END }
deleted file mode 100644 --- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_ram.h +++ /dev/null @@ -1,26 +0,0 @@ -// eCos memory layout - -#ifndef __ASSEMBLER__ -#include <cyg/infra/cyg_type.h> -#include <stddef.h> - -#endif -#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) -#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) -#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) - -#define CYGMEM_REGION_ram (0x20000000) -#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) -#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) - -#define CYGMEM_REGION_flash (0x00000000) -#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) -#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) - -#ifndef __ASSEMBLER__ -extern char CYG_LABEL_NAME (__heap1) []; -#endif -#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) -#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) - -
deleted file mode 100644 --- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_ram.ldi +++ /dev/null @@ -1,45 +0,0 @@ -// eCos memory layout - -#include <pkgconf/hal.h> -#include <cyg/infra/cyg_type.inc> - -MEMORY -{ - sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE - ram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE - flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE -} - -SECTIONS -{ - SECTIONS_BEGIN - SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) - USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) - - // Kinetis FLASH security configuration. Must be present at 0x00000400 - // Warning: Omitting FLASH security configuration or moving it to - // other location may lock Kinetis controller. - // See src/kinetis_mis.c for definition - - .flash_security 0x00000400 : { KEEP (*(.flash_security)) } > flash - - SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) - SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) - SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) - SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) - SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) - SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) - SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) - USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE (NOLOAD), LMA_EQ_VMA) - SECTION_data (ram, 0x20000400, FOLLOWING (.got)) - SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) - SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) - CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); - SECTIONS_END -} - -hal_vsr_table = (0x20000000); -hal_virtual_vector_table = hal_vsr_table + 128*4; -hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h @@ -9,10 +9,18 @@ #define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) #define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) -#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_CS0_AR) -#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_CS0_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + #ifndef __ASSEMBLER__ extern char CYG_LABEL_NAME (__heap1) []; #endif
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi @@ -3,34 +3,37 @@ #include <pkgconf/hal.h> #include <cyg/infra/cyg_type.inc> + MEMORY { - sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE - flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE - ram : ORIGIN = CYGHWR_HAL_KINETIS_FB_CS0_AR, LENGTH = CYGHWR_HAL_KINETIS_FB_CS0_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE } SECTIONS { SECTIONS_BEGIN - SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 , LMA_EQ_VMA) - SECTION_rom_vectors (ram, CYGHWR_HAL_KINETIS_FB_CS0_AR + 0x20000, LMA_EQ_VMA) - SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA) SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) SECTIONS_END } hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); hal_virtual_vector_table = hal_vsr_table + 128*4; -hal_startup_stack = CYGHWR_HAL_KINETIS_FB_CS0_AR + CYGHWR_HAL_KINETIS_FB_CS0_SIZE; - +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h @@ -13,10 +13,18 @@ #define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) #define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) -#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_CS0_BASE) -#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_CS0_SIZE - 0x100) +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + #ifndef __ASSEMBLER__ extern char CYG_LABEL_NAME (__heap1) []; #endif
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi @@ -5,9 +5,11 @@ MEMORY { - sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE - flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE - ram : ORIGIN = CYGHWR_HAL_KINETIS_FB_CS0_BASE, LENGTH = CYGHWR_HAL_KINETIS_FB_CS0_SIZE + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE } SECTIONS @@ -33,9 +35,10 @@ SECTIONS SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) - SECTION_data (ram, CYGHWR_HAL_KINETIS_FB_CS0_AR, FOLLOWING (.sram)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram)) SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) SECTIONS_END }
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h @@ -182,7 +182,7 @@ // the CPU to hang. These macros allow the GDB stubs to avoid making // accidental accesses to these areas. -__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ); +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ); #define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/misc/redboot_K60_FXM_SST25XX_ROM.ecm @@ -0,0 +1,81 @@ +# Redboot minimal configuration +# Target: TWR-K70F120M +# Startup: ROM with external RAM + + +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "RedBoot Kinetis TWR-K60N512-FXM" ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; +}; + +cdl_component CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0 { + user_value 1 +}; + +cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP { + user_value 100000000 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE { + user_value 16384 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 0 +}; + +#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH { +# user_value 1 +#}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + user_value -4 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK { + user_value -8 +}; + +#cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT { +# user_value 16 +#}; + +#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { +# user_value 0x20000 +#}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + user_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_CRCTABLE_LOCATION { + user_value ROM +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA { + user_value 1 +}; + +
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c @@ -101,11 +101,13 @@ CYGHWR_HAL_FB_CSCR(PS, __cs) + CYGHWR_HAL_FB_CSCR_IS(BEM, __cs) + \ CYGHWR_HAL_FB_CSCR_IS(BSTR, __cs) + CYGHWR_HAL_FB_CSCR_IS(BSTW, __cs)) +// Functions for final and initial FlexBus setting +// Description is with the code below. +static inline void hal_flexbus_init_initial(void); +static inline void hal_flexbus_init_final(void); #endif // CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS static inline void hal_misc_init(void); -static inline void hal_flexbus_init_initial(void); -static inline void hal_flexbus_init_final(void); // DATA and BSS locations __externC cyg_uint32 __ram_data_start; @@ -347,26 +349,34 @@ static struct { CYG_ADDRESS end; // End address (last byte) } hal_data_access[] = { - { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // Main RAM -#ifdef CYGMEM_REGION_sram - { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // System bus RAM partition +#if 1 //def CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#elif defined CYGMEM_REGION_sram_l + { CYGMEM_REGION_sram_l, CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1 }, // On-chip SRAM lower bank +#endif +#ifdef CYGMEM_REGION_ramcod + { CYGMEM_REGION_ramcod, CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition +#endif +#ifdef CYGMEM_REGION_ramnc + { CYGMEM_REGION_ramnc, CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1 }, // Non cachable RAM partition #endif #ifdef CYGMEM_REGION_flash - { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash #endif #ifdef CYGMEM_REGION_rom - { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash [currently none] #endif - { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals - { 0x40000000, 0x60000000-1 }, // Chip specific peripherals + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 } // Chip specific peripherals }; -__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ) +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ) { int i; for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) { - if( (addr >= hal_data_access[i].start) && - (addr+count) <= hal_data_access[i].end) + if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) && + ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end) return true; } return false; @@ -383,7 +393,7 @@ static struct { //-------------------------------------------------------------------------- // Memory layout // -// We report the on-chip SRAM and external SRAM. +// We report the on-chip SRAM and external RAM. void cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) @@ -399,6 +409,31 @@ cyg_plf_memory_segment(int seg, unsigned *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); break; #endif +#ifdef CYGMEM_REGION_sram_l +# define CASE_CODE 3 +# define CASE_RAMNC 4 + case 2: + *start = (unsigned char *)CYGMEM_REGION_sram_l; + *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE); + break; +#else +# define CASE_CODE 2 +# define CASE_RAMNC 3 +#endif + +#ifdef CYGMEM_REGION_ramcod + case CASE_CODE: + *start = (unsigned char *)CYGMEM_REGION_ramcod; + *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE); + break; +#endif + +#ifdef CYGMEM_REGION_ramnc + case CASE_RAMNC: + *start = (unsigned char *)CYGMEM_REGION_ramnc; + *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE); + break; +#endif default: *start = *end = NO_MEMORY; break;