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comparison packages/hal/sh/edk7708/current/include/platform.inc @ 507:0baabe6e08e0

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Minor clean ups to cope with a more finicky SH assembler
author bartv
date Sun, 19 Jan 2003 12:18:48 +0000
parents d2c90368aeef
children
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506:148c41b548dc 507:0baabe6e08e0
8 ## 8 ##
9 ##============================================================================= 9 ##=============================================================================
10 #####ECOSGPLCOPYRIGHTBEGIN#### 10 #####ECOSGPLCOPYRIGHTBEGIN####
11 ## ------------------------------------------- 11 ## -------------------------------------------
12 ## This file is part of eCos, the Embedded Configurable Operating System. 12 ## This file is part of eCos, the Embedded Configurable Operating System.
13 ## Copyright (C) 2003 Bart Veer
13 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. 14 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 ## 15 ##
15 ## eCos is free software; you can redistribute it and/or modify it under 16 ## eCos is free software; you can redistribute it and/or modify it under
16 ## the terms of the GNU General Public License as published by the Free 17 ## the terms of the GNU General Public License as published by the Free
17 ## Software Foundation; either version 2 or (at your option) any later version. 18 ## Software Foundation; either version 2 or (at your option) any later version.
72 1: mov.w @r3+,r0 // Address (or zero) 73 1: mov.w @r3+,r0 // Address (or zero)
73 cmp/eq #0,r0 74 cmp/eq #0,r0
74 bt 2f 75 bt 2f
75 mov.w @r3+,r1 // data 76 mov.w @r3+,r1 // data
76 bra 1b 77 bra 1b
77 mov.w r1,@r0 // delay slot 78 mov.w r1,@r0 // delay slot
78 79
79 .align 2 80 .align 2
80 BSC_settings_table: 81 BSC_settings_table:
81 # These are the settings set by the Hitachi ROM Monitor. 82 # These are the settings set by the Hitachi ROM Monitor.
82 83
83 .word CYGARC_REG_FRQCR 84 .word (CYGARC_REG_FRQCR & 0x0000FFFF)
84 .word CYGARC_REG_FRQCR_INIT 85 .word CYGARC_REG_FRQCR_INIT
85 86
86 # BCR2: Bus size of areas 1-6 to 32 bits 87 # BCR2: Bus size of areas 1-6 to 32 bits
87 .word CYGARC_REG_BCR2 88 .word (CYGARC_REG_BCR2 & 0x0000FFFF)
88 .word 0x3ffc 89 .word 0x3ffc
89 # BCR1: Areas 2 and 3 are SDRAM 90 # BCR1: Areas 2 and 3 are SDRAM
90 .word CYGARC_REG_BCR1 91 .word (CYGARC_REG_BCR1 & 0x0000FFFF)
91 .word 0x080c 92 .word 0x080c
92 # BCR2: Bus size of areas 1-6 to 32 bits [note: second write!] 93 # BCR2: Bus size of areas 1-6 to 32 bits [note: second write!]
93 .word CYGARC_REG_BCR2 94 .word (CYGARC_REG_BCR2 & 0x0000FFFF)
94 .word 0x3ffc 95 .word 0x3ffc
95 # WCR1: 3 wait-state cycles inserted for all areas 96 # WCR1: 3 wait-state cycles inserted for all areas
96 .word CYGARC_REG_WCR1 97 .word (CYGARC_REG_WCR1 & 0x0000FFFF)
97 .word 0x3fff 98 .word 0x3fff
98 # WCR2: extra wait states and full pitch for burst 99 # WCR2: extra wait states and full pitch for burst
99 .word CYGARC_REG_WCR2 100 .word (CYGARC_REG_WCR2 & 0x0000FFFF)
100 .word 0xffd7 101 .word 0xffd7
101 # MCR: RAS/CAS & burst timing area 2/3 102 # MCR: RAS/CAS & burst timing area 2/3
102 .word CYGARC_REG_MCR 103 .word (CYGARC_REG_MCR & 0x0000FFFF)
103 .word 0x963c 104 .word 0x963c
104 # RTCNT: refresh counter (needs a5 in top byte to accept write) 105 # RTCNT: refresh counter (needs a5 in top byte to accept write)
105 .word CYGARC_REG_RTCNT 106 .word (CYGARC_REG_RTCNT & 0x0000FFFF)
106 .word (0xa500 | 0x0000) 107 .word (0xa500 | 0x0000)
107 # RTCOR: refresh time constant (needs a5 in top byte to accept write) 108 # RTCOR: refresh time constant (needs a5 in top byte to accept write)
108 .word CYGARC_REG_RTCOR 109 .word (CYGARC_REG_RTCOR & 0x0000FFFF)
109 .word (0xa500 | 0x003b) 110 .word (0xa500 | 0x003b)
110 # RFCR: refresh count register (needs a4 in top byte to accept write) 111 # RFCR: refresh count register (needs a4 in top byte to accept write)
111 .word CYGARC_REG_RFCR 112 .word (CYGARC_REG_RFCR & 0x0000FFFF)
112 .word (0xa400 | 0x0000) 113 .word (0xa400 | 0x0000)
113 # RTCSR: refresh timer control (needs a5 in top byte to accept write) 114 # RTCSR: refresh timer control (needs a5 in top byte to accept write)
114 .word CYGARC_REG_RTCSR 115 .word (CYGARC_REG_RTCSR & 0x0000FFFF)
115 .word (0xa500 | 0x0008) 116 .word (0xa500 | 0x0008)
116 117
117 # Set SDMR to 0x220 118 # Set SDMR to 0x220
118 .word 0xd880 119 .word 0xd880
119 .word 0 120 .word 0