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comparison packages/hal/arm/sa11x0/sa1100mm/current/src/sa1100mm_misc.c @ 145:2e9a636d9de9 ecos-sw-2000-12-21

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Merge from eCos master repository on 2000-12-21-14:18:40-GMT
author jlarmour
date Fri, 22 Dec 2000 02:37:28 +0000
parents 450e4e1f1e80
children 8f2f7615e727
comparison
equal deleted inserted replaced
144:da1052144c56 145:2e9a636d9de9
58 #include <cyg/hal/hal_sa11x0.h> // Hardware definitions 58 #include <cyg/hal/hal_sa11x0.h> // Hardware definitions
59 #include <cyg/hal/sa1100mm.h> // Platform specifics 59 #include <cyg/hal/sa1100mm.h> // Platform specifics
60 60
61 #include <cyg/infra/diag.h> // diag_printf 61 #include <cyg/infra/diag.h> // diag_printf
62 62
63 // ------------------------------------------------------------------------- 63 // All the MM table layout is here:
64 // MMU initialization: 64 #include <cyg/hal/hal_mm.h>
65 //
66 // These structures are laid down in memory to define the translation
67 // table.
68 //
69
70 /*
71 * SA-1100 Translation Table Base Bit Masks */
72 #define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
73
74 /*
75 * SA-1100 Domain Access Control Bit Masks
76 */
77 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
78 #define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
79 #define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
80
81 struct ARM_MMU_FIRST_LEVEL_FAULT {
82 int id : 2;
83 int sbz : 30;
84 };
85 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
86
87 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
88 int id : 2;
89 int imp : 2;
90 int domain : 4;
91 int sbz : 1;
92 int base_address : 23;
93 };
94 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
95
96 struct ARM_MMU_FIRST_LEVEL_SECTION {
97 int id : 2;
98 int b : 1;
99 int c : 1;
100 int imp : 1;
101 int domain : 4;
102 int sbz0 : 1;
103 int ap : 2;
104 int sbz1 : 8;
105 int base_address : 12;
106 };
107 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
108
109 struct ARM_MMU_FIRST_LEVEL_RESERVED {
110 int id : 2;
111 int sbz : 30;
112 };
113 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
114
115 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
116 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
117
118 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
119
120 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
121 cacheable, bufferable, perm) \
122 CYG_MACRO_START \
123 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
124 \
125 desc.word = 0; \
126 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
127 desc.section.domain = 0; \
128 desc.section.c = (cacheable); \
129 desc.section.b = (bufferable); \
130 desc.section.ap = (perm); \
131 desc.section.base_address = (actual_base); \
132 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
133 = desc.word; \
134 CYG_MACRO_END
135
136 #define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
137 { int i; int j = abase; int k = vbase; \
138 for (i = size; i > 0 ; i--,j++,k++) \
139 { \
140 ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
141 } \
142 }
143
144 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
145 unsigned long word;
146 struct ARM_MMU_FIRST_LEVEL_FAULT fault;
147 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
148 struct ARM_MMU_FIRST_LEVEL_SECTION section;
149 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
150 };
151
152 #define ARM_UNCACHEABLE 0
153 #define ARM_CACHEABLE 1
154 #define ARM_UNBUFFERABLE 0
155 #define ARM_BUFFERABLE 1
156
157 #define ARM_ACCESS_PERM_NONE_NONE 0
158 #define ARM_ACCESS_PERM_RO_NONE 0
159 #define ARM_ACCESS_PERM_RO_RO 0
160 #define ARM_ACCESS_PERM_RW_NONE 1
161 #define ARM_ACCESS_PERM_RW_RO 2
162 #define ARM_ACCESS_PERM_RW_RW 3
163 65
164 void 66 void
165 hal_mmu_init(void) 67 hal_mmu_init(void)
166 { 68 {
167 unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000; 69 unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000;
173 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); 75 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
174 76
175 /* 77 /*
176 * Set the Domain Access Control Register 78 * Set the Domain Access Control Register
177 */ 79 */
178 i = ARM_ACCESS_TYPE_MANAGER(0) | 80 i = ARM_ACCESS_DACR_DEFAULT;
179 ARM_ACCESS_TYPE_NO_ACCESS(1) |
180 ARM_ACCESS_TYPE_NO_ACCESS(2) |
181 ARM_ACCESS_TYPE_NO_ACCESS(3) |
182 ARM_ACCESS_TYPE_NO_ACCESS(4) |
183 ARM_ACCESS_TYPE_NO_ACCESS(5) |
184 ARM_ACCESS_TYPE_NO_ACCESS(6) |
185 ARM_ACCESS_TYPE_NO_ACCESS(7) |
186 ARM_ACCESS_TYPE_NO_ACCESS(8) |
187 ARM_ACCESS_TYPE_NO_ACCESS(9) |
188 ARM_ACCESS_TYPE_NO_ACCESS(10) |
189 ARM_ACCESS_TYPE_NO_ACCESS(11) |
190 ARM_ACCESS_TYPE_NO_ACCESS(12) |
191 ARM_ACCESS_TYPE_NO_ACCESS(13) |
192 ARM_ACCESS_TYPE_NO_ACCESS(14) |
193 ARM_ACCESS_TYPE_NO_ACCESS(15);
194 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); 81 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
195 82
196 /* 83 /*
197 * First clear all TT entries - ie Set them to Faulting 84 * First clear all TT entries - ie Set them to Faulting
198 */ 85 */
238 new_func = (code_fun*)func; 125 new_func = (code_fun*)func;
239 new_func(); 126 new_func();
240 stack_ptr = old_stack; 127 stack_ptr = old_stack;
241 return; 128 return;
242 } 129 }
130
131 // ------------------------------------------------------------------------
132 // EOF sa1100mm_misc.c