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comparison packages/hal/mn10300/arch/current/include/hal_intr.h @ 30:641b639be825 ecos-sw-1999-08-16

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Merge from eCos master repository on 1999-08-16-22:01:37-BST
author jlarmour
date Mon, 16 Aug 1999 22:10:49 +0000
parents ece80412419a
children 3836136e7743
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29:093762bd6ba9 30:641b639be825
44 // 44 //
45 //####DESCRIPTIONEND#### 45 //####DESCRIPTIONEND####
46 // 46 //
47 //========================================================================== 47 //==========================================================================
48 48
49 #include <pkgconf/hal.h>
50
49 #include <cyg/infra/cyg_type.h> 51 #include <cyg/infra/cyg_type.h>
50 52 #include <cyg/hal/hal_io.h>
51 #include <pkgconf/hal.h> 53
52 54 #include <cyg/hal/var_intr.h>
53 //--------------------------------------------------------------------------
54
55 // The MN10300 has a somewhat complex interrupt structure. Besides the
56 // reset and NMI vectors there are seven maskable interrupt vectors
57 // which must point to code in the 64k starting at 0x40000000. There
58 // are also 25 Interrupt control groups, each of which can have 4
59 // interrupt lines attached, for a theoretical total of 100 interrupts
60 // (!). Some of these are dedicated to specific devices, other to
61 // external pins, and others are not connected to anything, resulting
62 // in only 45 that can actually be delivered. Each control group may
63 // be assigned one of seven interrupt levels, and is delivered to the
64 // corresponding vector. Software can then use a register to determine
65 // the delivering group and detect from there which interrupt has been
66 // delivered.
67 //
68 // The approach we will adopt at present is for the code attached to
69 // each vector to save state and jump via a table to a VSR. The
70 // default VSR will fully decode the delivered interrupt into a table
71 // of isr/data/object entries. VSR replacement will operate on the
72 // first level indirection table rather than the hardware
73 // vectors. This is the fastest mechanism, however it needs 100*3*4 +
74 // 7*4 = 1228 bytes for the tables.
75 //
76
77 //--------------------------------------------------------------------------
78 // Interrupt vectors.
79
80 // The level-specific hardware vectors
81 // These correspond to VSRs and are the values to use for HAL_VSR_GET/SET
82 #define CYGNUM_HAL_VECTOR_0 0
83 #define CYGNUM_HAL_VECTOR_1 1
84 #define CYGNUM_HAL_VECTOR_2 2
85 #define CYGNUM_HAL_VECTOR_3 3
86 #define CYGNUM_HAL_VECTOR_4 4
87 #define CYGNUM_HAL_VECTOR_5 5
88 #define CYGNUM_HAL_VECTOR_6 6
89 #define CYGNUM_HAL_VECTOR_NMI 7
90 #define CYGNUM_HAL_VECTOR_TRAP 8
91
92 #define CYGNUM_HAL_VSR_MIN 0
93 #define CYGNUM_HAL_VSR_MAX 8
94 #define CYGNUM_HAL_VSR_COUNT 9
95
96 // Exception vectors. These are the values used when passed out to an
97 // external exception handler using cyg_hal_deliver_exception()
98
99 #define CYGNUM_HAL_EXCEPTION_NMI 0
100 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS \
101 CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR
102 #define CYGNUM_HAL_EXCEPTION_TRAP 3
103
104 #define CYGNUM_HAL_EXCEPTION_MIN 0
105 #define CYGNUM_HAL_EXCEPTION_MAX 3
106 #define CYGNUM_HAL_EXCEPTION_COUNT 4
107
108
109 #if defined(CYG_HAL_MN10300_MN103000)
110
111 // The decoded interrupts
112
113 #define CYGNUM_HAL_INTERRUPT_NMIRQ 0
114 #define CYGNUM_HAL_INTERRUPT_WATCHDOG 1
115 #define CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR 2
116 #define CYGNUM_HAL_INTERRUPT_RESERVED_3 3
117
118 #define CYGNUM_HAL_INTERRUPT_RESERVED_4 4
119 #define CYGNUM_HAL_INTERRUPT_RESERVED_5 5
120 #define CYGNUM_HAL_INTERRUPT_RESERVED_6 6
121 #define CYGNUM_HAL_INTERRUPT_RESERVED_7 7
122
123 #define CYGNUM_HAL_INTERRUPT_TIMER_0 8
124 #define CYGNUM_HAL_INTERRUPT_TIMER_1 9
125 #define CYGNUM_HAL_INTERRUPT_TIMER_2 10
126 #define CYGNUM_HAL_INTERRUPT_TIMER_3 11
127
128 #define CYGNUM_HAL_INTERRUPT_TIMER_4 12
129 #define CYGNUM_HAL_INTERRUPT_TIMER_5 13
130 #define CYGNUM_HAL_INTERRUPT_TIMER_6 14
131 #define CYGNUM_HAL_INTERRUPT_TIMER_7 15
132
133 #define CYGNUM_HAL_INTERRUPT_TIMER_8 16
134 #define CYGNUM_HAL_INTERRUPT_TIMER_8_COMPARE_A 17
135 #define CYGNUM_HAL_INTERRUPT_TIMER_8_COMPARE_B 18
136 #define CYGNUM_HAL_INTERRUPT_RESERVED_19 19
137
138 #define CYGNUM_HAL_INTERRUPT_TIMER_9 20
139 #define CYGNUM_HAL_INTERRUPT_TIMER_9_COMPARE_A 21
140 #define CYGNUM_HAL_INTERRUPT_TIMER_9_COMPARE_B 22
141 #define CYGNUM_HAL_INTERRUPT_RESERVED_23 23
142
143 #define CYGNUM_HAL_INTERRUPT_TIMER_10 24
144 #define CYGNUM_HAL_INTERRUPT_TIMER_10_COMPARE_A 25
145 #define CYGNUM_HAL_INTERRUPT_TIMER_10_COMPARE_B 26
146 #define CYGNUM_HAL_INTERRUPT_TIMER_10_COMPARE_C 27
147
148 #define CYGNUM_HAL_INTERRUPT_TIMER_11 28
149 #define CYGNUM_HAL_INTERRUPT_TIMER_11_COMPARE_A 29
150 #define CYGNUM_HAL_INTERRUPT_TIMER_11_COMPARE_B 30
151 #define CYGNUM_HAL_INTERRUPT_TIMER_11_COMPARE_C 31
152
153 #define CYGNUM_HAL_INTERRUPT_TIMER_12 32
154 #define CYGNUM_HAL_INTERRUPT_TIMER_12_COMPARE_A 33
155 #define CYGNUM_HAL_INTERRUPT_TIMER_12_COMPARE_B 34
156 #define CYGNUM_HAL_INTERRUPT_TIMER_12_COMPARE_C 35
157
158 #define CYGNUM_HAL_INTERRUPT_TIMER_11_COMPARE_D 36
159 #define CYGNUM_HAL_INTERRUPT_TIMER_12_COMPARE_D 37
160 #define CYGNUM_HAL_INTERRUPT_RESERVED_38 38
161 #define CYGNUM_HAL_INTERRUPT_RESERVED_39 39
162
163 #define CYGNUM_HAL_INTERRUPT_DMA0 40
164 #define CYGNUM_HAL_INTERRUPT_RESERVED_41 41
165 #define CYGNUM_HAL_INTERRUPT_RESERVED_42 42
166 #define CYGNUM_HAL_INTERRUPT_RESERVED_43 43
167
168 #define CYGNUM_HAL_INTERRUPT_DMA1 44
169 #define CYGNUM_HAL_INTERRUPT_RESERVED_45 45
170 #define CYGNUM_HAL_INTERRUPT_RESERVED_46 46
171 #define CYGNUM_HAL_INTERRUPT_RESERVED_47 47
172
173 #define CYGNUM_HAL_INTERRUPT_DMA2 48
174 #define CYGNUM_HAL_INTERRUPT_RESERVED_49 49
175 #define CYGNUM_HAL_INTERRUPT_RESERVED_50 50
176 #define CYGNUM_HAL_INTERRUPT_RESERVED_51 51
177
178 #define CYGNUM_HAL_INTERRUPT_DMA3 52
179 #define CYGNUM_HAL_INTERRUPT_RESERVED_53 53
180 #define CYGNUM_HAL_INTERRUPT_RESERVED_54 54
181 #define CYGNUM_HAL_INTERRUPT_RESERVED_55 55
182
183 #define CYGNUM_HAL_INTERRUPT_SERIAL_0_RX 56
184 #define CYGNUM_HAL_INTERRUPT_SERIAL_0_TX 57
185 #define CYGNUM_HAL_INTERRUPT_RESERVED_58 58
186 #define CYGNUM_HAL_INTERRUPT_RESERVED_59 59
187
188 #define CYGNUM_HAL_INTERRUPT_SERIAL_1_RX 60
189 #define CYGNUM_HAL_INTERRUPT_SERIAL_1_TX 61
190 #define CYGNUM_HAL_INTERRUPT_RESERVED_62 62
191 #define CYGNUM_HAL_INTERRUPT_RESERVED_63 63
192
193 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_0 64
194 #define CYGNUM_HAL_INTERRUPT_RESERVED_65 65
195 #define CYGNUM_HAL_INTERRUPT_RESERVED_66 66
196 #define CYGNUM_HAL_INTERRUPT_RESERVED_67 67
197
198 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_1 68
199 #define CYGNUM_HAL_INTERRUPT_RESERVED_69 69
200 #define CYGNUM_HAL_INTERRUPT_RESERVED_70 70
201 #define CYGNUM_HAL_INTERRUPT_RESERVED_71 71
202
203 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_2 72
204 #define CYGNUM_HAL_INTERRUPT_RESERVED_73 73
205 #define CYGNUM_HAL_INTERRUPT_RESERVED_74 74
206 #define CYGNUM_HAL_INTERRUPT_RESERVED_75 75
207
208 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_3 76
209 #define CYGNUM_HAL_INTERRUPT_RESERVED_77 77
210 #define CYGNUM_HAL_INTERRUPT_RESERVED_78 78
211 #define CYGNUM_HAL_INTERRUPT_RESERVED_79 79
212
213 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_4 80
214 #define CYGNUM_HAL_INTERRUPT_RESERVED_81 81
215 #define CYGNUM_HAL_INTERRUPT_RESERVED_82 82
216 #define CYGNUM_HAL_INTERRUPT_RESERVED_83 83
217
218 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_5 84
219 #define CYGNUM_HAL_INTERRUPT_RESERVED_85 85
220 #define CYGNUM_HAL_INTERRUPT_RESERVED_86 86
221 #define CYGNUM_HAL_INTERRUPT_RESERVED_87 87
222
223 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_6 88
224 #define CYGNUM_HAL_INTERRUPT_RESERVED_89 89
225 #define CYGNUM_HAL_INTERRUPT_RESERVED_90 90
226 #define CYGNUM_HAL_INTERRUPT_RESERVED_91 91
227
228 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_7 92
229 #define CYGNUM_HAL_INTERRUPT_RESERVED_93 93
230 #define CYGNUM_HAL_INTERRUPT_RESERVED_94 94
231 #define CYGNUM_HAL_INTERRUPT_RESERVED_95 95
232
233 #define CYGNUM_HAL_INTERRUPT_AD_CONVERSION 96
234 #define CYGNUM_HAL_INTERRUPT_RESERVED_97 97
235 #define CYGNUM_HAL_INTERRUPT_RESERVED_98 98
236 #define CYGNUM_HAL_INTERRUPT_RESERVED_99 99
237
238 #define CYGNUM_HAL_ISR_MIN 0
239 #define CYGNUM_HAL_ISR_MAX 99
240
241 #define CYGNUM_HAL_ISR_COUNT 100
242
243 #elif defined(CYG_HAL_MN10300_MN103002)
244
245 // The decoded interrupts
246
247 #define CYGNUM_HAL_INTERRUPT_NMIRQ 0
248 #define CYGNUM_HAL_INTERRUPT_WATCHDOG 1
249 #define CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR 2
250 #define CYGNUM_HAL_INTERRUPT_RESERVED_3 3
251
252 #define CYGNUM_HAL_INTERRUPT_RESERVED_4 4
253 #define CYGNUM_HAL_INTERRUPT_RESERVED_5 5
254 #define CYGNUM_HAL_INTERRUPT_RESERVED_6 6
255 #define CYGNUM_HAL_INTERRUPT_RESERVED_7 7
256
257 #define CYGNUM_HAL_INTERRUPT_TIMER_0 8
258 #define CYGNUM_HAL_INTERRUPT_RESERVED_9 9
259 #define CYGNUM_HAL_INTERRUPT_RESERVED_10 10
260 #define CYGNUM_HAL_INTERRUPT_RESERVED_11 11
261
262 #define CYGNUM_HAL_INTERRUPT_TIMER_1 12
263 #define CYGNUM_HAL_INTERRUPT_RESERVED_13 13
264 #define CYGNUM_HAL_INTERRUPT_RESERVED_14 14
265 #define CYGNUM_HAL_INTERRUPT_RESERVED_15 15
266
267 #define CYGNUM_HAL_INTERRUPT_TIMER_2 16
268 #define CYGNUM_HAL_INTERRUPT_RESERVED_17 17
269 #define CYGNUM_HAL_INTERRUPT_RESERVED_18 18
270 #define CYGNUM_HAL_INTERRUPT_RESERVED_19 19
271
272 #define CYGNUM_HAL_INTERRUPT_TIMER_3 20
273 #define CYGNUM_HAL_INTERRUPT_RESERVED_21 21
274 #define CYGNUM_HAL_INTERRUPT_RESERVED_22 22
275 #define CYGNUM_HAL_INTERRUPT_RESERVED_23 23
276
277 #define CYGNUM_HAL_INTERRUPT_TIMER_4 24
278 #define CYGNUM_HAL_INTERRUPT_RESERVED_25 25
279 #define CYGNUM_HAL_INTERRUPT_RESERVED_26 26
280 #define CYGNUM_HAL_INTERRUPT_RESERVED_27 27
281
282 #define CYGNUM_HAL_INTERRUPT_TIMER_5 28
283 #define CYGNUM_HAL_INTERRUPT_RESERVED_29 29
284 #define CYGNUM_HAL_INTERRUPT_RESERVED_30 30
285 #define CYGNUM_HAL_INTERRUPT_RESERVED_31 31
286
287 #define CYGNUM_HAL_INTERRUPT_TIMER_6 32
288 #define CYGNUM_HAL_INTERRUPT_RESERVED_33 33
289 #define CYGNUM_HAL_INTERRUPT_RESERVED_34 34
290 #define CYGNUM_HAL_INTERRUPT_RESERVED_35 35
291
292 #define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_A 36
293 #define CYGNUM_HAL_INTERRUPT_RESERVED_37 37
294 #define CYGNUM_HAL_INTERRUPT_RESERVED_38 38
295 #define CYGNUM_HAL_INTERRUPT_RESERVED_39 39
296
297 #define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_B 40
298 #define CYGNUM_HAL_INTERRUPT_RESERVED_41 41
299 #define CYGNUM_HAL_INTERRUPT_RESERVED_42 42
300 #define CYGNUM_HAL_INTERRUPT_RESERVED_43 43
301
302 #define CYGNUM_HAL_INTERRUPT_RESERVED_44 44
303 #define CYGNUM_HAL_INTERRUPT_RESERVED_45 45
304 #define CYGNUM_HAL_INTERRUPT_RESERVED_46 46
305 #define CYGNUM_HAL_INTERRUPT_RESERVED_47 47
306
307 #define CYGNUM_HAL_INTERRUPT_DMA0 48
308 #define CYGNUM_HAL_INTERRUPT_RESERVED_49 49
309 #define CYGNUM_HAL_INTERRUPT_RESERVED_50 50
310 #define CYGNUM_HAL_INTERRUPT_RESERVED_51 51
311
312 #define CYGNUM_HAL_INTERRUPT_DMA1 52
313 #define CYGNUM_HAL_INTERRUPT_RESERVED_53 53
314 #define CYGNUM_HAL_INTERRUPT_RESERVED_54 54
315 #define CYGNUM_HAL_INTERRUPT_RESERVED_55 55
316
317 #define CYGNUM_HAL_INTERRUPT_DMA2 56
318 #define CYGNUM_HAL_INTERRUPT_RESERVED_57 57
319 #define CYGNUM_HAL_INTERRUPT_RESERVED_58 58
320 #define CYGNUM_HAL_INTERRUPT_RESERVED_59 59
321
322 #define CYGNUM_HAL_INTERRUPT_DMA3 60
323 #define CYGNUM_HAL_INTERRUPT_RESERVED_61 61
324 #define CYGNUM_HAL_INTERRUPT_RESERVED_62 62
325 #define CYGNUM_HAL_INTERRUPT_RESERVED_63 63
326
327 #define CYGNUM_HAL_INTERRUPT_SERIAL_0_RX 64
328 #define CYGNUM_HAL_INTERRUPT_RESERVED_65 65
329 #define CYGNUM_HAL_INTERRUPT_RESERVED_66 66
330 #define CYGNUM_HAL_INTERRUPT_RESERVED_67 67
331
332 #define CYGNUM_HAL_INTERRUPT_SERIAL_0_TX 68
333 #define CYGNUM_HAL_INTERRUPT_RESERVED_69 69
334 #define CYGNUM_HAL_INTERRUPT_RESERVED_70 70
335 #define CYGNUM_HAL_INTERRUPT_RESERVED_71 71
336
337 #define CYGNUM_HAL_INTERRUPT_SERIAL_1_RX 72
338 #define CYGNUM_HAL_INTERRUPT_RESERVED_73 73
339 #define CYGNUM_HAL_INTERRUPT_RESERVED_74 74
340 #define CYGNUM_HAL_INTERRUPT_RESERVED_75 75
341
342 #define CYGNUM_HAL_INTERRUPT_SERIAL_1_TX 76
343 #define CYGNUM_HAL_INTERRUPT_RESERVED_77 77
344 #define CYGNUM_HAL_INTERRUPT_RESERVED_78 78
345 #define CYGNUM_HAL_INTERRUPT_RESERVED_79 79
346
347 #define CYGNUM_HAL_INTERRUPT_SERIAL_2_RX 80
348 #define CYGNUM_HAL_INTERRUPT_RESERVED_81 81
349 #define CYGNUM_HAL_INTERRUPT_RESERVED_82 82
350 #define CYGNUM_HAL_INTERRUPT_RESERVED_83 83
351
352 #define CYGNUM_HAL_INTERRUPT_SERIAL_2_TX 84
353 #define CYGNUM_HAL_INTERRUPT_RESERVED_85 85
354 #define CYGNUM_HAL_INTERRUPT_RESERVED_86 86
355 #define CYGNUM_HAL_INTERRUPT_RESERVED_87 87
356
357 #define CYGNUM_HAL_INTERRUPT_RESERVED_88 88
358 #define CYGNUM_HAL_INTERRUPT_RESERVED_89 89
359 #define CYGNUM_HAL_INTERRUPT_RESERVED_90 90
360 #define CYGNUM_HAL_INTERRUPT_RESERVED_91 91
361
362 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_0 92
363 #define CYGNUM_HAL_INTERRUPT_RESERVED_93 93
364 #define CYGNUM_HAL_INTERRUPT_RESERVED_94 94
365 #define CYGNUM_HAL_INTERRUPT_RESERVED_95 95
366
367 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_1 96
368 #define CYGNUM_HAL_INTERRUPT_RESERVED_97 97
369 #define CYGNUM_HAL_INTERRUPT_RESERVED_98 98
370 #define CYGNUM_HAL_INTERRUPT_RESERVED_99 99
371
372 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_2 100
373 #define CYGNUM_HAL_INTERRUPT_RESERVED_101 101
374 #define CYGNUM_HAL_INTERRUPT_RESERVED_102 102
375 #define CYGNUM_HAL_INTERRUPT_RESERVED_103 103
376
377 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_3 104
378 #define CYGNUM_HAL_INTERRUPT_RESERVED_105 105
379 #define CYGNUM_HAL_INTERRUPT_RESERVED_106 106
380 #define CYGNUM_HAL_INTERRUPT_RESERVED_107 107
381
382 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_4 108
383 #define CYGNUM_HAL_INTERRUPT_RESERVED_109 109
384 #define CYGNUM_HAL_INTERRUPT_RESERVED_110 110
385 #define CYGNUM_HAL_INTERRUPT_RESERVED_111 111
386
387 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_5 112
388 #define CYGNUM_HAL_INTERRUPT_RESERVED_113 113
389 #define CYGNUM_HAL_INTERRUPT_RESERVED_114 114
390 #define CYGNUM_HAL_INTERRUPT_RESERVED_115 115
391
392 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_6 116
393 #define CYGNUM_HAL_INTERRUPT_RESERVED_117 117
394 #define CYGNUM_HAL_INTERRUPT_RESERVED_118 118
395 #define CYGNUM_HAL_INTERRUPT_RESERVED_119 119
396
397 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_7 120
398 #define CYGNUM_HAL_INTERRUPT_RESERVED_121 121
399 #define CYGNUM_HAL_INTERRUPT_RESERVED_122 122
400 #define CYGNUM_HAL_INTERRUPT_RESERVED_123 123
401
402 #define CYGNUM_HAL_ISR_MIN 0
403 #define CYGNUM_HAL_ISR_MAX 123
404
405 #define CYGNUM_HAL_ISR_COUNT (3+((CYGNUM_HAL_ISR_MAX+1)/4))
406
407 #endif
408
409 // The vector used by the Real time clock
410
411 #ifdef CYG_HAL_MN10300_SIM
412 # define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_5
413 //# define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_EXTERNAL_1
414 #else
415 # ifdef CYG_HAL_MN10300_MN103000
416 # define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_8
417 # endif
418 # ifdef CYG_HAL_MN10300_MN103002
419 # define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_5
420 # endif
421 #endif
422
423 //--------------------------------------------------------------------------
424 // Timer control registers.
425
426 // On simulator we use simulated external interrupt
427
428 #if defined(CYG_HAL_MN10300_MN103002)
429
430 // On the mn103002 we use timers 4 and 5
431
432 #define TIMER4_CR 0x340010a0
433 #define TIMER4_BR 0x34001090
434 #define TIMER4_MD 0x34001080
435
436 #define TIMER5_CR 0x340010a2
437 #define TIMER5_BR 0x34001092
438 #define TIMER5_MD 0x34001082
439
440 #define TIMER_CR TIMER5_CR
441 #define TIMER_BR TIMER5_BR
442 #define TIMER_MD TIMER5_MD
443
444 #define TIMER0_MD 0x34001000
445 #define TIMER0_BR 0x34001010
446 #define TIMER0_CR 0x34001020
447
448 #elif defined(CYG_HAL_MN10300_MN103000)
449
450 // on the mn103000 we use timers 4 and 5
451 #define TIMER4_CR 0x340010a0
452 #define TIMER4_BR 0x34001090
453 #define TIMER4_MD 0x34001080
454
455 #define TIMER5_CR 0x340010a2
456 #define TIMER5_BR 0x34001092
457 #define TIMER5_MD 0x34001082
458
459 #define TIMER_CR TIMER5_CR
460 #define TIMER_BR TIMER5_BR
461 #define TIMER_MD TIMER5_MD
462
463 #define TIMER0_MD 0x34001000
464 #define TIMER0_BR 0x34001010
465 #define TIMER0_CR 0x34001020
466
467 #endif
468 55
469 //-------------------------------------------------------------------------- 56 //--------------------------------------------------------------------------
470 // Static data used by HAL 57 // Static data used by HAL
471 58
472 // ISR tables 59 // ISR tables
476 63
477 // VSR table 64 // VSR table
478 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; 65 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
479 66
480 // MN10300 interrupt control registers, mapped by linker script. 67 // MN10300 interrupt control registers, mapped by linker script.
481 externC volatile cyg_uint16 mn10300_interrupt_control[0x300/2]; 68 externC volatile cyg_uint16 mn10300_interrupt_control[];
69
70 //--------------------------------------------------------------------------
71 // Default ISR
72 // The #define is used to test whether this routine exists, and to allow
73 // us to call it.
74
75 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
76
77 #define HAL_DEFAULT_ISR hal_default_isr
482 78
483 //-------------------------------------------------------------------------- 79 //--------------------------------------------------------------------------
484 // Interrupt state storage 80 // Interrupt state storage
485 81
486 typedef cyg_uint32 CYG_INTERRUPT_STATE; 82 typedef cyg_uint32 CYG_INTERRUPT_STATE;
487 83
488 //-------------------------------------------------------------------------- 84 //--------------------------------------------------------------------------
85
489 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK 86 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
87
88 // Routine to execute DSRs using separate interrupt stack
89 externC void hal_interrupt_stack_call_pending_DSRs(void);
90 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
91 hal_interrupt_stack_call_pending_DSRs()
490 92
491 // these are offered solely for stack usage testing 93 // these are offered solely for stack usage testing
492 // if they are not defined, then there is no interrupt stack. 94 // if they are not defined, then there is no interrupt stack.
493 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base 95 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
494 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack 96 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
495 // use them to declare these extern however you want: 97 // use them to declare these extern however you want:
496 // extern char HAL_INTERRUPT_STACK_BASE[]; 98 // extern char HAL_INTERRUPT_STACK_BASE[];
497 // extern char HAL_INTERRUPT_STACK_TOP[]; 99 // extern char HAL_INTERRUPT_STACK_TOP[];
498 // is recommended 100 // is recommended
101
499 #endif 102 #endif
500 103
501 //-------------------------------------------------------------------------- 104 //--------------------------------------------------------------------------
502 // Interrupt control macros 105 // Interrupt control macros
503 106
546 // level. On the MN103000 there are several interrupts per controller, 149 // level. On the MN103000 there are several interrupts per controller,
547 // so we have to decode to one of 100 vectors. On the MN103002 there is 150 // so we have to decode to one of 100 vectors. On the MN103002 there is
548 // only one interrupt per controller, so we can have just one ISR per 151 // only one interrupt per controller, so we can have just one ISR per
549 // controller, except for the NMI vectors which occupy the first 3 slots. 152 // controller, except for the NMI vectors which occupy the first 3 slots.
550 153
551 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN 154 #ifndef HAL_TRANSLATE_VECTOR
155
156 #if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
552 157
553 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ 158 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
554 { \ 159 { \
555 if( _vector_ <= CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR ) \ 160 if( _vector_ <= CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR ) \
556 (_index_) = (_vector_); \ 161 (_index_) = (_vector_); \
567 } \ 172 } \
568 } 173 }
569 174
570 #else 175 #else
571 176
572 #if defined(CYG_HAL_MN10300_MN103000)
573
574 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_) 177 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_)
575 178
576 #elif defined(CYG_HAL_MN10300_MN103002) 179 #endif
577 180
578 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ 181 #endif
579 _index_ = (((_vector_)<=CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR) ? \
580 (_vector_) : \
581 (((_vector_)>>2)+CYGNUM_HAL_INTERRUPT_RESERVED_3))
582
583 #endif
584
585 #endif
586
587 182
588 //-------------------------------------------------------------------------- 183 //--------------------------------------------------------------------------
589 // Interrupt and VSR attachment macros 184 // Interrupt and VSR attachment macros
590 185
591 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ 186 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
592 CYG_MACRO_START \ 187 CYG_MACRO_START \
593 cyg_uint32 _index_; \ 188 cyg_uint32 _index_; \
594 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ 189 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
595 \ 190 \
596 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)NULL ) \ 191 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
597 (_state_) = 0; \ 192 (_state_) = 0; \
598 else \ 193 else \
599 (_state_) = 1; \ 194 (_state_) = 1; \
600 CYG_MACRO_END 195 CYG_MACRO_END
601 196
602 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ 197 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
603 { \ 198 CYG_MACRO_START \
199 cyg_uint32 _index_; \
200 HAL_TRANSLATE_VECTOR(_vector_,_index_); \
201 \
202 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
203 { \
204 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
205 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
206 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
207 } \
208 CYG_MACRO_END
209
210 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
211 CYG_MACRO_START \
604 cyg_uint32 _index_; \ 212 cyg_uint32 _index_; \
605 HAL_TRANSLATE_VECTOR(_vector_,_index_); \ 213 HAL_TRANSLATE_VECTOR(_vector_,_index_); \
606 \ 214 \
607 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)NULL ) \
608 { \
609 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
610 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
611 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
612 } \
613 }
614
615 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
616 { \
617 cyg_uint32 _index_; \
618 HAL_TRANSLATE_VECTOR(_vector_,_index_); \
619 \
620 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ 215 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
621 { \ 216 { \
622 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)NULL; \ 217 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
623 hal_interrupt_data[_index_] = 0; \ 218 hal_interrupt_data[_index_] = 0; \
624 hal_interrupt_objects[_index_] = 0; \ 219 hal_interrupt_objects[_index_] = 0; \
625 } \ 220 } \
626 } 221 CYG_MACRO_END
627 222
628 #define HAL_VSR_GET( _vector_, _pvsr_ ) \ 223 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
629 *((CYG_ADDRESS *)_pvsr_) = hal_vsr_table[_vector_]; 224 *((CYG_ADDRESS *)_pvsr_) = hal_vsr_table[_vector_];
630 225
631 226
689 /* restore the interrupt control register */ \ 284 /* restore the interrupt control register */ \
690 mn10300_interrupt_control[_index_] = _icr_; \ 285 mn10300_interrupt_control[_index_] = _icr_; \
691 _icr_ = mn10300_interrupt_control[_index_]; \ 286 _icr_ = mn10300_interrupt_control[_index_]; \
692 } 287 }
693 288
694 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ 289 #if !defined(HAL_INTERRUPT_CONFIGURE)
695 { \ 290
696 cyg_uint32 _v_ = _vector_; \ 291 #error HAL_INTERRUPT_CONFIGURE not defined by variant
697 cyg_uint16 _val_ = 0; \ 292
698 cyg_uint16 _reg_; \ 293 #endif
699 \
700 /* adjust vector to bit offset in EXTMD */ \
701 _v_ -= CYGNUM_HAL_INTERRUPT_EXTERNAL_0; \
702 _v_ >>= 1; \
703 \
704 /* set bits according to requirements */ \
705 if( _up_ ) _val_ |= 1; \
706 if( !(_level_) ) _val_ |= 2; \
707 \
708 /* get EXTMD */ \
709 _reg_ = mn10300_interrupt_control[0x180>>1]; \
710 \
711 /* clear old value and set new */ \
712 _reg_ &= ~(3<<_v_); \
713 _reg_ |= _val_<<_v_; \
714 \
715 /* restore EXTMD */ \
716 mn10300_interrupt_control[0x180>>1] = _reg_; \
717 }
718 294
719 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ 295 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
720 { \ 296 { \
721 /* ICRs are 16 bit regs at 32 bit spacing */ \ 297 /* ICRs are 16 bit regs at 32 bit spacing */ \
722 cyg_ucount16 _index_ = (_vector_>>2)<<1; \ 298 cyg_ucount16 _index_ = (_vector_>>2)<<1; \
732 mn10300_interrupt_control[_index_] = _icr_; \ 308 mn10300_interrupt_control[_index_] = _icr_; \
733 _icr_ = mn10300_interrupt_control[_index_]; \ 309 _icr_ = mn10300_interrupt_control[_index_]; \
734 } 310 }
735 311
736 //-------------------------------------------------------------------------- 312 //--------------------------------------------------------------------------
737 // Clock control 313 // Clock control.
738 314 // This is almost all handled in the var_intr.h.
739
740 #if 0 // defined(CYG_HAL_MN10300_SIM)
741
742 #define OEA_DEV 0x31000000
743
744 #define HAL_SWAP(x) ((((x)&0xff)<<24)|(((x)&0xff00)<<8)| \
745 (((x)&0xff0000)>>8)|(((x)&0xff000000)>>24))
746
747 #define PAL_COUNTDOWN_TIMER 0x20 // one shot on IR0
748 #define PAL_COUNTDOWN_VALUE 0x24
749 #define PAL_PERIODIC_TIMER 0x28 // repeating on IR1
750 #define PAL_PERIODIC_VALUE 0x2c
751
752
753 // IRQ1 set to receive clock intrs
754 #define HAL_CLOCK_INITIALIZE( _period_ ) \
755 { \
756 volatile cyg_uint32 *timer = (cyg_uint32 *) \
757 (OEA_DEV + PAL_PERIODIC_TIMER); \
758 cyg_uint32 p = _period_; \
759 \
760 *timer = HAL_SWAP(p); \
761 }
762
763 #elif defined(CYG_HAL_MN10300_MN103000)
764
765 #define HAL_CLOCK_INITIALIZE( _period_ ) \
766 { \
767 volatile cyg_uint16 *timer_ctr = (cyg_uint16 *)TIMER_BR; \
768 volatile cyg_uint16 *timer_mode = (cyg_uint16 *)TIMER_MD; \
769 volatile cyg_uint8 *timer_a_mode = (cyg_uint8 *)0x34001084; \
770 \
771 *timer_a_mode = 0x04; \
772 \
773 *timer_ctr = 0xf000; \
774 \
775 *timer_mode = 0x0013; \
776 *timer_mode = 0x4013; \
777 *timer_mode = 0x0013; \
778 *timer_mode = 0x8013; \
779 }
780
781 #elif defined(CYG_HAL_MN10300_MN103002)
782
783 #define HAL_CLOCK_INITIALIZE( _period_ ) \
784 { \
785 volatile cyg_uint16 *timer4_br = (cyg_uint16 *)TIMER4_BR; \
786 volatile cyg_uint8 *timer4_md = (cyg_uint8 *)TIMER4_MD; \
787 volatile cyg_uint16 *timer5_br = (cyg_uint16 *)TIMER5_BR; \
788 volatile cyg_uint8 *timer5_md = (cyg_uint8 *)TIMER5_MD; \
789 \
790 /* Set timers 4 and 5 into cascade mode */ \
791 \
792 *timer5_br = (_period_)>>16; \
793 \
794 *timer5_md = 0x40; \
795 *timer5_md = 0x83; \
796 \
797 *timer4_br = (_period_)&0x0000FFFF; \
798 \
799 *timer4_md = 0x40; \
800 *timer4_md = 0x80; \
801 }
802
803 #else
804
805 #error Undefined MN10300 model
806
807 #endif
808
809 #define HAL_CLOCK_RESET( _vector_, _period_ )
810
811 #if 0 //def CYG_HAL_MN10300_SIM
812
813 // This timer counts down, so subtract from set value.
814 #define HAL_CLOCK_READ( _pvalue_ ) \
815 { \
816 volatile cyg_uint32 *timer = (cyg_uint32 *) \
817 (OEA_DEV + PAL_PERIODIC_TIMER); \
818 volatile cyg_uint32 *value = (cyg_uint32 *) \
819 (OEA_DEV + PAL_PERIODIC_VALUE); \
820 cyg_uint32 t,v; \
821 t = *timer; \
822 v = *value; \
823 *(_pvalue_) = HAL_SWAP(t) - HAL_SWAP(v); \
824 }
825
826 #else // CYG_HAL_MN10300_SIM not
827 #define HAL_CLOCK_READ( _pvalue_ ) \
828 { \
829 volatile cyg_uint16 *timer4_cr = (cyg_uint16 *)TIMER4_CR; \
830 volatile cyg_uint16 *timer5_cr = (cyg_uint16 *)TIMER5_CR; \
831 \
832 cyg_uint16 t5; \
833 cyg_uint16 t4; \
834 \
835 /* Loop reading the two timers until we can read t5 twice */ \
836 /* with the same value. This avoids getting silly times if */ \
837 /* the timers carry between reading the two regs. */ \
838 do { \
839 t5 = *timer5_cr; \
840 t4 = *timer4_cr; \
841 } while( t5 != *timer5_cr ); \
842 \
843 *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD - ((t5<<16) + t4); \
844 }
845
846 // FIXME: above line should not use CYGNUM_KERNEL_COUNTERS_RTC_PERIOD since
847 // this means the HAL gets configured by kernel options even when the
848 // kernel is disabled!
849
850 #endif // CYG_HAL_MN10300_SIM
851 315
852 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY 316 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
853 #define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_) 317 #define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_)
854 #endif 318 #endif
855 319