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comparison packages/devs/serial/mips/vrc4373/current/src/vrc4373_serial.h @ 82:6736c52df507 ecos-sw-2000-04-14

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Merge from eCos master repository on 2000-04-14-13:35:46-BST
author jlarmour
date Tue, 18 Apr 2000 21:51:55 +0000
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81:89fef2181d7d 82:6736c52df507
1 #ifndef CYGONCE_MIPS_VRC4373_SERIAL_H
2 #define CYGONCE_MIPS_VRC4373_SERIAL_H
3
4 // ====================================================================
5 //
6 // aeb_serial.h
7 //
8 // Device I/O - Description of Mips VRC4373 serial hardware
9 //
10 // ====================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Red Hat eCos Public License
15 // Version 1.1 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://www.redhat.com/
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Configurable Operating System,
25 // released September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Red Hat.
28 // Portions created by Red Hat are
29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
30 // All Rights Reserved.
31 // -------------------------------------------
32 //
33 //####COPYRIGHTEND####
34 // ====================================================================
35 //#####DESCRIPTIONBEGIN####
36 //
37 // Author(s): gthomas
38 // Contributors: gthomas
39 // Date: 1999-04-15
40 // Purpose: Internal interfaces for serial I/O drivers
41 // Description:
42 //
43 //####DESCRIPTIONEND####
44 //
45 // ====================================================================
46
47 // Description of serial ports on Mips VRC4373
48 // Based on Zilog 85C30 SCC
49
50 struct serial_port {
51 unsigned char _byte[16];
52 };
53
54 #define scc_ctl _byte[0]
55 #define scc_dat _byte[8]
56
57 #define R0 0 /* Register selects */
58 #define R1 1
59 #define R2 2
60 #define R3 3
61 #define R4 4
62 #define R5 5
63 #define R6 6
64 #define R7 7
65 #define R8 8
66 #define R9 9
67 #define R10 10
68 #define R11 11
69 #define R12 12
70 #define R13 13
71 #define R14 14
72 #define R15 15
73
74 /* Write Register 0 */
75 #define WR0_NullCode 0x00 /* Null Code */
76 #define WR0_PointHigh 0x08 /* Select upper half of registers */
77 #define WR0_ResExtInt 0x10 /* Reset Ext. Status Interrupts */
78 #define WR0_SendAbort 0x18 /* HDLC Abort */
79 #define WR0_ResRxIntFC 0x20 /* Reset RxINT on First Character */
80 #define WR0_ResTxP 0x28 /* Reset TxINT Pending */
81 #define WR0_ErrReset 0x30 /* Error Reset */
82 #define WR0_ResHiIUS 0x38 /* Reset highest IUS */
83
84 #define WR0_ResRxCRC 0x40 /* Reset Rx CRC Checker */
85 #define WR0_ResTxCRC 0x80 /* Reset Tx CRC Checker */
86 #define WR0_ResEOMlatch 0xC0 /* Reset EOM latch */
87
88 /* Write Register 1 */
89
90 #define WR1_ExtIntEnab 0x01 /* Ext Int Enable */
91 #define WR1_TxIntEnab 0x02 /* Tx Int Enable */
92 #define WR1_ParSpec 0x04 /* Parity is special condition */
93
94 #define WR1_RxIntDisab 0x00 /* Rx Int Disable */
95 #define WR1_RxIntFCE 0x08 /* Rx Int on First Character Only or Error */
96 #define WR1_IntAllRx 0x10 /* Int on all Rx Characters or error */
97 #define WR1_IntErrRx 0x18 /* Int on error only */
98
99 #define WR1_WtRdyRT 0x20 /* Wait/Ready on R/T */
100 #define WR1_WtFnRdyFn 0x40 /* Wait/FN/Ready FN */
101 #define WR1_WtRdyEnab 0x80 /* Wait/Ready Enable */
102
103 /* Write Register #2 (Interrupt Vector) */
104
105 /* Write Register 3 */
106
107 #define WR3_RxEnable 0x01 /* Rx Enable */
108 #define WR3_SyncInhibit 0x02 /* Sync Character Load Inhibit */
109 #define WR3_AddrSearch 0x04 /* Address Search Mode (SDLC) */
110 #define WR3_RxCRC_ENAB 0x08 /* Rx CRC Enable */
111 #define WR3_EntHuntMode 0x10 /* Enter Hunt Mode */
112 #define WR3_AutoEnab 0x20 /* Auto Enables */
113 #define WR3_Rx5 0x00 /* Rx 5 Bits/Character */
114 #define WR3_Rx7 0x40 /* Rx 7 Bits/Character */
115 #define WR3_Rx6 0x80 /* Rx 6 Bits/Character */
116 #define WR3_Rx8 0xc0 /* Rx 8 Bits/Character */
117 #define WR3_RxNbitsMask 0xc0
118
119 /* Write Register 4 */
120
121 #define WR4_ParityEn 0x01 /* Parity Enable */
122 #define WR4_ParityEven 0x02 /* Parity Even/Odd* */
123
124 #define WR4_SyncEnable 0x00 /* Sync Modes Enable */
125 #define WR4_SB1 0x04 /* 1 stop bit/char */
126 #define WR4_SB15 0x08 /* 1.5 stop bits/char */
127 #define WR4_SB2 0x0c /* 2 stop bits/char */
128 #define WR4_SB_MASK 0x0c
129
130 #define WR4_Monsync 0x00 /* 8 Bit Sync character */
131 #define WR4_Bisync 0x10 /* 16 bit sync character */
132 #define WR4_SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
133 #define WR4_EXtSync 0x30 /* External Sync Mode */
134
135 #define WR4_X1CLK 0x00 /* x1 clock mode */
136 #define WR4_X16CLK 0x40 /* x16 clock mode */
137 #define WR4_X32CLK 0x80 /* x32 clock mode */
138 #define WR4_X64CLK 0xC0 /* x64 clock mode */
139 #define WR4_XCLK_MASK 0xC0
140
141 /* Write Register 5 */
142
143 #define WR5_TxCRCEnab 0x01 /* Tx CRC Enable */
144 #define WR5_RTS 0x02 /* RTS */
145 #define WR5_SDLC_CRC 0x04 /* SDLC/CRC-16 */
146 #define WR5_TxEnable 0x08 /* Tx Enable */
147 #define WR5_SendBreak 0x10 /* Send Break */
148 #define WR5_Tx5 0x00 /* Tx 5 bits (or less)/character */
149 #define WR5_Tx7 0x20 /* Tx 7 bits/character */
150 #define WR5_Tx6 0x40 /* Tx 6 bits/character */
151 #define WR5_Tx8 0x60 /* Tx 8 bits/character */
152 #define WR5_TxNbitsMask 0x60
153 #define WR5_DTR 0x80 /* DTR */
154
155 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156
157 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
158
159 /* Write Register 8 (transmit buffer) */
160
161 /* Write Register 9 (Master interrupt control) */
162 #define WR9_VIS 0x01 /* Vector Includes Status */
163 #define WR9_NoVector 0x02 /* No Vector */
164 #define WR9_DLC 0x04 /* Disable Lower Chain */
165 #define WR9_MIE 0x08 /* Master Interrupt Enable */
166 #define WR9_StatHi 0x10 /* Status high */
167 #define WR9_NoReset 0x00 /* No reset on write to R9 */
168 #define WR9_ResetB 0x40 /* Reset channel B */
169 #define WR9_ResetA 0x80 /* Reset channel A */
170 #define WR9_HwReset 0xc0 /* Force hardware reset */
171
172 /* Write Register 10 (misc control bits) */
173 #define WR10_Bit6 0x01 /* 6 bit/8bit sync */
174 #define WR10_LoopMode 0x02 /* SDLC Loop mode */
175 #define WR10_AbrtUnder 0x04 /* Abort/flag on SDLC xmit underrun */
176 #define WR10_MarkIdle 0x08 /* Mark/flag on idle */
177 #define WR10_GAOP 0x10 /* Go active on poll */
178 #define WR10_NRZ 0x00 /* NRZ mode */
179 #define WR10_NRZI 0x20 /* NRZI mode */
180 #define WR10_FM1 0x40 /* FM1 (transition = 1) */
181 #define WR10_FM0 0x60 /* FM0 (transition = 0) */
182 #define WR10_CRCPS 0x80 /* CRC Preset I/O */
183
184 /* Write Register 11 (Clock Mode control) */
185 #define WR11_TRxCXT 0x00 /* TRxC = Xtal output */
186 #define WR11_TRxCTC 0x01 /* TRxC = Transmit clock */
187 #define WR11_TRxCBR 0x02 /* TRxC = BR Generator Output */
188 #define WR11_TRxCDP 0x03 /* TRxC = DPLL output */
189 #define WR11_TRxCOI 0x04 /* TRxC O/I */
190 #define WR11_TxCRTxCP 0x00 /* Transmit clock = RTxC pin */
191 #define WR11_TxCTRxCP 0x08 /* Transmit clock = TRxC pin */
192 #define WR11_TxCBR 0x10 /* Transmit clock = BR Generator output */
193 #define WR11_TxCDPLL 0x18 /* Transmit clock = DPLL output */
194 #define WR11_RxCRTxCP 0x00 /* Receive clock = RTxC pin */
195 #define WR11_RxCTRxCP 0x20 /* Receive clock = TRxC pin */
196 #define WR11_RxCBR 0x40 /* Receive clock = BR Generator output */
197 #define WR11_RxCDPLL 0x60 /* Receive clock = DPLL output */
198 #define WR11_RTxCX 0x80 /* RTxC Xtal/No Xtal */
199
200 /* Write Register 12 (lower byte of baud rate generator time constant) */
201
202 /* Write Register 13 (upper byte of baud rate generator time constant) */
203
204 /* Write Register 14 (Misc control bits) */
205 #define WR14_BRenable 0x01 /* Baud rate generator enable */
206 #define WR14_BRSRC 0x02 /* Baud rate generator source */
207 #define WR14_DTRreq 0x04 /* DTR/Request function */
208 #define WR14_AutoEcho 0x08 /* Auto Echo */
209 #define WR14_LoopBack 0x10 /* Local loopback */
210 #define WR14_Search 0x20 /* Enter search mode */
211 #define WR14_RMC 0x40 /* Reset missing clock */
212 #define WR14_NoDPLL 0x60 /* Disable DPLL */
213 #define WR14_SSBR 0x80 /* Set DPLL source = BR generator */
214 #define WR14_SSRTxC 0xa0 /* Set DPLL source = RTxC */
215 #define WR14_SFMM 0xc0 /* Set FM mode */
216 #define WR14_SNRZI 0xe0 /* Set NRZI mode */
217
218 /* Write Register 15 (external/status interrupt control) */
219 #define WR15_ZCIE 0x02 /* Zero count IE */
220 #define WR15_DCDIE 0x08 /* DCD IE */
221 #define WR15_SYNCIE 0x10 /* Sync/hunt IE */
222 #define WR15_CTSIE 0x20 /* CTS IE */
223 #define WR15_TxUIE 0x40 /* Tx Underrun/EOM IE */
224 #define WR15_BRKIE 0x80 /* Break/Abort IE */
225
226 /* Read Register 0 */
227 #define RR0_RxAvail 0x01 /* Rx Character Available */
228 #define RR0_Zcount 0x02 /* Zero count */
229 #define RR0_TxEmpty 0x04 /* Tx Buffer empty */
230 #define RR0_DCD 0x08 /* DCD */
231 #define RR0_SyncHunt 0x10 /* Sync/hunt */
232 #define RR0_CTS 0x20 /* CTS */
233 #define RR0_TxEOM 0x40 /* Tx underrun */
234 #define RR0_BrkAbort 0x80 /* Break/Abort */
235
236 /* Read Register 1 */
237 #define RR1_AllSent 0x01 /* All sent */
238 /* Residue Data for 8 Rx bits/char programmed */
239 #define RR1_RES3 0x08 /* 0/3 */
240 #define RR1_RES4 0x04 /* 0/4 */
241 #define RR1_RES5 0x0c /* 0/5 */
242 #define RR1_RES6 0x02 /* 0/6 */
243 #define RR1_RES7 0x0a /* 0/7 */
244 #define RR1_RES8 0x06 /* 0/8 */
245 #define RR1_RES18 0x0e /* 1/8 */
246 #define RR1_RES28 0x00 /* 2/8 */
247 /* Special Rx Condition Interrupts */
248 #define RR1_PariryError 0x10 /* Parity error */
249 #define RR1_RxOverrun 0x20 /* Rx Overrun Error */
250 #define RR1_FrameError 0x40 /* CRC/Framing Error */
251 #define RR1_EndOfFrame 0x80 /* End of Frame (SDLC) */
252
253 /* Read Register 2 (channel b only) - Interrupt vector */
254
255 /* Read Register 3 (interrupt pending register) ch a only */
256 #define RR3_BExt 0x01 /* Channel B Ext/Stat IP */
257 #define RR3_BTxIP 0x02 /* Channel B Tx IP */
258 #define RR3_BRxIP 0x04 /* Channel B Rx IP */
259 #define RR3_AExt 0x08 /* Channel A Ext/Stat IP */
260 #define RR3_ATxIP 0x10 /* Channel A Tx IP */
261 #define RR3_ARxIP 0x20 /* Channel A Rx IP */
262
263 /* Read Register 8 (receive data register) */
264
265 /* Read Register 10 (misc status bits) */
266 #define RR10_OnLoop 0x02 /* On loop */
267 #define RR10_LoopSend 0x10 /* Loop sending */
268 #define RR10_Clk2Mis 0x40 /* Two clocks missing */
269 #define RR10_Clk1Mis 0x80 /* One clock missing */
270
271 /* Read Register 12 (lower byte of baud rate generator constant) */
272
273 /* Read Register 13 (upper byte of baud rate generator constant) */
274
275 /* Read Register 15 (value of WR 15) */
276
277 #define BRTC(brate) (( ((unsigned) DUART_CLOCK) / (2*(brate)*SCC_CLKMODE_TC)) - 2)
278 #define DUART_CLOCK 4915200 /* Z8530 duart */
279 #define SCC_CLKMODE_TC 16 /* Always run x16 clock for async modes */
280
281 static unsigned char select_word_length_WR3[] = {
282 WR3_Rx5, // 5 bits / word (char)
283 WR3_Rx6,
284 WR3_Rx7,
285 WR3_Rx8
286 };
287
288 static unsigned char select_word_length_WR5[] = {
289 WR5_Tx5, // 5 bits / word (char)
290 WR5_Tx6,
291 WR5_Tx7,
292 WR5_Tx8
293 };
294
295 static unsigned char select_stop_bits[] = {
296 0,
297 WR4_SB1, // 1 stop bit
298 WR4_SB15, // 1.5 stop bit
299 WR4_SB2 // 2 stop bits
300 };
301
302 static unsigned char select_parity[] = {
303 0, // No parity
304 WR4_ParityEn | WR4_ParityEven, // Even parity
305 WR4_ParityEn, // Odd parity
306 0xFF, // Mark parity
307 0xFF, // Space parity
308 };
309
310 static cyg_int32 select_baud[] = {
311 0, // Unused
312 50, // 50
313 75, // 75
314 110, // 110
315 0, // 134.5
316 150, // 150
317 200, // 200
318 300, // 300
319 600, // 600
320 1200, // 1200
321 1800, // 1800
322 2400, // 2400
323 3600, // 3600
324 4800, // 4800
325 7200, // 7200
326 9600, // 9600
327 14400, // 14400
328 19200, // 19200
329 38400, // 38400
330 0, // 57600
331 0, // 115200
332 0, // 230400
333 };
334
335 #endif // CYGONCE_MIPS_VRC4373_SERIAL_H