Mercurial > ecos-v2_0-branch
comparison packages/hal/mips/arch/current/include/hal_intr.h @ 10:d3fbcdfa1b2f ecos-sw-1999-05-29
Merge from eCos master repository on 1999-05-29-00:13:11-BST
| author | jlarmour |
|---|---|
| date | Fri, 28 May 1999 16:43:09 +0000 |
| parents | ece80412419a |
| children | 7253dcc42a09 |
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| 9:95cc44ea0068 | 10:d3fbcdfa1b2f |
|---|---|
| 166 // VSR table | 166 // VSR table |
| 167 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1]; | 167 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1]; |
| 168 | 168 |
| 169 //-------------------------------------------------------------------------- | 169 //-------------------------------------------------------------------------- |
| 170 // Default ISR | 170 // Default ISR |
| 171 // The #define is used to test whether this routine exists, and to allow | |
| 172 // us to call it. | |
| 171 | 173 |
| 172 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); | 174 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); |
| 175 | |
| 176 #define HAL_DEFAULT_ISR hal_default_isr | |
| 173 | 177 |
| 174 //-------------------------------------------------------------------------- | 178 //-------------------------------------------------------------------------- |
| 175 // Interrupt state storage | 179 // Interrupt state storage |
| 176 | 180 |
| 177 typedef cyg_uint32 CYG_INTERRUPT_STATE; | 181 typedef cyg_uint32 CYG_INTERRUPT_STATE; |
| 278 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ | 282 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ |
| 279 CYG_MACRO_START \ | 283 CYG_MACRO_START \ |
| 280 cyg_uint32 _index_; \ | 284 cyg_uint32 _index_; \ |
| 281 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ | 285 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ |
| 282 \ | 286 \ |
| 283 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ | 287 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ |
| 284 (_state_) = 0; \ | 288 (_state_) = 0; \ |
| 285 else \ | 289 else \ |
| 286 (_state_) = 1; \ | 290 (_state_) = 1; \ |
| 287 CYG_MACRO_END | 291 CYG_MACRO_END |
| 288 | 292 |
| 289 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ | 293 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ |
| 290 { \ | 294 { \ |
| 291 cyg_uint32 _index_; \ | 295 cyg_uint32 _index_; \ |
| 292 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ | 296 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ |
| 293 \ | 297 \ |
| 294 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ | 298 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ |
| 295 { \ | 299 { \ |
| 296 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ | 300 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ |
| 297 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ | 301 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ |
| 298 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ | 302 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ |
| 299 } \ | 303 } \ |
| 304 cyg_uint32 _index_; \ | 308 cyg_uint32 _index_; \ |
| 305 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ | 309 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ |
| 306 \ | 310 \ |
| 307 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ | 311 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ |
| 308 { \ | 312 { \ |
| 309 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \ | 313 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \ |
| 310 hal_interrupt_data[_index_] = 0; \ | 314 hal_interrupt_data[_index_] = 0; \ |
| 311 hal_interrupt_objects[_index_] = 0; \ | 315 hal_interrupt_objects[_index_] = 0; \ |
| 312 } \ | 316 } \ |
| 313 } | 317 } |
| 314 | 318 |
