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comparison packages/hal/powerpc/arch/current/src/vectors.S @ 68:f74b2666b30d ecos-sw-2000-02-04

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Merge from eCos master repository on 2000-02-04-07:47:04-GMT
author jlarmour
date Fri, 04 Feb 2000 15:01:01 +0000
parents bf00f99aec69
children c5536bad4c24
comparison
equal deleted inserted replaced
67:34eb8438750d 68:f74b2666b30d
76 # DR = data address translation 76 # DR = data address translation
77 # RI = recoverable interrupt 77 # RI = recoverable interrupt
78 78
79 #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_IR | MSR_DR | MSR_RI) 79 #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_IR | MSR_DR | MSR_RI)
80 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) 80 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS)
81 # ifdef CYG_HAL_POWERPC_COPY_VECTORS 81 # ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS
82 # define CYG_MSR CYG_MSR_COMMON 82 # define CYG_MSR CYG_MSR_COMMON
83 # else 83 # else
84 # define CYG_MSR (CYG_MSR_COMMON | MSR_IP) 84 # define CYG_MSR (CYG_MSR_COMMON | MSR_IP)
85 # endif 85 # endif
86 #endif 86 #endif
87 #ifdef CYG_HAL_STARTUP_RAM 87 #ifdef CYG_HAL_STARTUP_RAM
88 #define CYG_MSR CYG_MSR_COMMON 88 #define CYG_MSR CYG_MSR_COMMON
89 #endif 89 #endif
90 #ifdef CYG_HAL_POWERPC_SIM 90 #ifdef CYGPKG_HAL_POWERPC_SIM
91 # When building for SIM, don~t enable MMU -- it~s not needed since caches 91 # When building for SIM, don~t enable MMU -- it~s not needed since caches
92 # are disabled, and there is a runtime simulation overhead. 92 # are disabled, and there is a runtime simulation overhead.
93 #undef CYG_MSR 93 #undef CYG_MSR
94 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR | MSR_DR)) 94 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR | MSR_DR))
95 #endif 95 #endif
205 exception_vector reserved_00f00 205 exception_vector reserved_00f00
206 206
207 # There are some additional vectors defined 207 # There are some additional vectors defined
208 # on various implementations. 208 # on various implementations.
209 209
210 #ifdef CYG_HAL_POWERPC_MPC8xx 210 #ifdef CYGPKG_HAL_POWERPC_MPC8xx
211 # MPC8xx vectors 211 # MPC8xx vectors
212 212
213 exception_vector software_emu 213 exception_vector software_emu
214 exception_vector instruction_tlb_miss 214 exception_vector instruction_tlb_miss
215 exception_vector data_tlb_miss 215 exception_vector data_tlb_miss
239 239
240 _start: 240 _start:
241 # Initialize CPU 241 # Initialize CPU
242 bl _init_CPU 242 bl _init_CPU
243 243
244 #ifdef CYG_HAL_POWERPC_MPC8xx 244 #ifdef CYGPKG_HAL_POWERPC_MPC8xx
245 # Disable special MPC8xx "development support" which 245 # Disable special MPC8xx "development support" which
246 # suppresses trace exceptions. The CPU seems to hang, not 246 # suppresses trace exceptions. The CPU seems to hang, not
247 # executing from offset 0x1e00(?) as expected. 247 # executing from offset 0x1e00(?) as expected.
248 248
249 lwi r3,0x00000007 249 lwi r3,0x00000007
290 blt 1b # loop if not yet done 290 blt 1b # loop if not yet done
291 2: 291 2:
292 #endif 292 #endif
293 293
294 294
295 #ifdef CYG_HAL_POWERPC_COPY_VECTORS // only for StubRom-supported startup 295 #ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS // only for StubRom-supported startup
296 296
297 #ifdef CYG_HAL_POWERPC_MBX 297 #ifdef CYGPKG_HAL_POWERPC_MBX
298 # define CYGPRI_STUBROM_HAS_RAM_VECTORS 298 # define CYGPRI_STUBROM_HAS_RAM_VECTORS
299 #endif 299 #endif
300 300
301 #ifdef CYGPRI_STUBROM_HAS_RAM_VECTORS 301 #ifdef CYGPRI_STUBROM_HAS_RAM_VECTORS
302 # ifdef CYG_HAL_STARTUP_RAM 302 # ifdef CYG_HAL_STARTUP_RAM
518 ## system is using isr tables or chaining, and depending on the interrupt 518 ## system is using isr tables or chaining, and depending on the interrupt
519 ## controller in the system. 519 ## controller in the system.
520 520
521 ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h. 521 ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h.
522 522
523 #ifdef CYG_HAL_POWERPC_MPC8xx 523 #ifdef CYGPKG_HAL_POWERPC_MPC8xx
524 524
525 ## First level decoding of MPC8xx SIU interrupt controller. 525 ## First level decoding of MPC8xx SIU interrupt controller.
526 526
527 #define CYG_ISR_TABLE_SIZE 59 527 #define CYG_ISR_TABLE_SIZE 59
528 528
687 1: 687 1:
688 #endif 688 #endif
689 689
690 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING 690 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
691 691
692 #ifdef CYG_HAL_POWERPC_MPC8xx 692 #ifdef CYGPKG_HAL_POWERPC_MPC8xx
693 # The CPM controller allows nested interrupts. However, 693 # The CPM controller allows nested interrupts. However,
694 # it sits on the back of the SIU controller which has no 694 # it sits on the back of the SIU controller which has no
695 # HW support for this. In effect, SW masking of lower 695 # HW support for this. In effect, SW masking of lower
696 # priority IRQs in the SIU would be required for this to work. 696 # priority IRQs in the SIU would be required for this to work.
697 #endif 697 #endif
892 #endif 892 #endif
893 893
894 #--------------------------------------------------------------------------- 894 #---------------------------------------------------------------------------
895 # Code for putting the CPU in a post-reset state; disabling MMU and caches. 895 # Code for putting the CPU in a post-reset state; disabling MMU and caches.
896 _init_CPU: 896 _init_CPU:
897 #ifdef CYG_HAL_POWERPC_MPC8xx 897 #ifdef CYGPKG_HAL_POWERPC_MPC8xx
898 lwi r3,CYGARC_REG_DC_CMD_CD 898 lwi r3,CYGARC_REG_DC_CMD_CD
899 sync 899 sync
900 mtspr CYGARC_REG_DC_CST,r3 900 mtspr CYGARC_REG_DC_CST,r3
901 lwi r3,CYGARC_REG_IC_CMD_CD 901 lwi r3,CYGARC_REG_IC_CMD_CD
902 isync 902 isync
941 .long __default_exception_vsr # system call 941 .long __default_exception_vsr # system call
942 .long __default_exception_vsr # trace 942 .long __default_exception_vsr # trace
943 .long __default_exception_vsr # floating point assist 943 .long __default_exception_vsr # floating point assist
944 .long __default_exception_vsr # reserved 0x0f00 944 .long __default_exception_vsr # reserved 0x0f00
945 945
946 #ifdef CYG_HAL_POWERPC_MPC8xx 946 #ifdef CYGPKG_HAL_POWERPC_MPC8xx
947 947
948 # Implementation defined vectors 948 # Implementation defined vectors
949 .long __default_exception_vsr # software emulation 949 .long __default_exception_vsr # software emulation
950 .long __default_exception_vsr # instruction TLB miss 950 .long __default_exception_vsr # instruction TLB miss
951 .long __default_exception_vsr # data TLB miss 951 .long __default_exception_vsr # data TLB miss