Mercurial > ecos-v2_0-branch
diff packages/hal/mips/arch/current/include/hal_cache.h @ 18:7253dcc42a09 ecos-sw-1999-06-25
Merge from eCos master repository on 1999-06-25-15:31:50-BST
| author | jlarmour |
|---|---|
| date | Fri, 25 Jun 1999 08:28:05 +0000 |
| parents | d3fbcdfa1b2f |
| children | 306eee292492 |
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--- a/packages/hal/mips/arch/current/include/hal_cache.h +++ b/packages/hal/mips/arch/current/include/hal_cache.h @@ -108,19 +108,16 @@ // Synchronize the contents of the cache with memory. // This uses the index-writeback-invalidate operation. #ifndef HAL_DCACHE_SYNC_DEFINED -#define HAL_DCACHE_SYNC() \ -{ \ - register CYG_ADDRESS _baddr_ = 0x80000000; \ - register CYG_ADDRESS _addr_ = 0x80000000; \ - register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED(_state_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_DCACHE_ENABLE(); \ +#define HAL_DCACHE_SYNC() \ +{ \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); } \ } #endif @@ -137,19 +134,16 @@ // and then lock the cache so that it stays there. // This uses the fetch-and-lock cache operation. #ifndef HAL_DCACHE_LOCK_DEFINED -#define HAL_DCACHE_LOCK(_base_, _asize_) \ -CYG_MACRO_START \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED(_state_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_DCACHE_ENABLE(); \ +#define HAL_DCACHE_LOCK(_base_, _asize_) \ +CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); } \ CYG_MACRO_END #endif @@ -177,57 +171,48 @@ CYG_MACRO_END // for the given address range. // This uses the hit-writeback-invalidate cache operation. #ifndef HAL_DCACHE_FLUSH_DEFINED -#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED(_state_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_DCACHE_ENABLE(); \ +#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); } \ } #endif // Invalidate cache lines in the given range without writing to memory. // This uses the hit-invalidate cache operation. #ifndef HAL_DCACHE_INVALIDATE_DEFINED -#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED(_state_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_DCACHE_ENABLE(); \ +#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); } \ } #endif // Write dirty cache lines to memory for the given address range. // This uses the hit-writeback cache operation. #ifndef HAL_DCACHE_STORE_DEFINED -#define HAL_DCACHE_STORE( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED(_state_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_DCACHE_ENABLE(); \ +#define HAL_DCACHE_STORE( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); } \ } #endif @@ -263,18 +248,15 @@ CYG_MACRO_END // Invalidate the entire cache // This uses the index-invalidate cache operation. #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED -#define HAL_ICACHE_INVALIDATE_ALL() \ -{ \ - register CYG_ADDRESS _baddr_ = 0x80000000; \ - register CYG_ADDRESS _addr_ = 0x80000000; \ - register CYG_WORD _state_; \ - HAL_ICACHE_IS_ENABLED(_state_); \ - HAL_ICACHE_DISABLE(); \ - for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_ICACHE_ENABLE(); \ +#define HAL_ICACHE_INVALIDATE_ALL() \ +{ \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); } \ } #endif @@ -291,19 +273,16 @@ CYG_MACRO_END // and then lock the cache so that it stays there. // This uses the fetch-and-lock cache operation. #ifndef HAL_ICACHE_LOCK_DEFINED -#define HAL_ICACHE_LOCK(_base_, _asize_) \ -CYG_MACRO_START \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_ICACHE_IS_ENABLED(_state_); \ - HAL_ICACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_ICACHE_ENABLE(); \ +#define HAL_ICACHE_LOCK(_base_, _asize_) \ +CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); } \ CYG_MACRO_END #endif @@ -323,19 +302,16 @@ CYG_MACRO_END // Invalidate cache lines in the given range without writing to memory. // This uses the hit-invalidate cache operation. #ifndef HAL_ICACHE_INVALIDATE_DEFINED -#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_ICACHE_IS_ENABLED(_state_); \ - HAL_ICACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); \ - } \ - HAL_ICACHE_ENABLE(); \ +#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); } \ } #endif