Mercurial > ecos-v2_0-branch
changeset 14:01ce82f3e11a ecos-sw-1999-06-11
Merge from eCos master repository on 1999-06-11-17:05:41-BST
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,14 @@ +1999-06-09 Gary Thomas <gthomas@cygnus.co.uk> + + * pkgconf.tcl (pkgconf::produce_misc_files): MLT files need + actual platform name, not base platform, to be compatible with + the ConfigTool. + +1999-06-07 Gary Thomas <gthomas@cygnus.co.uk> + + * pkgconf.tcl (pkgconf::process_arguments): Fix GUI problem with + new 'base_platform' stuff. + 1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> * pkgconf.tcl (command_prefix): Allow command_prefix to be overridden
--- a/packages/hal/arm/arch/current/ChangeLog +++ b/packages/hal/arm/arch/current/ChangeLog @@ -1,3 +1,7 @@ +1999-06-09 Gary Thomas <gthomas@cygnus.co.uk> + + * src/vectors.S (reset_vector): Streamline ROM/STUBS code. + 1999-05-25 Gary Thomas <gthomas@cygnus.co.uk> * src/vectors.S (_eCos_id): Add version string. Useful for
--- a/packages/hal/arm/arch/current/include/hal_mmu.h +++ b/packages/hal/arm/arch/current/include/hal_mmu.h @@ -65,8 +65,9 @@ #define MMU_AP_ap1_Any 0x0C0 #define MMU_AP_ap2_Any 0x300 #define MMU_AP_ap3_Any 0xC00 +#define MMU_AP_All (MMU_AP_ap0_Any|MMU_AP_ap1_Any|MMU_AP_ap2_Any|MMU_AP_ap3_Any) -#define MMU_AP_All (MMU_AP_ap0_Any|MMU_AP_ap1_Any|MMU_AP_ap2_Any|MMU_AP_ap3_Any) +#define MMU_DOMAIN(x) ((x)<<5) #define MMU_PAGE_SIZE 0x1000 #define MMU_SECTION_SIZE 0x100000
--- a/packages/hal/arm/arch/current/src/vectors.S +++ b/packages/hal/arm/arch/current/src/vectors.S @@ -126,15 +126,18 @@ reset_vector: str r2,[r0,#0x24] ldr r2,[r1,#0x08] // software interrupt str r2,[r0,#0x08] +#if defined(CYG_HAL_STARTUP_RAM) +// Ugly hack to get into supervisor mode ldr r2,[r1,#0x40] str r2,[r0,#0x28] swi // switch to supervisor mode +#endif // ========================================================================= // Real startup code. We jump here from the reset vector to set up the world. .globl start start: - + #if defined(CYG_HAL_STARTUP_RAM) && \ !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) // If we get restarted, hang here to avoid corrupting memory @@ -532,6 +535,9 @@ 10: str r4,[r3] #endif +// TEMP + mov r0,v6 +// TEMP bl hal_IRQ_handler // determine interrupt source mov v1,r0 // returned vector # @@ -634,6 +640,7 @@ hal_interrupt_stack_call_pending_DSRs: ldmfd sp!,{r4,r5,pc} // return #endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + // Dummy functions
--- a/packages/hal/common/current/ChangeLog +++ b/packages/hal/common/current/ChangeLog @@ -1,3 +1,7 @@ +1999-06-10 Gary Thomas <gthomas@cygnus.co.uk> + + * src/hal_stub.c: Need to init register pointer. + 1999-05-31 Jesper Skov <jskov@cygnus.co.uk> * src/hal_stub.c: Respect HAL_BREAKINST_SIZE setting.
--- a/packages/hal/common/current/src/hal_stub.c +++ b/packages/hal/common/current/src/hal_stub.c @@ -62,9 +62,9 @@ // Saved registers. HAL_SavedRegisters *_hal_registers; -target_register_t * _registers; // Pointer to current set of registers target_register_t registers[NUMREGS]; -target_register_t alt_registers[NUMREGS] ; // Thread or saved process state +target_register_t alt_registers[NUMREGS] ; // Thread or saved process state +target_register_t * _registers = registers; // Pointer to current set of registers // Interrupt control. static volatile __PFI __interruptible_control;
--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -1,3 +1,16 @@ +1999-06-10 Nick Garnett <nickg@cygnus.co.uk> + + * include/hal_arch.h: Added macros to copy FPU registers between + HAL and GDB register save states. + +1999-06-08 Nick Garnett <nickg@cygnus.co.uk> + + * src/vectors.S: Dummy __gccmain did not have a delay slot after + the "jr ra". + + * include/hal_arch.h: Make value of CYGNUM_HAL_STACK_SIZE_TYPICAL + always be greater than CYGNUM_HAL_STACK_SIZE_MINIMUM. + 1999-06-02 Jonathan Larmour <jlarmour@cygnus.co.uk> * src/hal_misc.c (cyg_hal_invoke_constructors):
--- a/packages/hal/mips/arch/current/include/hal_arch.h +++ b/packages/hal/mips/arch/current/include/hal_arch.h @@ -116,10 +116,10 @@ externC cyg_uint32 hal_msbit_index(cyg_u // Optional FPU context initialization #ifdef CYGHWR_HAL_MIPS_FPU -#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ) \ -{ \ - for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->f[_i_] = (_id_)|_i_; \ - (_regs_)->fcr31 = 0; \ +#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ) \ +{ \ + for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->f[_i_] = (_id_)|0xFF00|_i_; \ + (_regs_)->fcr31 = 0; \ } #else #define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ) @@ -209,6 +209,27 @@ asm volatile (" .globl " #_label_ ";" #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ (_regs_) = (HAL_SavedRegisters *)(_sp_) +// If the CPU has an FPU, we also need to move the FPU registers. +#ifdef CYGHWR_HAL_MIPS_FPU +#define HAL_GET_GDB_FPU_REGISTERS( _regval_ , _regs_ ) \ +CYG_MACRO_START \ + int _i_; \ + for( _i_ = 0; _i_ < 32; _i_++ ) \ + _regval_[38+_i_] = (_regs_)->f[_i_]; \ + _regval_[70] = (_regs_)->fcr31; \ +CYG_MACRO_END +#define HAL_SET_GDB_FPU_REGISTERS( _regs_ , _regval_ ) \ +CYG_MACRO_START \ + int _i_; \ + for( _i_ = 0; _i_ < 32; _i_++ ) \ + (_regs_)->f[_i_] = _regval_[38+_i_]; \ + (_regs_)->fcr31 = _regval_[70]; \ +CYG_MACRO_END +#else +#define HAL_GET_GDB_FPU_REGISTERS( _regval_ , _regs_ ) +#define HAL_SET_GDB_FPU_REGISTERS( _regs_ , _regval_ ) +#endif + // Copy a set of registers from a HAL_SavedRegisters structure into a // GDB ordered array. #define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \ @@ -219,6 +240,8 @@ asm volatile (" .globl " #_label_ ";" for( _i_ = 0; _i_ < 32; _i_++ ) \ _regval_[_i_] = (_regs_)->d[_i_]; \ \ + HAL_GET_GDB_FPU_REGISTERS( _regval_, _regs_ ); \ + \ _regval_[32] = (_regs_)->sr; \ _regval_[33] = (_regs_)->lo; \ _regval_[34] = (_regs_)->hi; \ @@ -236,6 +259,8 @@ asm volatile (" .globl " #_label_ ";" for( _i_ = 0; _i_ < 32; _i_++ ) \ (_regs_)->d[_i_] = _regval_[_i_]; \ \ + HAL_SET_GDB_FPU_REGISTERS( _regs_, _regval_ ); \ + \ (_regs_)->sr = _regval_[32]; \ (_regs_)->lo = _regval_[33]; \ (_regs_)->hi = _regval_[34]; \ @@ -326,7 +351,7 @@ externC void hal_idle_thread_action(cyg_ #define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \ CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \ CYGNUM_HAL_STACK_FRAME_SIZE*8) -#define CYGNUM_HAL_STACK_SIZE_TYPICAL (2048) +#define CYGNUM_HAL_STACK_SIZE_TYPICAL (CYGNUM_HAL_STACK_SIZE_MINIMUM+1024) #else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
--- a/packages/hal/mips/arch/current/src/vectors.S +++ b/packages/hal/mips/arch/current/src/vectors.S @@ -606,12 +606,13 @@ FUNC_START(hal_interrupt_stack_call_pend FUNC_END(hal_interrupt_stack_call_pending_DSRs) #endif +##----------------------------------------------------------------------------- +## Short circuit in case any code tries to use "__gccmain()" -// Short circuit in case any code tries to use "__gccmain()" FUNC_START(__gccmain) jr ra + nop FUNC_END(__gccmain) - ##----------------------------------------------------------------------------- ## Interrupt Stack.
--- a/packages/hal/mn10300/arch/current/ChangeLog +++ b/packages/hal/mn10300/arch/current/ChangeLog @@ -1,3 +1,14 @@ +1999-06-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/hal_misc.c (cyg_hal_dcache_store): Only define for HW target. + +1999-06-07 Jesper Skov <jskov@cygnus.co.uk> + PR 20136 + * src/hal_misc.c (cyg_hal_dcache_store): + * include/hal_cache.h (HAL_DCACHE_STORE): + DCACHE store operation needs 4 register variables. Put it in a + separate function to ensure registers are availble. + 1999-05-21 Hugo Tyson <hmt@masala.cygnus.co.uk> * include/hal_intr.h: Define HAL_INTERRUPT_STACK_BASE and
--- a/packages/hal/mn10300/arch/current/include/hal_cache.h +++ b/packages/hal/mn10300/arch/current/include/hal_cache.h @@ -300,29 +300,13 @@ //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) // Write dirty cache lines to memory for the given address range. -#define HAL_DCACHE_STORE( _base_ , _size_ ) \ -{ \ - volatile register CYG_BYTE *way0 = HAL_DCACHE_PURGE_WAY0; \ - volatile register CYG_BYTE *way1 = HAL_DCACHE_PURGE_WAY1; \ - int i; \ - register CYG_ADDRWORD state; \ - \ - HAL_DCACHE_IS_ENABLED(state); \ - if (state) \ - HAL_DCACHE_DISABLE(); \ - \ - way0 += ((CYG_ADDRWORD)_base_) & 0x000007f0; \ - way1 += ((CYG_ADDRWORD)_base_) & 0x000007f0; \ - for( i = 0; i < (_size_) ; i += HAL_DCACHE_LINE_SIZE ) \ - { \ - *(CYG_ADDRWORD *)way0 = 0; \ - *(CYG_ADDRWORD *)way1 = 0; \ - way0 += HAL_DCACHE_LINE_SIZE; \ - way1 += HAL_DCACHE_LINE_SIZE; \ - } \ - if (state) \ - HAL_DCACHE_ENABLE(); \ -} + +// This functionality requires 4 register variables. To prevent register +// spilling, put the code in a separate function. +externC void cyg_hal_dcache_store(CYG_ADDRWORD base, int size); + +#define HAL_DCACHE_STORE( _base_ , _size_ ) \ + cyg_hal_dcache_store((_base_), (_size_)) // Preread the given range into the cache with the intention of reading // from it later.
--- a/packages/hal/mn10300/arch/current/src/hal_misc.c +++ b/packages/hal/mn10300/arch/current/src/hal_misc.c @@ -247,4 +247,33 @@ cyg_hal_exception_handler(HAL_SavedRegis } /*------------------------------------------------------------------------*/ +/* Cache functions. */ + +#if !defined(CYG_HAL_MN10300_SIM) && defined(CYG_HAL_MN10300_MN103002) +void cyg_hal_dcache_store(CYG_ADDRWORD base, int size) +{ + volatile register CYG_BYTE *way0 = HAL_DCACHE_PURGE_WAY0; + volatile register CYG_BYTE *way1 = HAL_DCACHE_PURGE_WAY1; + register int i; + register CYG_ADDRWORD state; + + HAL_DCACHE_IS_ENABLED(state); + if (state) + HAL_DCACHE_DISABLE(); + + way0 += base & 0x000007f0; + way1 += base & 0x000007f0; + for( i = 0; i < size; i += HAL_DCACHE_LINE_SIZE ) + { + *(CYG_ADDRWORD *)way0 = 0; + *(CYG_ADDRWORD *)way1 = 0; + way0 += HAL_DCACHE_LINE_SIZE; + way1 += HAL_DCACHE_LINE_SIZE; + } + if (state) + HAL_DCACHE_ENABLE(); +} +#endif + +/*------------------------------------------------------------------------*/ /* End of hal_misc.c */
--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,3 +1,22 @@ +1999-06-10 Hugo Tyson <hmt@cygnus.co.uk> + + * src/vectors.S (_start): Add better support for various startup + options, including CygMon loading. + + * src/PKGconf.mak (COMPILE): remove quicc_smc.c; it has been + reorganized and renamed into the FADS component. + + * include/quicc_smc.h, src/ppc_860.h, src/quicc_smc.c: removed; + reorganized and renamed into the FADS component. + +1999-06-08 Jesper Skov <jskov@cygnus.co.uk> + + * include/hal_intr.h: + * src/vectors.S (hal_vsr_table): + * src/hal_misc.c (hal_default_decrementer_isr): + Use NOP default ISR for decrementer. + Fix hal_intr macros. + 1999-06-04 Jesper Skov <jskov@cygnus.co.uk> PR 20146 * src/ppc_860.h: Added padding to some structures, reported by
--- a/packages/hal/powerpc/arch/current/include/hal_intr.h +++ b/packages/hal/powerpc/arch/current/include/hal_intr.h @@ -249,9 +249,11 @@ externC volatile CYG_ADDRESS hal_inte externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; //-------------------------------------------------------------------------- -// Default ISR +// Default ISRs externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); +externC cyg_uint32 hal_default_decrementer_isr(CYG_ADDRWORD vector, + CYG_ADDRWORD data); //-------------------------------------------------------------------------- // Interrupt state storage @@ -343,41 +345,49 @@ externC void hal_interrupt_stack_call_pe //-------------------------------------------------------------------------- // Interrupt and VSR attachment macros -#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ - CYG_MACRO_START \ - cyg_uint32 _index_; \ - HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ - \ - if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ - (_state_) = 0; \ - else \ - (_state_) = 1; \ +#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if((hal_interrupt_handlers[_index_] \ + == (CYG_ADDRESS)hal_default_decrementer_isr) \ + || (hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr)) \ + (_state_) = 0; \ + else \ + (_state_) = 1; \ CYG_MACRO_END -#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ - CYG_MACRO_START \ - cyg_uint32 _index_; \ - HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ - \ - if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ - { \ - hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ - hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \ - hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ - } \ +#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if((hal_interrupt_handlers[_index_] \ + == (CYG_ADDRESS)hal_default_decrementer_isr) \ + || (hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr)) \ + { \ + hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ + hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \ + hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ + } \ CYG_MACRO_END -#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ - CYG_MACRO_START \ - cyg_uint32 _index_; \ - HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ - \ - if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ - { \ - hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \ - hal_interrupt_data[_index_] = 0; \ - hal_interrupt_objects[_index_] = 0; \ - } \ +#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ + { \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER == (_vector_)) \ + hal_interrupt_handlers[_index_] = \ + (CYG_ADDRESS)hal_default_decrementer_isr; \ + else \ + hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \ + hal_interrupt_data[_index_] = 0; \ + hal_interrupt_objects[_index_] = 0; \ + } \ CYG_MACRO_END #define HAL_VSR_GET( _vector_, _pvsr_ ) \
deleted file mode 100644 --- a/packages/hal/powerpc/arch/current/include/quicc_smc.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef CYGONCE_QUICC_SMC_H -#define CYGONCE_QUICC_SMC_H -//============================================================================= -//####UNSUPPORTEDBEGIN#### -// -// ------------------------------------------- -// This source file has been contributed to eCos/Cygnus. It may have been -// changed slightly to provide an interface consistent with those of other -// files. -// -// The functionality and contents of this file is supplied "AS IS" -// without any form of support and will not necessarily be kept up -// to date by Cygnus. -// -// The style of programming used in this file may not comply with the -// eCos programming guidelines. Please do not use as a base for other -// files. -// -// All inquiries about this file, or the functionality provided by it, -// should be directed to the 'ecos-discuss' mailing list (see -// http://sourceware.cygnus.com/ecos/intouch.html for details). -// -// Contributed by: Kevin Hester <khester@opticworks.com> -// Maintained by: <Unmaintained> -// See also: -// Motorola's "Example Software Initializing the SMC as a UART" package -// (smc2.zip) at: -// http://www.mot.com/SPS/RISC/netcomm/tools/index.html#MPC860_table -// ------------------------------------------- -// -//####UNSUPPORTEDEND#### -//============================================================================= - -extern void cyg_smc2_init(unsigned long baudRate); -extern void cyg_smc2_putchar(char); -extern char cyg_smc2_getchar(void); - -#endif - -
--- a/packages/hal/powerpc/arch/current/src/PKGconf.mak +++ b/packages/hal/powerpc/arch/current/src/PKGconf.mak @@ -32,7 +32,7 @@ PACKAGE := hal_powerpc include ../../../../../pkgconf/pkgconf.mak LIBRARY := libtarget.a -COMPILE := hal_misc.c context.S ppc_stub.c hal_intr.c quicc_smc.c +COMPILE := hal_misc.c context.S ppc_stub.c hal_intr.c OTHER_OBJS := OTHER_TARGETS := vectors.stamp ldscript.stamp OTHER_DEPS := $(PACKAGE)_vectors.d ldscript.d
--- a/packages/hal/powerpc/arch/current/src/hal_misc.c +++ b/packages/hal/powerpc/arch/current/src/hal_misc.c @@ -157,7 +157,7 @@ cyg_hal_exception_handler(HAL_SavedRegis } //--------------------------------------------------------------------------- -// Default ISR +// Default ISRs externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) @@ -168,6 +168,17 @@ hal_default_isr(CYG_ADDRWORD vector, CYG return 0; } +// The decrementer default ISR has to do nothing. The reason is that +// decrementer interrupts cannot be disabled - if a kernel configuration +// does not use the RTC, but does use external interrupts, the decrementer +// underflow could cause a CYG_FAIL (as above) even though the user did +// not expect any decrementer interrupts to happen. +externC cyg_uint32 +hal_default_decrementer_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + return 0; +} + //--------------------------------------------------------------------------- // Idle thread action
deleted file mode 100644 --- a/packages/hal/powerpc/arch/current/src/ppc_860.h +++ /dev/null @@ -1,1312 +0,0 @@ -#ifndef CYGONCE_PPC_860_H -#define CYGONCE_PPC_860_H - -//============================================================================= -//####UNSUPPORTEDBEGIN#### -// -// ------------------------------------------- -// This source file has been contributed to eCos/Cygnus. It may have been -// changed slightly to provide an interface consistent with those of other -// files. -// -// The functionality and contents of this file is supplied "AS IS" -// without any form of support and will not necessarily be kept up -// to date by Cygnus. -// -// The style of programming used in this file may not comply with the -// eCos programming guidelines. Please do not use as a base for other -// files. -// -// All inquiries about this file, or the functionality provided by it, -// should be directed to the 'ecos-discuss' mailing list (see -// http://sourceware.cygnus.com/ecos/intouch.html for details). -// -// Contributed by: Kevin Hester <khester@opticworks.com> -// Maintained by: <Unmaintained> -// See also: -// Motorola's "Example Software Initializing the SMC as a UART" package -// (smc2.zip) at: -// http://www.mot.com/SPS/RISC/netcomm/tools/index.html#MPC860_table -// ------------------------------------------- -// -//####UNSUPPORTEDEND#### -//============================================================================= - -#include <cyg/infra/cyg_type.h> - -/****************************************************************************** -* -* Definitions of Parameter RAM entries for each peripheral and mode -* -******************************************************************************/ - -/*---------------------------------------------------------------------------*/ -/* HDLC parameter RAM (SCC) */ -/*---------------------------------------------------------------------------*/ - -struct hdlc_pram - -{ - - /*-------------------*/ - /* SCC parameter RAM */ - /*-------------------*/ - - cyg_uint16 rbase; /* RX BD base address */ - cyg_uint16 tbase; /* TX BD base address */ - cyg_uint8 rfcr; /* Rx function code */ - cyg_uint8 tfcr; /* Tx function code */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rtemp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - cyg_uint32 rcrc; /* temp receive CRC */ - cyg_uint32 tcrc; /* temp transmit CRC */ - - /*-----------------------------*/ - /* HDLC specific parameter RAM */ - /*-----------------------------*/ - - cyg_uint8 RESERVED1[4]; /* Reserved area */ - cyg_uint32 c_mask; /* CRC constant */ - cyg_uint32 c_pres; /* CRC preset */ - cyg_uint16 disfc; /* discarded frame counter */ - cyg_uint16 crcec; /* CRC error counter */ - cyg_uint16 abtsc; /* abort sequence counter */ - cyg_uint16 nmarc; /* nonmatching address rx cnt */ - cyg_uint16 retrc; /* frame retransmission cnt */ - cyg_uint16 mflr; /* maximum frame length reg */ - cyg_uint16 max_cnt; /* maximum length counter */ - cyg_uint16 rfthr; /* received frames threshold */ - cyg_uint16 rfcnt; /* received frames count */ - cyg_uint16 hmask; /* user defined frm addr mask */ - cyg_uint16 haddr1; /* user defined frm address 1 */ - cyg_uint16 haddr2; /* user defined frm address 2 */ - cyg_uint16 haddr3; /* user defined frm address 3 */ - cyg_uint16 haddr4; /* user defined frm address 4 */ - cyg_uint16 tmp; /* temp */ - cyg_uint16 tmp_mb; /* temp */ -}; - - -/*-------------------------------------------------------------------------*/ -/* ASYNC HDLC parameter RAM (SCC) */ -/*-------------------------------------------------------------------------*/ - -struct async_hdlc_pram - -{ - - /*-------------------*/ - /* SCC parameter RAM */ - /*-------------------*/ - - cyg_uint16 rbase; /* RX BD base address */ - cyg_uint16 tbase; /* TX BD base address */ - cyg_uint8 rfcr; /* Rx function code */ - cyg_uint8 tfcr; /* Tx function code */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rtemp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - cyg_uint32 rcrc; /* temp receive CRC */ - cyg_uint32 tcrc; /* temp transmit CRC */ - - /*-----------------------------------*/ - /* ASYNC HDLC specific parameter RAM */ - /*-----------------------------------*/ - - cyg_uint8 RESERVED2[4]; /* Reserved area */ - cyg_uint32 c_mask; /* CRC constant */ - cyg_uint32 c_pres; /* CRC preset */ - cyg_uint16 bof; /* begining of flag character */ - cyg_uint16 eof; /* end of flag character */ - cyg_uint16 esc; /* control escape character */ - cyg_uint8 RESERVED3[4]; /* Reserved area */ - cyg_uint16 zero; /* zero */ - cyg_uint8 RESERVED4[2]; /* Reserved area */ - cyg_uint16 rfthr; /* received frames threshold */ - cyg_uint8 RESERVED5[4]; /* Reserved area */ - cyg_uint32 txctl_tbl; /* Tx ctl char mapping table */ - cyg_uint32 rxctl_tbl; /* Rx ctl char mapping table */ - cyg_uint16 nof; /* Number of opening flags */ -}; - - -/*--------------------------------------------------------------------------*/ -/* UART parameter RAM (SCC) */ -/*--------------------------------------------------------------------------*/ - -/*----------------------------------------*/ -/* bits in uart control characters table */ -/*----------------------------------------*/ - -#define CC_INVALID 0x8000 /* control character is valid */ -#define CC_REJ 0x4000 /* don't store char in buffer */ -#define CC_CHAR 0x00ff /* control character */ - -/*------*/ -/* UART */ -/*------*/ - -struct uart_pram - -{ - /*-------------------*/ - /* SCC parameter RAM */ - /*-------------------*/ - - cyg_uint16 rbase; /* RX BD base address */ - cyg_uint16 tbase; /* TX BD base address */ - cyg_uint8 rfcr; /* Rx function code */ - cyg_uint8 tfcr; /* Tx function code */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rx_temp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - cyg_uint32 rcrc; /* temp receive CRC */ - cyg_uint32 tcrc; /* temp transmit CRC */ - - /*------------------------------*/ - /* UART specific parameter RAM */ - /*------------------------------*/ - - cyg_uint8 RESERVED6[8]; /* Reserved area */ - cyg_uint16 max_idl; /* maximum idle characters */ - cyg_uint16 idlc; /* rx idle counter (internal) */ - cyg_uint16 brkcr; /* break count register */ - - cyg_uint16 parec; /* Rx parity error counter */ - cyg_uint16 frmec; /* Rx framing error counter */ - cyg_uint16 nosec; /* Rx noise counter */ - cyg_uint16 brkec; /* Rx break character counter */ - cyg_uint16 brkln; /* Reaceive break length */ - - cyg_uint16 uaddr1; /* address character 1 */ - cyg_uint16 uaddr2; /* address character 2 */ - cyg_uint16 rtemp; /* temp storage */ - cyg_uint16 toseq; /* Tx out of sequence char */ - cyg_uint16 cc[8]; /* Rx control characters */ - cyg_uint16 rccm; /* Rx control char mask */ - cyg_uint16 rccr; /* Rx control char register */ - cyg_uint16 rlbc; /* Receive last break char */ -}; - - -/*--------------------------------------------------------------------------- -* BISYNC parameter RAM (SCC) -*--------------------------------------------------------------------------*/ - -struct bisync_pram - -{ - /*-------------------*/ - /* SCC parameter RAM */ - /*-------------------*/ - - cyg_uint16 rbase; /* RX BD base address */ - cyg_uint16 tbase; /* TX BD base address */ - cyg_uint8 rfcr; /* Rx function code */ - cyg_uint8 tfcr; /* Tx function code */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rtemp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - cyg_uint32 rcrc; /* temp receive CRC */ - cyg_uint32 tcrc; /* temp transmit CRC */ - - /*--------------------------------*/ - /* BISYNC specific parameter RAM */ - /*--------------------------------*/ - - cyg_uint8 RESERVED7[4]; /* Reserved area */ - cyg_uint32 crcc; /* CRC Constant Temp Value */ - cyg_uint16 prcrc; /* Preset Receiver CRC-16/LRC */ - cyg_uint16 ptcrc; /* Preset Transmitter CRC-16/LRC */ - cyg_uint16 parec; /* Receive Parity Error Counter */ - cyg_uint16 bsync; /* BISYNC SYNC Character */ - cyg_uint16 bdle; /* BISYNC DLE Character */ - cyg_uint16 cc[8]; /* Rx control characters */ - cyg_uint16 rccm; /* Receive Control Character Mask */ -}; - - -/*-------------------------------------------------------------------------*/ -/* Transparent mode parameter RAM (SCC) */ -/*-------------------------------------------------------------------------*/ - -struct transparent_pram - -{ - /*--------------------*/ - /* SCC parameter RAM */ - /*--------------------*/ - - cyg_uint16 rbase; /* RX BD base address */ - cyg_uint16 tbase; /* TX BD base address */ - cyg_uint8 rfcr; /* Rx function code */ - cyg_uint8 tfcr; /* Tx function code */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rtemp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - cyg_uint32 rcrc; /* temp receive CRC */ - cyg_uint32 tcrc; /* temp transmit CRC */ - - /*-------------------------------------*/ - /* TRANSPARENT specific parameter RAM */ - /*-------------------------------------*/ - - cyg_uint32 crc_p; /* CRC Preset */ - cyg_uint32 crc_c; /* CRC constant */ -}; - - -/*-------------------------------------------------------------------------*/ -/* Ethernet parameter RAM (SCC) */ -/*-------------------------------------------------------------------------*/ - -struct ethernet_pram - -{ - /*--------------------*/ - /* SCC parameter RAM */ - /*--------------------*/ - - cyg_uint16 rbase; /* RX BD base address */ - cyg_uint16 tbase; /* TX BD base address */ - cyg_uint8 rfcr; /* Rx function code */ - cyg_uint8 tfcr; /* Tx function code */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rtemp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - cyg_uint32 rcrc; /* temp receive CRC */ - cyg_uint32 tcrc; /* temp transmit CRC */ - - /*---------------------------------*/ - /* ETHERNET specific parameter RAM */ - /*---------------------------------*/ - - cyg_uint32 c_pres; /* preset CRC */ - cyg_uint32 c_mask; /* constant mask for CRC */ - cyg_uint32 crcec; /* CRC error counter */ - cyg_uint32 alec; /* alighnment error counter */ - cyg_uint32 disfc; /* discard frame counter */ - cyg_uint16 pads; /* short frame PAD characters */ - cyg_uint16 ret_lim; /* retry limit threshold */ - cyg_uint16 ret_cnt; /* retry limit counter */ - cyg_uint16 mflr; /* maximum frame length reg */ - cyg_uint16 minflr; /* minimum frame length reg */ - cyg_uint16 maxd1; /* maximum DMA1 length reg */ - cyg_uint16 maxd2; /* maximum DMA2 length reg */ - cyg_uint16 maxd; /* rx max DMA */ - cyg_uint16 dma_cnt; /* rx dma counter */ - cyg_uint16 max_b; /* max bd byte count */ - cyg_uint16 gaddr1; /* group address filter 1 */ - cyg_uint16 gaddr2; /* group address filter 2 */ - cyg_uint16 gaddr3; /* group address filter 3 */ - cyg_uint16 gaddr4; /* group address filter 4 */ - cyg_uint32 tbuf0_data0; /* save area 0 - current frm */ - cyg_uint32 tbuf0_data1; /* save area 1 - current frm */ - cyg_uint32 tbuf0_rba0; - cyg_uint32 tbuf0_crc; - cyg_uint16 tbuf0_bcnt; - cyg_uint16 paddr_h; /* physical address (MSB) */ - cyg_uint16 paddr_m; /* physical address */ - cyg_uint16 paddr_l; /* physical address (LSB) */ - cyg_uint16 p_per; /* persistence */ - cyg_uint16 rfbd_ptr; /* rx first bd pointer */ - cyg_uint16 tfbd_ptr; /* tx first bd pointer */ - cyg_uint16 tlbd_ptr; /* tx last bd pointer */ - cyg_uint32 tbuf1_data0; /* save area 0 - next frame */ - cyg_uint32 tbuf1_data1; /* save area 1 - next frame */ - cyg_uint32 tbuf1_rba0; - cyg_uint32 tbuf1_crc; - cyg_uint16 tbuf1_bcnt; - cyg_uint16 tx_len; /* tx frame length counter */ - cyg_uint16 iaddr1; /* individual address filter 1*/ - cyg_uint16 iaddr2; /* individual address filter 2*/ - cyg_uint16 iaddr3; /* individual address filter 3*/ - cyg_uint16 iaddr4; /* individual address filter 4*/ - cyg_uint16 boff_cnt; /* back-off counter */ - cyg_uint16 taddr_h; /* temp address (MSB) */ - cyg_uint16 taddr_m; /* temp address */ - cyg_uint16 taddr_l; /* temp address (LSB) */ -}; - - -/*------------------------------------------------------------------*/ -/* QMC definitions */ -/*------------------------------------------------------------------*/ - - -struct global_qmc_pram { - - cyg_uint32 mcbase; /* Multichannel Base pointer */ - cyg_uint16 qmcstate; /* Multichannel Controller state */ - cyg_uint16 mrblr; /* Maximum Receive Buffer Length */ - cyg_uint16 tx_s_ptr; /* TSATTx Pointer */ - cyg_uint16 rxptr; /* Current Time slot entry in TSATRx */ - cyg_uint16 grfthr; /* Global Receive frame threshold */ - cyg_uint16 grfcnt; /* Global Receive Frame Count */ - cyg_uint32 intbase; /* Multichannel Base address */ - cyg_uint32 intptr; /* Pointer to interrupt queue */ - cyg_uint16 rx_s_ptr; /* TSATRx Pointer */ - cyg_uint16 txptr; /* Current Time slot entry in TSATTx */ - cyg_uint32 c_mask32; /* CRC Constant (debb20e3) */ - cyg_uint16 tsatrx[32]; /* Time Slot Assignment Table Rx */ - cyg_uint16 tsattx[32]; /* Time Slot Assignment Table Tx */ - cyg_uint16 c_mask16; /* CRC Constant (f0b8) */ - -}; - - - /*------------------------------------------*/ - /* QMC HDLC channel specific parameter RAM */ - /*------------------------------------------*/ - -struct qmc_hdlc_pram { - - cyg_uint16 tbase; /* Tx Buffer Descriptors Base Address */ - cyg_uint16 chamr; /* Channel Mode Register */ - cyg_uint32 tstate; /* Tx Internal State */ - cyg_uint32 txintr; /* Tx Internal Data Pointer */ - cyg_uint16 tbptr; /* Tx Buffer Descriptor Pointer */ - cyg_uint16 txcntr; /* Tx Internal Byte Count */ - cyg_uint32 tupack; /* (Tx Temp) */ - cyg_uint32 zistate; /* Zero Insertion machine state */ - cyg_uint32 tcrc; /* Temp Transmit CRC */ - cyg_uint16 intmsk; /* Channel's interrupt mask flags */ - cyg_uint16 bdflags; - cyg_uint16 rbase; /* Rx Buffer Descriptors Base Address */ - cyg_uint16 mflr; /* Max Frame Length Register */ - cyg_uint32 rstate; /* Rx Internal State */ - cyg_uint32 rxintr; /* Rx Internal Data Pointer */ - cyg_uint16 rbptr; /* Rx Buffer Descriptor Pointer */ - cyg_uint16 rxbyc; /* Rx Internal Byte Count */ - cyg_uint32 rpack; /* (Rx Temp) */ - cyg_uint32 zdstate; /* Zero Deletion machine state */ - cyg_uint32 rcrc; /* Temp Transmit CRC */ - cyg_uint16 maxc; /* Max_length counter */ - cyg_uint16 tmp_mb; /* Temp */ -}; - - - /*-------------------------------------------------*/ - /* QMC Transparent channel specific parameter RAM */ - /*-------------------------------------------------*/ - -struct qmc_tran_pram { - - cyg_uint16 tbase; /* Tx Bufer Descriptors Base Address */ - cyg_uint16 chamr; /* Channel Mode Register */ - cyg_uint32 tstate; /* Tx Internal State */ - cyg_uint32 txintr; /* Tx Internal Data Pointer */ - cyg_uint16 tbptr; /* Tx Buffer Descriptor Pointer */ - cyg_uint16 txcntr; /* Tx Internal Byte Count */ - cyg_uint32 tupack; /* (Tx Temp) */ - cyg_uint32 zistate; /* Zero Insertion machine state */ - cyg_uint32 RESERVED8; - cyg_uint16 intmsk; /* Channel's interrupt mask flags */ - cyg_uint16 bdflags; - cyg_uint16 rbase; /* Rx Buffer Descriptors Base Address */ - cyg_uint16 tmrblr; /* Max receive buffer length */ - cyg_uint32 rstate; /* Rx Internal State */ - cyg_uint32 rxintr; /* Rx Internal Data Pointer */ - cyg_uint16 rbptr; /* Rx Buffer Descriptor Pointer */ - cyg_uint16 rxbyc; /* Rx Internal Byte Count */ - cyg_uint32 rpack; /* (Rx Temp) */ - cyg_uint32 zdstate; /* Zero Deletion machine state */ - cyg_uint32 RESERVED9; /* Temp Transmit CRC */ - cyg_uint16 trnsync; /* Max_length counter */ - cyg_uint16 RESERVED10; /* Temp */ - -}; - -/*----------------------------------------------------------*/ -/* allows multiprotocol array declaration in the memory map */ -/*----------------------------------------------------------*/ - -struct qmc_chan_pram -{ - union - { - struct qmc_hdlc_pram h; - struct qmc_tran_pram t; - }h_or_t; -}; - - - -/*--------------------------------------------------------------------*/ -/* SMC UART parameter RAM */ -/*--------------------------------------------------------------------*/ - -struct smc_uart_pram - -{ - cyg_uint16 rbase; /* Rx BD Base Address */ - cyg_uint16 tbase; /* Tx BD Base Address */ - cyg_uint8 rfcr; /* Rx function code */ - cyg_uint8 tfcr; /* Tx function code */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rtemp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - cyg_uint16 max_idl; /* Maximum IDLE Characters */ - cyg_uint16 idlc; /* Temporary IDLE Counter */ - cyg_uint16 brkln; /* Last Rx Break Length */ - cyg_uint16 brkec; /* Rx Break Condition Counter */ - cyg_uint16 brkcr; /* Break Count Register (Tx) */ - cyg_uint16 r_mask; /* Temporary bit mask */ -}; - - -/*--------------------------------------------------------------------------*/ -/* SMC Transparent mode parameter RAM */ -/*--------------------------------------------------------------------------*/ - -struct smc_trnsp_pram - -{ - cyg_uint16 rbase; /* Rx BD Base Address */ - cyg_uint16 tbase; /* Tx BD Base Address */ - cyg_uint8 rfcr; /* Rx function code */ - cyg_uint8 tfcr; /* Tx function code */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rtemp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - cyg_uint16 RESERVED11[5]; /* Reserved */ -}; - - -/*--------------------------------------------------------------------------*/ -/* SPI parameter RAM */ -/*--------------------------------------------------------------------------*/ - -#define SPI_R 0x8000 /* Ready bit in BD */ - -struct spi_pram - -{ - cyg_uint16 rbase; /* Rx BD Base Address */ - cyg_uint16 tbase; /* Tx BD Base Address */ - cyg_uint8 rfcr; /* Rx function code */ - cyg_uint8 tfcr; /* Tx function code */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rtemp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - - cyg_uint8 RESERVED12[8]; /* Reserved */ -}; - - -/*--------------------------------------------------------------------------*/ -/* I2C parameter RAM */ -/*--------------------------------------------------------------------------*/ - -struct i2c_pram - -{ - /*--------------------*/ - /* I2C parameter RAM */ - /*--------------------*/ - - cyg_uint16 rbase; /* RX BD base address */ - cyg_uint16 tbase; /* TX BD base address */ - cyg_uint8 rfcr; /* Rx function code */ - cyg_uint8 tfcr; /* Tx function code */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rtemp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - - cyg_uint8 RESERVED13[8]; -}; - -/*--------------------------------------------------------------------------*/ -/* MISC parameter RAM */ -/*--------------------------------------------------------------------------*/ - -struct misc_pram -{ - cyg_uint8 RESERVED14[16]; -}; - - - -/*--------------------------------------------------------------------------*/ -/* PIP Centronics parameter RAM */ -/*--------------------------------------------------------------------------*/ - -struct centronics_pram - -{ - cyg_uint16 rbase; /* Rx BD Base Address */ - cyg_uint16 tbase; /* Tx BD Base Address */ - cyg_uint8 fcr; /* function code */ - cyg_uint8 smask; /* Status Mask */ - cyg_uint16 mrblr; /* Rx buffer length */ - cyg_uint32 rstate; /* Rx internal state */ - cyg_uint32 rptr; /* Rx internal data pointer */ - cyg_uint16 rbptr; /* rb BD Pointer */ - cyg_uint16 rcount; /* Rx internal byte count */ - cyg_uint32 rtemp; /* Rx temp */ - cyg_uint32 tstate; /* Tx internal state */ - cyg_uint32 tptr; /* Tx internal data pointer */ - cyg_uint16 tbptr; /* Tx BD pointer */ - cyg_uint16 tcount; /* Tx byte count */ - cyg_uint32 ttemp; /* Tx temp */ - cyg_uint16 max_sl; /* Maximum Silence period */ - cyg_uint16 sl_cnt; /* Silence Counter */ - cyg_uint16 char1; /* CONTROL char 1 */ - cyg_uint16 char2; /* CONTROL char 2 */ - cyg_uint16 char3; /* CONTROL char 3 */ - cyg_uint16 char4; /* CONTROL char 4 */ - cyg_uint16 char5; /* CONTROL char 5 */ - cyg_uint16 char6; /* CONTROL char 6 */ - cyg_uint16 char7; /* CONTROL char 7 */ - cyg_uint16 char8; /* CONTROL char 8 */ - cyg_uint16 rccm; /* Rx Control Char Mask */ - cyg_uint16 rccr; /* Rx Char Control Register */ -}; - - -/*--------------------------------------------------------------------------*/ -/* IDMA parameter RAM */ -/*--------------------------------------------------------------------------*/ - -struct idma_pram - -{ - cyg_uint16 ibase; /* IDMA BD Base Address */ - cyg_uint16 dcmr; /* DMA Channel Mode Register */ - cyg_uint32 sapr; /* Source Internal Data Pointer */ - cyg_uint32 dapr; /* Destination Internal Data Pointer */ - cyg_uint16 ibptr; /* Buffer Descriptor Pointer */ - cyg_uint16 write_sp; /* No description given in manual */ - cyg_uint32 s_byte_c; /* Internal Source Byte Count */ - cyg_uint32 d_byte_c; /* Internal Destination Byte Count */ - cyg_uint32 s_state; /* Internal State */ - cyg_uint32 itemp0; /* Temp Data Storage */ - cyg_uint32 itemp1; /* Temp Data Storage */ - cyg_uint32 itemp2; /* Temp Data Storage */ - cyg_uint32 itemp3; /* Temp Data Storage */ - cyg_uint32 sr_mem; /* Data Storage for Peripherial Write */ - cyg_uint16 read_sp; /* No description given in manual */ - cyg_uint16 nodesc0; /* Diff Between Source and Destination Residue*/ - cyg_uint16 nodesc1; /* Temp Storage Address Pointer */ - cyg_uint16 nodesc2; /* SR_MEM Byte Count */ - cyg_uint32 d_state; /* Internal State */ -}; - - - -/*--------------------------------------------------------------------------*/ -/* RISC timer parameter RAM */ -/*--------------------------------------------------------------------------*/ - -struct timer_pram - -{ - /*----------------------------*/ - /* RISC timers parameter RAM */ - /*----------------------------*/ - - cyg_uint16 tm_base; /* RISC timer table base adr */ - cyg_uint16 tm_ptr; /* RISC timer table pointer */ - cyg_uint16 r_tmr; /* RISC timer mode register */ - cyg_uint16 r_tmv; /* RISC timer valid register */ - cyg_uint32 tm_cmd; /* RISC timer cmd register */ - cyg_uint32 tm_cnt; /* RISC timer internal cnt */ -}; - - -/*--------------------------------------------------------------------------*/ -/* ROM Microcode parameter RAM */ -/*--------------------------------------------------------------------------*/ - -struct ucode_pram - -{ - /*---------------------------*/ - /* RISC ucode parameter RAM */ - /*---------------------------*/ - - cyg_uint16 rev_num; /* Ucode Revision Number */ - cyg_uint16 d_ptr; /* MISC Dump area pointer */ - cyg_uint32 temp1; /* MISC Temp1 */ - cyg_uint32 temp2; /* MISC Temp2 */ -}; - - -/*---------------------------------------------------------------------------*/ -/* Example structuring of user data area of memory at 0x2000 (base of DPRAM) */ -/* Note that this area can also be used by microcodes and the QMC channel */ -/* specific parameter ram. */ -/*---------------------------------------------------------------------------*/ - -struct user_data - -{ - - volatile cyg_uint8 udata_bd_ucode[0x200]; /* user data bd's or Ucode (small) */ - volatile cyg_uint8 udata_bd_ucode2[0x200]; /* user data bd's or Ucode (medium) */ - volatile cyg_uint8 udata_bd_ucode3[0x400]; /* user data bd's or Ucode (large) */ - volatile cyg_uint8 udata_bd[0x700]; /* user data bd's*/ - volatile cyg_uint8 ucode_ext[0x100]; /* Ucode Extension ram*/ - volatile cyg_uint8 RESERVED12[0x0c00]; /* Reserved area */ - -}; - - - -/***************************************************************************/ -/* */ -/* Definitions of Embedded PowerPC (EPPC) internal memory structures, */ -/* including registers and dual-port RAM */ -/* */ -/***************************************************************************/ - -typedef struct eppc - -{ - /*-----------------------------------*/ - /* BASE + 0x0000: INTERNAL REGISTERS */ - /*-----------------------------------*/ - - /*-----*/ - /* SIU */ - /*-----*/ - - volatile cyg_uint32 siu_mcr; /* module configuration reg */ - volatile cyg_uint32 siu_sypcr; /* System protection cnt */ - cyg_uint8 RESERVED13[0x6]; - volatile cyg_uint16 siu_swsr; /* sw service */ - volatile cyg_uint32 siu_sipend; /* Interrupt pend reg */ - volatile cyg_uint32 siu_simask; /* Interrupt mask reg */ - volatile cyg_uint32 siu_siel; /* Interrupt edge level mask reg */ - volatile cyg_uint32 siu_sivec; /* Interrupt vector */ - volatile cyg_uint32 siu_tesr; /* Transfer error status */ - volatile cyg_uint8 RESERVED14[0xc]; /* Reserved area */ - volatile cyg_uint32 dma_sdcr; /* SDMA configuration reg */ - cyg_uint8 RESERVED15[0x4c]; - - /*--------*/ - /* PCMCIA */ - /*--------*/ - - volatile cyg_uint32 pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */ - volatile cyg_uint32 pcmcia_por0; /* PCMCIA Option Reg: Window 0 */ - volatile cyg_uint32 pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */ - volatile cyg_uint32 pcmcia_por1; /* PCMCIA Option Reg: Window 1 */ - volatile cyg_uint32 pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */ - volatile cyg_uint32 pcmcia_por2; /* PCMCIA Option Reg: Window 2 */ - volatile cyg_uint32 pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */ - volatile cyg_uint32 pcmcia_por3; /* PCMCIA Option Reg: Window 3 */ - volatile cyg_uint32 pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */ - volatile cyg_uint32 pcmcia_por4; /* PCMCIA Option Reg: Window 4 */ - volatile cyg_uint32 pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */ - volatile cyg_uint32 pcmcia_por5; /* PCMCIA Option Reg: Window 5 */ - volatile cyg_uint32 pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */ - volatile cyg_uint32 pcmcia_por6; /* PCMCIA Option Reg: Window 6 */ - volatile cyg_uint32 pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */ - volatile cyg_uint32 pcmcia_por7; /* PCMCIA Option Reg: Window 7 */ - volatile cyg_uint8 RESERVED16[0x20]; /* Reserved area */ - volatile cyg_uint32 pcmcia_pgcra; /* PCMCIA Slot A Control Reg */ - volatile cyg_uint32 pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */ - volatile cyg_uint32 pcmcia_pscr; /* PCMCIA Status Reg */ - volatile cyg_uint8 RESERVED17[0x4]; /* Reserved area */ - volatile cyg_uint32 pcmcia_pipr; /* PCMCIA Pins Value Reg */ - volatile cyg_uint8 RESERVED18[0x4]; /* Reserved area */ - volatile cyg_uint32 pcmcia_per; /* PCMCIA Enable Reg */ - volatile cyg_uint8 RESERVED19[0x4]; /* Reserved area */ - - /*------*/ - /* MEMC */ - /*------*/ - - volatile cyg_uint32 memc_br0; /* base register 0 */ - volatile cyg_uint32 memc_or0; /* option register 0 */ - volatile cyg_uint32 memc_br1; /* base register 1 */ - volatile cyg_uint32 memc_or1; /* option register 1 */ - volatile cyg_uint32 memc_br2; /* base register 2 */ - volatile cyg_uint32 memc_or2; /* option register 2 */ - volatile cyg_uint32 memc_br3; /* base register 3 */ - volatile cyg_uint32 memc_or3; /* option register 3 */ - volatile cyg_uint32 memc_br4; /* base register 3 */ - volatile cyg_uint32 memc_or4; /* option register 3 */ - volatile cyg_uint32 memc_br5; /* base register 3 */ - volatile cyg_uint32 memc_or5; /* option register 3 */ - volatile cyg_uint32 memc_br6; /* base register 3 */ - volatile cyg_uint32 memc_or6; /* option register 3 */ - volatile cyg_uint32 memc_br7; /* base register 3 */ - volatile cyg_uint32 memc_or7; /* option register 3 */ - volatile cyg_uint8 RESERVED20[0x24]; /* Reserved area */ - volatile cyg_uint32 memc_mar; /* Memory address */ - volatile cyg_uint32 memc_mcr; /* Memory command */ - volatile cyg_uint8 RESERVED21[0x4]; /* Reserved area */ - volatile cyg_uint32 memc_mamr; /* Machine A mode */ - volatile cyg_uint32 memc_mbmr; /* Machine B mode */ - volatile cyg_uint16 memc_mstat; /* Memory status */ - volatile cyg_uint16 memc_mptpr; /* Memory preidic timer prescalar */ - volatile cyg_uint32 memc_mdr; /* Memory data */ - volatile cyg_uint8 RESERVED22[0x80]; /* Reserved area */ - - /*---------------------------*/ - /* SYSTEM INTEGRATION TIMERS */ - /*---------------------------*/ - - volatile cyg_uint16 simt_tbscr; /* Time base stat&ctr */ - volatile cyg_uint8 RESERVED23[0x2]; /* Reserved area */ - volatile cyg_uint32 simt_tbreff0; /* Time base reference 0 */ - volatile cyg_uint32 simt_tbreff1; /* Time base reference 1 */ - volatile cyg_uint8 RESERVED24[0x14]; /* Reserved area */ - volatile cyg_uint16 simt_rtcsc; /* Realtime clk stat&cntr 1 */ - volatile cyg_uint8 RESERVED25[0x2]; /* Reserved area */ - volatile cyg_uint32 simt_rtc; /* Realtime clock */ - volatile cyg_uint32 simt_rtsec; /* Realtime alarm seconds */ - volatile cyg_uint32 simt_rtcal; /* Realtime alarm */ - volatile cyg_uint8 RESERVED26[0x10]; /* Reserved area */ - volatile cyg_uint32 simt_piscr; /* PIT stat&ctrl */ - volatile cyg_uint32 simt_pitc; /* PIT counter */ - volatile cyg_uint32 simt_pitr; /* PIT */ - volatile cyg_uint8 RESERVED27[0x34]; /* Reserved area */ - - /*---------------*/ - /* CLOCKS, RESET */ - /*---------------*/ - - volatile cyg_uint32 clkr_sccr; /* System clk cntrl */ - volatile cyg_uint32 clkr_plprcr; /* PLL reset&ctrl */ - volatile cyg_uint32 clkr_rsr; /* reset status */ - cyg_uint8 RESERVED28[0x74]; /* Reserved area */ - - /*--------------------------------*/ - /* System Integration Timers Keys */ - /*--------------------------------*/ - - volatile cyg_uint32 simt_tbscrk; /* Timebase Status&Ctrl Key */ - volatile cyg_uint32 simt_tbreff0k; /* Timebase Reference 0 Key */ - volatile cyg_uint32 simt_tbreff1k; /* Timebase Reference 1 Key */ - volatile cyg_uint32 simt_tbk; /* Timebase and Decrementer Key */ - cyg_uint8 RESERVED29[0x10]; /* Reserved area */ - volatile cyg_uint32 simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */ - - volatile cyg_uint32 simt_rtck; /* Real-Time Clock Key */ - volatile cyg_uint32 simt_rtseck; /* Real-Time Alarm Seconds Key */ - volatile cyg_uint32 simt_rtcalk; /* Real-Time Alarm Key */ - cyg_uint8 RESERVED30[0x10]; /* Reserved area */ - volatile cyg_uint32 simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */ - volatile cyg_uint32 simt_pitck; /* Periodic Interrupt Count Key */ - cyg_uint8 RESERVED31[0x38]; /* Reserved area */ - - /*----------------------*/ - /* Clock and Reset Keys */ - /*----------------------*/ - - volatile cyg_uint32 clkr_sccrk; /* System Clock Control Key */ - volatile cyg_uint32 clkr_plprcrk; /* PLL, Low Power and Reset Control Key */ - volatile cyg_uint32 clkr_rsrk; /* Reset Status Key */ - cyg_uint8 RESERVED32[0x4d4]; /* Reserved area */ - - /*-----*/ - /* I2C */ - /*-----*/ - - volatile cyg_uint8 i2c_i2mod; /* i2c mode */ - cyg_uint8 RESERVED33[3]; - volatile cyg_uint8 i2c_i2add; /* i2c address */ - cyg_uint8 RESERVED34[3]; - volatile cyg_uint8 i2c_i2brg; /* i2c brg */ - cyg_uint8 RESERVED35[3]; - volatile cyg_uint8 i2c_i2com; /* i2c command */ - cyg_uint8 RESERVED36[3]; - volatile cyg_uint8 i2c_i2cer; /* i2c event */ - cyg_uint8 RESERVED37[3]; - volatile cyg_uint8 i2c_i2cmr; /* i2c mask */ - volatile cyg_uint8 RESERVED38[0x8b]; /* Reserved area */ - - /*-----*/ - /* DMA */ - /*-----*/ - - volatile cyg_uint8 RESERVED39[0x4]; /* Reserved area */ - volatile cyg_uint32 dma_sdar; /* SDMA address reg */ - volatile cyg_uint8 RESERVED40[0x2]; /* Reserved area */ - volatile cyg_uint8 dma_sdsr; /* SDMA status reg */ - volatile cyg_uint8 RESERVED41[0x3]; /* Reserved area */ - volatile cyg_uint8 dma_sdmr; /* SDMA mask reg */ - volatile cyg_uint8 RESERVED42[0x1]; /* Reserved area */ - volatile cyg_uint8 dma_idsr1; /* IDMA1 status reg */ - volatile cyg_uint8 RESERVED43[0x3]; /* Reserved area */ - volatile cyg_uint8 dma_idmr1; /* IDMA1 mask reg */ - volatile cyg_uint8 RESERVED44[0x3]; /* Reserved area */ - volatile cyg_uint8 dma_idsr2; /* IDMA2 status reg */ - volatile cyg_uint8 RESERVED45[0x3]; /* Reserved area */ - volatile cyg_uint8 dma_idmr2; /* IDMA2 mask reg */ - volatile cyg_uint8 RESERVED46[0x13]; /* Reserved area */ - - /*--------------------------*/ - /* CPM Interrupt Controller */ - /*--------------------------*/ - - volatile cyg_uint16 cpmi_civr; /* CP interrupt vector reg */ - volatile cyg_uint8 RESERVED47[0xe]; /* Reserved area */ - volatile cyg_uint32 cpmi_cicr; /* CP interrupt configuration reg */ - volatile cyg_uint32 cpmi_cipr; /* CP interrupt pending reg */ - volatile cyg_uint32 cpmi_cimr; /* CP interrupt mask reg */ - volatile cyg_uint32 cpmi_cisr; /* CP interrupt in-service reg */ - - /*----------*/ - /* I/O port */ - /*----------*/ - - volatile cyg_uint16 pio_padir; /* port A data direction reg */ - volatile cyg_uint16 pio_papar; /* port A pin assignment reg */ - volatile cyg_uint16 pio_paodr; /* port A open drain reg */ - volatile cyg_uint16 pio_padat; /* port A data register */ - volatile cyg_uint8 RESERVED48[0x8]; /* Reserved area */ - volatile cyg_uint16 pio_pcdir; /* port C data direction reg */ - volatile cyg_uint16 pio_pcpar; /* port C pin assignment reg */ - volatile cyg_uint16 pio_pcso; /* port C special options */ - volatile cyg_uint16 pio_pcdat; /* port C data register */ - volatile cyg_uint16 pio_pcint; /* port C interrupt cntrl reg */ - cyg_uint8 RESERVED49[6]; - volatile cyg_uint16 pio_pddir; /* port D Data Direction reg */ - volatile cyg_uint16 pio_pdpar; /* port D pin assignment reg */ - cyg_uint8 RESERVED50[2]; - volatile cyg_uint16 pio_pddat; /* port D data reg */ - volatile cyg_uint8 RESERVED51[0x8]; /* Reserved area */ - - /*-----------*/ - /* CPM Timer */ - /*-----------*/ - - volatile cyg_uint16 timer_tgcr; /* timer global configuration reg */ - volatile cyg_uint8 RESERVED52[0xe]; /* Reserved area */ - volatile cyg_uint16 timer_tmr1; /* timer 1 mode reg */ - volatile cyg_uint16 timer_tmr2; /* timer 2 mode reg */ - volatile cyg_uint16 timer_trr1; /* timer 1 referance reg */ - volatile cyg_uint16 timer_trr2; /* timer 2 referance reg */ - volatile cyg_uint16 timer_tcr1; /* timer 1 capture reg */ - volatile cyg_uint16 timer_tcr2; /* timer 2 capture reg */ - volatile cyg_uint16 timer_tcn1; /* timer 1 counter reg */ - volatile cyg_uint16 timer_tcn2; /* timer 2 counter reg */ - volatile cyg_uint16 timer_tmr3; /* timer 3 mode reg */ - volatile cyg_uint16 timer_tmr4; /* timer 4 mode reg */ - volatile cyg_uint16 timer_trr3; /* timer 3 referance reg */ - volatile cyg_uint16 timer_trr4; /* timer 4 referance reg */ - volatile cyg_uint16 timer_tcr3; /* timer 3 capture reg */ - volatile cyg_uint16 timer_tcr4; /* timer 4 capture reg */ - volatile cyg_uint16 timer_tcn3; /* timer 3 counter reg */ - volatile cyg_uint16 timer_tcn4; /* timer 4 counter reg */ - volatile cyg_uint16 timer_ter1; /* timer 1 event reg */ - volatile cyg_uint16 timer_ter2; /* timer 2 event reg */ - volatile cyg_uint16 timer_ter3; /* timer 3 event reg */ - volatile cyg_uint16 timer_ter4; /* timer 4 event reg */ - volatile cyg_uint8 RESERVED53[0x8]; /* Reserved area */ - - /*----*/ - /* CP */ - /*----*/ - - volatile cyg_uint16 cp_cr; /* command register */ - volatile cyg_uint8 RESERVED54[0x2]; /* Reserved area */ - volatile cyg_uint16 cp_rccr; /* main configuration reg */ - volatile cyg_uint8 RESERVED55; /* Reserved area */ - volatile cyg_uint8 cp_resv1; /* Reserved reg */ - volatile cyg_uint32 cp_resv2; /* Reserved reg */ - volatile cyg_uint16 cp_rctr1; /* ram break register 1 */ - volatile cyg_uint16 cp_rctr2; /* ram break register 2 */ - volatile cyg_uint16 cp_rctr3; /* ram break register 3 */ - volatile cyg_uint16 cp_rctr4; /* ram break register 4 */ - volatile cyg_uint8 RESERVED56[0x2]; /* Reserved area */ - volatile cyg_uint16 cp_rter; /* RISC timers event reg */ - volatile cyg_uint8 RESERVED57[0x2]; /* Reserved area */ - volatile cyg_uint16 cp_rtmr; /* RISC timers mask reg */ - volatile cyg_uint8 RESERVED58[0x14]; /* Reserved area */ - - /*-----*/ - /* BRG */ - /*-----*/ - - volatile cyg_uint32 brgc1; /* BRG1 configuration reg */ - volatile cyg_uint32 brgc2; /* BRG2 configuration reg */ - volatile cyg_uint32 brgc3; /* BRG3 configuration reg */ - volatile cyg_uint32 brgc4; /* BRG4 configuration reg */ - - /*---------------*/ - /* SCC registers */ - /*---------------*/ - - struct scc_regs - - { - volatile cyg_uint32 scc_gsmr_l; /* SCC Gen mode (LOW) */ - volatile cyg_uint32 scc_gsmr_h; /* SCC Gen mode (HIGH) */ - volatile cyg_uint16 scc_psmr; /* protocol specific mode register */ - volatile cyg_uint8 RESERVED59[0x2]; /* Reserved area */ - volatile cyg_uint16 scc_todr; /* SCC transmit on demand */ - volatile cyg_uint16 scc_dsr; /* SCC data sync reg */ - volatile cyg_uint16 scc_scce; /* SCC event reg */ - volatile cyg_uint8 RESERVED60[0x2]; /* Reserved area */ - volatile cyg_uint16 scc_sccm; /* SCC mask reg */ - volatile cyg_uint8 RESERVED61[0x1]; /* Reserved area */ - volatile cyg_uint8 scc_sccs; /* SCC status reg */ - volatile cyg_uint8 RESERVED62[0x8]; /* Reserved area */ - - } scc_regs[4]; - - - /*-----*/ - /* SMC */ - /*-----*/ - - struct smc_regs - - { - volatile cyg_uint8 RESERVED63[0x2]; /* Reserved area */ - volatile cyg_uint16 smc_smcmr; /* SMC mode reg */ - volatile cyg_uint8 RESERVED64[0x2]; /* Reserved area */ - volatile cyg_uint8 smc_smce; /* SMC event reg */ - volatile cyg_uint8 RESERVED65[0x3]; /* Reserved area */ - volatile cyg_uint8 smc_smcm; /* SMC mask reg */ - volatile cyg_uint8 RESERVED66[0x5]; /* Reserved area */ - - } smc_regs[2]; - - - /*-----*/ - /* SPI */ - /*-----*/ - - volatile cyg_uint16 spi_spmode; /* SPI mode reg */ - volatile cyg_uint8 RESERVED67[0x4]; /* Reserved area */ - volatile cyg_uint8 spi_spie; /* SPI event reg */ - volatile cyg_uint8 RESERVED68[0x3]; /* Reserved area */ - volatile cyg_uint8 spi_spim; /* SPI mask reg */ - volatile cyg_uint8 RESERVED69[0x2]; /* Reserved area */ - volatile cyg_uint8 spi_spcom; /* SPI command reg */ - volatile cyg_uint8 RESERVED70[0x4]; /* Reserved area */ - - /*-----*/ - /* PIP */ - /*-----*/ - - volatile cyg_uint16 pip_pipc; /* pip configuration reg */ - volatile cyg_uint8 RESERVED71[0x2]; /* Reserved area */ - volatile cyg_uint16 pip_ptpr; /* pip timing parameters reg */ - volatile cyg_uint32 pip_pbdir; /* port b data direction reg */ - volatile cyg_uint32 pip_pbpar; /* port b pin assignment reg */ - volatile cyg_uint8 RESERVED72[0x2]; /* Reserved area */ - volatile cyg_uint16 pip_pbodr; /* port b open drain reg */ - volatile cyg_uint32 pip_pbdat; /* port b data reg */ - volatile cyg_uint8 RESERVED73[0x18]; /* Reserved area */ - - - /*------------------*/ - /* Serial Interface */ - /*------------------*/ - - volatile cyg_uint32 si_simode; /* SI mode register */ - volatile cyg_uint8 si_sigmr; /* SI global mode register */ - volatile cyg_uint8 RESERVED74; /* Reserved area */ - volatile cyg_uint8 si_sistr; /* SI status register */ - volatile cyg_uint8 si_sicmr; /* SI command register */ - volatile cyg_uint8 RESERVED75[0x4]; /* Reserved area */ - volatile cyg_uint32 si_sicr; /* SI clock routing */ - volatile cyg_uint32 si_sirp; /* SI ram pointers */ - volatile cyg_uint8 RESERVED76[0x10c]; /* Reserved area */ - volatile cyg_uint8 si_siram[0x200]; /* SI routing ram */ - volatile cyg_uint8 RESERVED77[0x1200]; /* Reserved area */ - - /*-----------------------------------------------------------------*/ - /* BASE + 0x2000: user data memory, microcode, or QMC channel PRAM */ - /*-----------------------------------------------------------------*/ - - union - { - struct qmc_chan_pram qcp[64]; - struct user_data ud; - cyg_uint8 RESERVED[0x1c00]; - } qcp_or_ud; - - - /*-----------------------------------------------------------------------*/ - /* BASE + 0x3c00: PARAMETER RAM. This main union defines 4 memory blocks */ - /* of an identical size. See the Parameter RAM definition in the MPC860 */ - /* user's manual. */ - /*-----------------------------------------------------------------------*/ - - /*------------------------*/ - /* Base + 0x3C00 (page 1) */ - /* + 0x3D00 (page 2) */ - /* + 0x3E00 (page 3) */ - /* + 0x3F00 (page 4) */ - /*------------------------*/ - - union - - { - struct page_of_pram - - { - /*------------------------------------------------------------*/ - /* scc parameter area - 1st memory block (protocol dependent) */ - /*------------------------------------------------------------*/ - - union - - { - struct hdlc_pram h; - struct uart_pram u; - struct bisync_pram b; - struct transparent_pram t; - struct async_hdlc_pram a; - cyg_uint8 RESERVED78[0x80]; - - } scc; - - /*----------------------------------------------------------------*/ - /* Other protocol areas for the rest of the memory blocks in each */ - /* page. */ - /*----------------------------------------------------------------*/ - - union - - { - /*---------------------------------------------------------------*/ - /* This structure defines the rest of the blocks on the 1st page */ - /*---------------------------------------------------------------*/ - - struct - - { - struct i2c_pram i2c; /* I2C */ - struct misc_pram misc; /* MISC */ - struct idma_pram idma1; /* IDMA1 */ - - } i2c_idma; - - /*---------------------------------------------------------------*/ - /* This structure defines the rest of the blocks on the 2nd page */ - /*---------------------------------------------------------------*/ - - struct - - { - struct spi_pram spi; /* SPI */ - struct timer_pram timer; /* Timers */ - struct idma_pram idma2; /* IDMA2 */ - - } spi_timer_idma; - - /*---------------------------------------------------------------*/ - /* This structure defines the rest of the blocks on the 3rd page */ - /*---------------------------------------------------------------*/ - - struct - - { - union - - { - struct smc_uart_pram u1; /* SMC1 */ - struct smc_trnsp_pram t1; /* SMC1 */ - cyg_uint8 RESERVED78[0x80]; /* declare full block */ - - } psmc1; - - } smc_dsp1; - - - /*---------------------------------------------------------------*/ - /* This structure defines the rest of the blocks on the 4th page */ - /*---------------------------------------------------------------*/ - - struct - - { - union - - { - struct smc_uart_pram u2; /* SMC2 */ - struct smc_trnsp_pram t2; /* SMC2 */ - struct centronics_pram c; /* Uses SM2's space */ - cyg_uint8 RESERVED79[0x80]; /* declare full block */ - - } psmc2; - - } smc_dsp2; - - cyg_uint8 RESERVED80[0x80]; /* declare full block */ - - } other; - - } pg; - - /*---------------------------------------------------------------*/ - /* When selecting Ethernet as protocol for an SCC, this protocol */ - /* uses a complete page of Parameter RAM memory. */ - /*---------------------------------------------------------------*/ - - struct ethernet_pram enet_scc; - - /*---------------------------------------------------------------*/ - /* When using QMC as a mode for an SCC, the QMC global parameter */ - /* ram uses from SCC BASE to BASE+AC. */ - /*---------------------------------------------------------------*/ - - struct global_qmc_pram gqp; - - /*--------------------------------------------------------*/ - /* declaration to guarantee a page of memory is allocated */ - /*--------------------------------------------------------*/ - - cyg_uint8 RESERVED83[0x100]; - - } PRAM[4]; /* end of union */ - -} EPPC; - - -/***************************************************************************/ -/* General Global Definitions */ -/***************************************************************************/ - - -#define PAGE1 0 /* SCC1 Index into SCC Param RAM Array */ -#define PAGE2 1 /* SCC2 Index into SCC Param RAM Array */ -#define PAGE3 2 /* SCC3 Index into SCC Param RAM Array */ -#define PAGE4 3 /* SCC4 Index into SCC Param RAM Array */ - -#define SCC1_REG 0 /* SCC1 Index into SCC Regs Array */ -#define SCC2_REG 1 /* SCC2 Index into SCC Regs Array */ -#define SCC3_REG 2 /* SCC3 Index into SCC Regs Array */ -#define SCC4_REG 3 /* SCC4 Index into SCC Regs Array */ - - -/*--------------------------------*/ -/* KEEP ALIVE POWER REGISTERS KEY */ -/*--------------------------------*/ - -#define KEEP_ALIVE_KEY 0x55ccaa33 - - -#define SMC2_REG 1 /* SMC Regs Array Index for SMC2 */ - -/*-------------------------*/ -/* Single buffer component */ -/*-------------------------*/ - -typedef struct BufferPool - -{ - cyg_uint8 RxBuffer; - cyg_uint8 TxBuffer; - -} LB; - - -/*--------------------------*/ -/* Buffer Descriptor Format */ -/*--------------------------*/ - -typedef struct BufferDescriptor - -{ - cyg_uint16 bd_cstatus; /* control and status */ - cyg_uint16 bd_length; /* transfer length */ - cyg_uint8 *bd_addr; /* buffer address */ - -} BD; - - -/*-------------------------------*/ -/* Buffer Descriptor Ring format */ -/*-------------------------------*/ - -typedef struct BufferDescRings - -{ - volatile BD RxBD; /* Rx BD ring */ - volatile BD TxBD; /* Tx BD ring */ - -} BDRINGS; - - -#endif
deleted file mode 100644 --- a/packages/hal/powerpc/arch/current/src/quicc_smc.c +++ /dev/null @@ -1,446 +0,0 @@ -//============================================================================= -//####UNSUPPORTEDBEGIN#### -// -// ------------------------------------------- -// This source file has been contributed to eCos/Cygnus. It may have been -// changed slightly to provide an interface consistent with those of other -// files. -// -// The functionality and contents of this file is supplied "AS IS" -// without any form of support and will not necessarily be kept up -// to date by Cygnus. -// -// The style of programming used in this file may not comply with the -// eCos programming guidelines. Please do not use as a base for other -// files. -// -// All inquiries about this file, or the functionality provided by it, -// should be directed to the 'ecos-discuss' mailing list (see -// http://sourceware.cygnus.com/ecos/intouch.html for details). -// -// Contributed by: Kevin Hester <khester@opticworks.com> -// Maintained by: <Unmaintained> -// See also: -// Motorola's "Example Software Initializing the SMC as a UART" package -// (smc2.zip) at: -// http://www.mot.com/SPS/RISC/netcomm/tools/index.html#MPC860_table -// ------------------------------------------- -// -//####UNSUPPORTEDEND#### -//============================================================================= -/*------------------------------------------------------------------------- -* FILENAME: smc2.c -* -* DESCRIPTION: -* -* The code in this module provides echo capability on SMC2. It's -* intent is to provide the beginnings of a debug port that is -* mostly compiler independent. If an ASCII terminal is connected -* at 9600,N,8,1 on Port 2 (PB3) on the ADS board with no hardware -* control, characters typed on the keyboard will be received by -* SMC2 and echoed back out the RS232 port to the ASCII terminal. -* This function was designed and tested on an ADS860 -* development board. Note that if a different baud rate is -* required, there is a header file on the netcomm website under -* the General Software category that is labelled "Asynchronous -* Baud Rate Tables". -* -* REFERENCES: -* -* 1) MPC860 Users Manual -* 2) PowerPC Microprocessor Family: The Programming Environments for -* 32-Bit Microprocessors -* -* HISTORY: -* -* 27 APR 98 jay initial release -* -*-------------------------------------------------------------------------*/ - -#include <cyg/hal/quicc_smc.h> -#include "ppc_860.h" - -/***********************/ -/* Global Declarations */ -/***********************/ - -static EPPC *IMMR; /* IMMR base pointer */ -static BDRINGS *RxTxBD; /* buffer descriptors base pointer */ -static LB *SMC2Buffers; /* SMC2 base pointers */ - -/*---------------------*/ -/* Function Prototypes */ -/*---------------------*/ - -//static char SMC2Poll(void); -static void InitBDs(void); -//static void EchoChar(void); -static unsigned long GetIMMR(void); - - -/*----------------------------------------------------------------------------- -* -* FUNCTION NAME: cyg_smc2_init -* -* DESCRIPTION: -* -* EXTERNAL EFFECT: -* -* PARAMETERS: None -* -* RETURNS: None -* -*---------------------------------------------------------------------------*/ - -void cyg_smc2_init(unsigned long baudRate) - -{ - unsigned long *bcsr1; - unsigned long clockRate = 20 * 1000 * 1000; // 20Mhz - unsigned long divider = clockRate / (baudRate * 16) - 1; - - /*------------------------*/ - /* Establish IMMR pointer */ - /*------------------------*/ - - IMMR = (EPPC *)(GetIMMR() & 0xFFFF0000); /* MPC8xx internal register - map */ - - /*-----------------------------------------------*/ - /* Enable RS232 interface on ADS board via BCSR1 */ - /* Get the base address of BCSR */ - /*-----------------------------------------------*/ - - bcsr1 = (unsigned long *) ((IMMR->memc_br1 & 0xffff0000) + 4); - *bcsr1 &= ~(1 << 18); // turn on RS232 port 2 - - - /*-----------------------*/ - /* Allow SMC2 TX, RX out */ - /*-----------------------*/ - - IMMR->pip_pbpar |= (0x0C00); - IMMR->pip_pbdir &= 0xF3FF; - - /*------------------------------------------------*/ - /* Set Baud Rate to 9600 for 40MHz System Clock. */ - /* Enable BRG Count. */ - /*------------------------------------------------*/ - - IMMR->brgc2 = ((divider << 1) | 0x10000); - - IMMR->si_simode &= ~(0xF0000000); /* SCM2: NMSI mode */ - IMMR->si_simode |= 0x10000000; /* SCM2: Tx/Rx Clocks are BRG2 */ - - - /*----------------------------------------*/ - /* Set RXBD table start at Dual Port +800 */ - /*----------------------------------------*/ - - IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.rbase = (unsigned short) (unsigned) &RxTxBD->RxBD; - - /*----------------------------------------*/ - /* Set TXBD table start at Dual Port +808 */ - /*----------------------------------------*/ - - IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.tbase = (unsigned short) (unsigned) &RxTxBD->TxBD; - - /*---------------------------------------*/ - /* Initialize Rx and Tx Params for SMC2: */ - /* Spin until cpcr flag is cleared */ - /*---------------------------------------*/ - - for(IMMR->cp_cr = 0x00d1; IMMR->cp_cr & 0x0001;) ; - - - /*--------------------------------------*/ - /* Set RFCR,TFCR -- Rx,Tx Function Code */ - /* Normal Operation and Motorola byte */ - /* ordering */ - /*--------------------------------------*/ - - IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.rfcr = 0x18; - IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.tfcr = 0x18; - - /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ - /* Protocol Specific Parameters */ - /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ - - /*---------------------------*/ - /* MRBLR = MAX buffer length */ - /*---------------------------*/ - - IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.mrblr = 1; - - /*------------------------------------*/ - /* MAX_IDL = Disable MAX Idle Feature */ - /*------------------------------------*/ - - IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.max_idl = 0; - - /*-------------------------------------*/ - /* BRKEC = No break condition occurred */ - /*-------------------------------------*/ - - IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.brkec = 0; - - /*---------------------------------------*/ - /* BRKCR = 1 break char sent on top XMIT */ - /*---------------------------------------*/ - - IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.brkcr = 1; - - /*--------------------*/ - /* Initialize the BDs */ - /*--------------------*/ - - InitBDs(); - - IMMR->smc_regs[SMC2_REG].smc_smce = 0xFF; /* Clear any pending events */ - - /*--------------------------------------------------*/ - /* SMC_SMCM = Mask all interrupts, use polling mode */ - /*--------------------------------------------------*/ - - IMMR->smc_regs[SMC2_REG].smc_smcm = 0; - - IMMR->cpmi_cicr = 0; /* Disable all CPM interrups */ - IMMR->cpmi_cipr = 0xFFFFFFFF; /* Clear all pending interrupt events */ - IMMR->cpmi_cimr = 0; /* Mask all event interrupts */ - - /*------------------------------------*/ - /* 8-bit mode, no parity, 1 stop-bit */ - /* UART SMC Mode */ - /* Normal operation (no loopback), */ - /* SMC Transmitter/Receiver Enabled */ - /*------------------------------------*/ - - IMMR->smc_regs[SMC2_REG].smc_smcmr = 0x4823; - -} - - - -/*----------------------------------------------------------------------------- -* -* FUNCTION NAME: InitBDs -* -* DESCRIPTION: This function initializes the Tx and Rx Buffer Descriptors. -* -* EXTERNAL EFFECT: RxTxBD -* -* PARAMETERS: None -* -* RETURNS: None -* -*---------------------------------------------------------------------------*/ - -static void InitBDs(void) - -{ - /*--------------------------------------------------------------------*/ - /* We add 64 bytes to the start of the buffer descriptors because */ - /* this code was also tested on the monitor version of SDS debugger. */ - /* The monitor program on our target uses most of the first 64 bytes */ - /* for buffer descriptors. If you are not using the SDS monitor with */ - /* Motorola's ADS development board, you can delete 64 below and */ - /* start at the beginning of this particular block of Dual Port RAM. */ - /*--------------------------------------------------------------------*/ - - /*----------------------------------*/ - /* Get pointer to BD area on DP RAM */ - /*----------------------------------*/ - - RxTxBD = (BDRINGS *)(IMMR->qcp_or_ud.ud.udata_bd + 64); - - /*-------------------------------------------------------------------*/ - /* Establish the buffer pool in Dual Port RAM. We do this because the*/ - /* pool size is only 2 bytes (1 for Rx and 1 for Tx) and to avoid */ - /* disabling data cache for the memory region where BufferPool would */ - /* reside. The CPM does not recognize data in buffer pools once it */ - /* been cached. It's acesses are direct through DMA to external */ - /* memory. */ - /*-------------------------------------------------------------------*/ - - SMC2Buffers = (LB *)(IMMR->qcp_or_ud.ud.udata_bd + 80); - - /*-----------------------------------*/ - /* Setup Receiver Buffer Descriptors */ - /*-----------------------------------*/ - - RxTxBD->RxBD.bd_cstatus = 0xA000; /* Enable, Last BD */ - RxTxBD->RxBD.bd_length = 1; - RxTxBD->RxBD.bd_addr = &(SMC2Buffers->RxBuffer); - - - /*--------------------------------------*/ - /* Setup Transmitter Buffer Descriptors */ - /*--------------------------------------*/ - - RxTxBD->TxBD.bd_cstatus = 0x2000; /* Buffer not yet ready; Last BD */ - RxTxBD->TxBD.bd_length = 1; - RxTxBD->TxBD.bd_addr = &(SMC2Buffers->TxBuffer); - -} /* END InitBDs */ - - -#if 0 // static unused function. -jskov 19990122 -/*----------------------------------------------------------------------------- -* -* FUNCTION NAME: EchoChar -* -* DESCRIPTION: This function facilitates the echoing of a received character. -* -* EXTERNAL EFFECT: RxTxBD -* -* PARAMETERS: None -* -* RETURNS: None -* -*---------------------------------------------------------------------------*/ - -static void EchoChar(void) - -{ - char mych; - - mych = cyg_smc2_getchar(); - cyg_smc2_putchar(mych); - -} /* end EchoChar */ -#endif - -/*----------------------------------------------------------------------------- -* -* FUNCTION NAME: cyg_smc2_putchar -* -* DESCRIPTION: Output a character to SMC2 -* -* EXTERNAL EFFECT: RxTxBD -* -* PARAMETERS: ch - input character -* -* RETURNS: None -* -*---------------------------------------------------------------------------*/ - -void cyg_smc2_putchar(char ch) - -{ - /*-----------------------------------*/ - /* Loop until transmission completed */ - /*-----------------------------------*/ - - while (RxTxBD->TxBD.bd_cstatus & 0x8000); - - /*------------*/ - /* Store data */ - /*------------*/ - - *(RxTxBD->TxBD.bd_addr) = ch; - RxTxBD->TxBD.bd_length = 1; - - /*---------------*/ - /* Set Ready bit */ - /*---------------*/ - - RxTxBD->TxBD.bd_cstatus |= 0x8000; - -} - - - -/*----------------------------------------------------------------------------- -* -* FUNCTION NAME: cyg_smc2_getchar -* -* DESCRIPTION: Get a character from SMC2 -* -* EXTERNAL EFFECT: RxTxBD -* -* PARAMETERS: NONE -* -* RETURNS: A character from SMC2 -* -*---------------------------------------------------------------------------*/ - -char cyg_smc2_getchar(void) - -{ - - char ch; /* output character from SMC2 */ - - /*--------------------*/ - /* Loop if RxBD empty */ - /*--------------------*/ - - while (RxTxBD->RxBD.bd_cstatus & 0x8000); - - /*--------------*/ - /* Receive data */ - /*--------------*/ - - ch = *(RxTxBD->RxBD.bd_addr); - - /*----------------------*/ - /* Set Buffer Empty bit */ - /*----------------------*/ - - RxTxBD->RxBD.bd_cstatus |= 0x8000; - - return ch; - -} - - -#if 0 // static unused function. -jskov 19990122 -/*----------------------------------------------------------------------------- -* -* FUNCTION NAME: SMC2Poll -* -* DESCRIPTION: Poll SMC2 RxBD and check to see if a character was received -* -* EXTERNAL EFFECT: NONE -* -* PARAMETERS: NONE -* -* RETURNS: A one if there is a character available in the receive buffer, -* else zero. -* -*---------------------------------------------------------------------------*/ - -static char SMC2Poll(void) - -{ - return (RxTxBD->RxBD.bd_cstatus & 0x8000) ? 0 : 1; - -} /* END SMC2Poll */ -#endif - - -/*----------------------------------------------------------------------------- -* -* FUNCTION NAME: GetIMMR -* -* DESCRIPTION: Returns current value in the IMMR register. -* -* EXTERNAL EFFECT: NONE -* -* PARAMETERS: NONE -* -* RETURNS: The IMMR value in r3. The compiler uses r3 as the register -* containing the return value. -* -*---------------------------------------------------------------------------*/ - -static unsigned long GetIMMR(void) - -{ - unsigned long ret; - asm volatile (" mfspr %0,638 " : "=r" (ret)); /* IMMR is spr #638 */ - - return ret; -} - - -
--- a/packages/hal/powerpc/arch/current/src/vectors.S +++ b/packages/hal/powerpc/arch/current/src/vectors.S @@ -87,12 +87,13 @@ name: #define CYG_MSR CYG_MSR_COMMON #endif #ifdef CYG_HAL_POWERPC_SIM -# When building for SIM, don't enable MMU -- it's not needed since caches +# When building for SIM, don~t enable MMU -- it~s not needed since caches # are disabled, and there is a runtime simulation overhead. #undef CYG_MSR #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR | MSR_DR)) #endif + #=========================================================================== # If the following option is enabled, we only save registers up to R12. # The PowerPC ABI defines registers 13..31 as callee saved and thus we do @@ -283,9 +284,11 @@ 1: cmplw r4,r5 # compare blt 1b # loop if not yet done 2: +#endif -#ifdef CYG_HAL_POWERPC_COPY_VECTORS - # Copy RAM exception vectors from ROM to RAM + +#ifdef CYG_HAL_POWERPC_COPY_VECTORS // only for CygMon-supported startup + # Copy RAM exception vectors from ROM (or load place) to RAM lwi r3,rom_vectors # r3 = rom start lwi r4,0 # r4 = ram start lwi r5,rom_vectors_end # r5 = rom end @@ -302,8 +305,6 @@ 1: blt 1b # loop if not yet done 2: #endif - -#endif # clear BSS .extern __bss_start @@ -353,7 +354,7 @@ 2: sync mtmsr r3 sync - + # Enable caches .extern hal_enable_caches bl hal_enable_caches @@ -367,6 +368,7 @@ 2: bl initialize_stub #endif + .extern cyg_start bl cyg_start # call cyg_start 9: @@ -939,11 +941,13 @@ hal_vsr_table: .section ".sdata","aw" #endif + .extern hal_default_decrementer_isr .extern hal_default_isr .globl hal_interrupt_handlers hal_interrupt_handlers: - .rept CYG_ISR_TABLE_SIZE + .long hal_default_decrementer_isr + .rept CYG_ISR_TABLE_SIZE-1 .long hal_default_isr .endr
--- a/packages/hal/powerpc/fads/current/ChangeLog +++ b/packages/hal/powerpc/fads/current/ChangeLog @@ -1,3 +1,15 @@ +1999-06-10 Hugo Tyson <hmt@cygnus.co.uk> + + * src/PKGconf.mak: Add quicc_smc2.c, which now lives in here; + moved from the architectural HAL. + + * src/hal_diag.c: use local quicc_smc2.c module for IO. + + * include/plf_stub.h: use local quicc_smc2.c module for IO. + + * include/quicc_smc2.h, src/quicc_smc2.c, src/ppc_860.h: new + files; renamed and reorganized from the architectural HAL. + 1999-05-20 Gary Thomas <gthomas@cygnus.co.uk> * include/pkgconf/hal_powerpc_fads.h: Move RTC setup here.
--- a/packages/hal/powerpc/fads/current/include/plf_stub.h +++ b/packages/hal/powerpc/fads/current/include/plf_stub.h @@ -55,7 +55,7 @@ //---------------------------------------------------------------------------- // Define serial stuff. All comes from the quicc_smc.c file. -#include <cyg/hal/quicc_smc.h> +#include <cyg/hal/quicc_smc2.h> #define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_smc2_init(38400) #define HAL_STUB_PLATFORM_GET_CHAR() cyg_smc2_getchar()
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/fads/current/include/quicc_smc2.h @@ -0,0 +1,38 @@ +#ifndef CYGONCE_HAL_PPC_FADS_QUICC_SMC2_H +#define CYGONCE_HAL_PPC_FADS_QUICC_SMC2_H +//============================================================================= +//####UNSUPPORTEDBEGIN#### +// +// ------------------------------------------- +// This source file has been contributed to eCos/Cygnus. It may have been +// changed slightly to provide an interface consistent with those of other +// files. +// +// The functionality and contents of this file is supplied "AS IS" +// without any form of support and will not necessarily be kept up +// to date by Cygnus. +// +// The style of programming used in this file may not comply with the +// eCos programming guidelines. Please do not use as a base for other +// files. +// +// All inquiries about this file, or the functionality provided by it, +// should be directed to the 'ecos-discuss' mailing list (see +// http://sourceware.cygnus.com/ecos/intouch.html for details). +// +// Contributed by: Kevin Hester <khester@opticworks.com> +// Maintained by: <Unmaintained> +// See also: +// Motorola's "Example Software Initializing the SMC as a UART" package +// (smc2.zip) at: +// http://www.mot.com/SPS/RISC/netcomm/tools/index.html#MPC860_table +// ------------------------------------------- +// +//####UNSUPPORTEDEND#### +//============================================================================= + +extern void cyg_smc2_init(unsigned long baudRate); +extern void cyg_smc2_putchar(char); +extern char cyg_smc2_getchar(void); + +#endif /* CYGONCE_HAL_PPC_FADS_QUICC_SMC2_H */
--- a/packages/hal/powerpc/fads/current/src/PKGconf.mak +++ b/packages/hal/powerpc/fads/current/src/PKGconf.mak @@ -53,7 +53,7 @@ PACKAGE := hal_powerpc_fads include ../../../../../pkgconf/pkgconf.mak LIBRARY := libtarget.a -COMPILE := hal_diag.c fads.S +COMPILE := hal_diag.c fads.S quicc_smc2.c OTHER_OBJS := OTHER_TARGETS := OTHER_CLEAN :=
--- a/packages/hal/powerpc/fads/current/src/hal_diag.c +++ b/packages/hal/powerpc/fads/current/src/hal_diag.c @@ -75,7 +75,7 @@ #endif #include <cyg/hal/ppc_regs.h> -#include <cyg/hal/quicc_smc.h> +#include <cyg/hal/quicc_smc2.h> //----------------------------------------------------------------------------- // Select default diag channel to use
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/fads/current/src/ppc_860.h @@ -0,0 +1,1312 @@ +#ifndef CYGONCE_HAL_PPC_FADS_PPC_860_H +#define CYGONCE_HAL_PPC_FADS_PPC_860_H + +//============================================================================= +//####UNSUPPORTEDBEGIN#### +// +// ------------------------------------------- +// This source file has been contributed to eCos/Cygnus. It may have been +// changed slightly to provide an interface consistent with those of other +// files. +// +// The functionality and contents of this file is supplied "AS IS" +// without any form of support and will not necessarily be kept up +// to date by Cygnus. +// +// The style of programming used in this file may not comply with the +// eCos programming guidelines. Please do not use as a base for other +// files. +// +// All inquiries about this file, or the functionality provided by it, +// should be directed to the 'ecos-discuss' mailing list (see +// http://sourceware.cygnus.com/ecos/intouch.html for details). +// +// Contributed by: Kevin Hester <khester@opticworks.com> +// Maintained by: <Unmaintained> +// See also: +// Motorola's "Example Software Initializing the SMC as a UART" package +// (smc2.zip) at: +// http://www.mot.com/SPS/RISC/netcomm/tools/index.html#MPC860_table +// ------------------------------------------- +// +//####UNSUPPORTEDEND#### +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +/****************************************************************************** +* +* Definitions of Parameter RAM entries for each peripheral and mode +* +******************************************************************************/ + +/*---------------------------------------------------------------------------*/ +/* HDLC parameter RAM (SCC) */ +/*---------------------------------------------------------------------------*/ + +struct hdlc_pram + +{ + + /*-------------------*/ + /* SCC parameter RAM */ + /*-------------------*/ + + cyg_uint16 rbase; /* RX BD base address */ + cyg_uint16 tbase; /* TX BD base address */ + cyg_uint8 rfcr; /* Rx function code */ + cyg_uint8 tfcr; /* Tx function code */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rtemp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + cyg_uint32 rcrc; /* temp receive CRC */ + cyg_uint32 tcrc; /* temp transmit CRC */ + + /*-----------------------------*/ + /* HDLC specific parameter RAM */ + /*-----------------------------*/ + + cyg_uint8 RESERVED1[4]; /* Reserved area */ + cyg_uint32 c_mask; /* CRC constant */ + cyg_uint32 c_pres; /* CRC preset */ + cyg_uint16 disfc; /* discarded frame counter */ + cyg_uint16 crcec; /* CRC error counter */ + cyg_uint16 abtsc; /* abort sequence counter */ + cyg_uint16 nmarc; /* nonmatching address rx cnt */ + cyg_uint16 retrc; /* frame retransmission cnt */ + cyg_uint16 mflr; /* maximum frame length reg */ + cyg_uint16 max_cnt; /* maximum length counter */ + cyg_uint16 rfthr; /* received frames threshold */ + cyg_uint16 rfcnt; /* received frames count */ + cyg_uint16 hmask; /* user defined frm addr mask */ + cyg_uint16 haddr1; /* user defined frm address 1 */ + cyg_uint16 haddr2; /* user defined frm address 2 */ + cyg_uint16 haddr3; /* user defined frm address 3 */ + cyg_uint16 haddr4; /* user defined frm address 4 */ + cyg_uint16 tmp; /* temp */ + cyg_uint16 tmp_mb; /* temp */ +}; + + +/*-------------------------------------------------------------------------*/ +/* ASYNC HDLC parameter RAM (SCC) */ +/*-------------------------------------------------------------------------*/ + +struct async_hdlc_pram + +{ + + /*-------------------*/ + /* SCC parameter RAM */ + /*-------------------*/ + + cyg_uint16 rbase; /* RX BD base address */ + cyg_uint16 tbase; /* TX BD base address */ + cyg_uint8 rfcr; /* Rx function code */ + cyg_uint8 tfcr; /* Tx function code */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rtemp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + cyg_uint32 rcrc; /* temp receive CRC */ + cyg_uint32 tcrc; /* temp transmit CRC */ + + /*-----------------------------------*/ + /* ASYNC HDLC specific parameter RAM */ + /*-----------------------------------*/ + + cyg_uint8 RESERVED2[4]; /* Reserved area */ + cyg_uint32 c_mask; /* CRC constant */ + cyg_uint32 c_pres; /* CRC preset */ + cyg_uint16 bof; /* begining of flag character */ + cyg_uint16 eof; /* end of flag character */ + cyg_uint16 esc; /* control escape character */ + cyg_uint8 RESERVED3[4]; /* Reserved area */ + cyg_uint16 zero; /* zero */ + cyg_uint8 RESERVED4[2]; /* Reserved area */ + cyg_uint16 rfthr; /* received frames threshold */ + cyg_uint8 RESERVED5[4]; /* Reserved area */ + cyg_uint32 txctl_tbl; /* Tx ctl char mapping table */ + cyg_uint32 rxctl_tbl; /* Rx ctl char mapping table */ + cyg_uint16 nof; /* Number of opening flags */ +}; + + +/*--------------------------------------------------------------------------*/ +/* UART parameter RAM (SCC) */ +/*--------------------------------------------------------------------------*/ + +/*----------------------------------------*/ +/* bits in uart control characters table */ +/*----------------------------------------*/ + +#define CC_INVALID 0x8000 /* control character is valid */ +#define CC_REJ 0x4000 /* don't store char in buffer */ +#define CC_CHAR 0x00ff /* control character */ + +/*------*/ +/* UART */ +/*------*/ + +struct uart_pram + +{ + /*-------------------*/ + /* SCC parameter RAM */ + /*-------------------*/ + + cyg_uint16 rbase; /* RX BD base address */ + cyg_uint16 tbase; /* TX BD base address */ + cyg_uint8 rfcr; /* Rx function code */ + cyg_uint8 tfcr; /* Tx function code */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rx_temp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + cyg_uint32 rcrc; /* temp receive CRC */ + cyg_uint32 tcrc; /* temp transmit CRC */ + + /*------------------------------*/ + /* UART specific parameter RAM */ + /*------------------------------*/ + + cyg_uint8 RESERVED6[8]; /* Reserved area */ + cyg_uint16 max_idl; /* maximum idle characters */ + cyg_uint16 idlc; /* rx idle counter (internal) */ + cyg_uint16 brkcr; /* break count register */ + + cyg_uint16 parec; /* Rx parity error counter */ + cyg_uint16 frmec; /* Rx framing error counter */ + cyg_uint16 nosec; /* Rx noise counter */ + cyg_uint16 brkec; /* Rx break character counter */ + cyg_uint16 brkln; /* Reaceive break length */ + + cyg_uint16 uaddr1; /* address character 1 */ + cyg_uint16 uaddr2; /* address character 2 */ + cyg_uint16 rtemp; /* temp storage */ + cyg_uint16 toseq; /* Tx out of sequence char */ + cyg_uint16 cc[8]; /* Rx control characters */ + cyg_uint16 rccm; /* Rx control char mask */ + cyg_uint16 rccr; /* Rx control char register */ + cyg_uint16 rlbc; /* Receive last break char */ +}; + + +/*--------------------------------------------------------------------------- +* BISYNC parameter RAM (SCC) +*--------------------------------------------------------------------------*/ + +struct bisync_pram + +{ + /*-------------------*/ + /* SCC parameter RAM */ + /*-------------------*/ + + cyg_uint16 rbase; /* RX BD base address */ + cyg_uint16 tbase; /* TX BD base address */ + cyg_uint8 rfcr; /* Rx function code */ + cyg_uint8 tfcr; /* Tx function code */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rtemp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + cyg_uint32 rcrc; /* temp receive CRC */ + cyg_uint32 tcrc; /* temp transmit CRC */ + + /*--------------------------------*/ + /* BISYNC specific parameter RAM */ + /*--------------------------------*/ + + cyg_uint8 RESERVED7[4]; /* Reserved area */ + cyg_uint32 crcc; /* CRC Constant Temp Value */ + cyg_uint16 prcrc; /* Preset Receiver CRC-16/LRC */ + cyg_uint16 ptcrc; /* Preset Transmitter CRC-16/LRC */ + cyg_uint16 parec; /* Receive Parity Error Counter */ + cyg_uint16 bsync; /* BISYNC SYNC Character */ + cyg_uint16 bdle; /* BISYNC DLE Character */ + cyg_uint16 cc[8]; /* Rx control characters */ + cyg_uint16 rccm; /* Receive Control Character Mask */ +}; + + +/*-------------------------------------------------------------------------*/ +/* Transparent mode parameter RAM (SCC) */ +/*-------------------------------------------------------------------------*/ + +struct transparent_pram + +{ + /*--------------------*/ + /* SCC parameter RAM */ + /*--------------------*/ + + cyg_uint16 rbase; /* RX BD base address */ + cyg_uint16 tbase; /* TX BD base address */ + cyg_uint8 rfcr; /* Rx function code */ + cyg_uint8 tfcr; /* Tx function code */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rtemp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + cyg_uint32 rcrc; /* temp receive CRC */ + cyg_uint32 tcrc; /* temp transmit CRC */ + + /*-------------------------------------*/ + /* TRANSPARENT specific parameter RAM */ + /*-------------------------------------*/ + + cyg_uint32 crc_p; /* CRC Preset */ + cyg_uint32 crc_c; /* CRC constant */ +}; + + +/*-------------------------------------------------------------------------*/ +/* Ethernet parameter RAM (SCC) */ +/*-------------------------------------------------------------------------*/ + +struct ethernet_pram + +{ + /*--------------------*/ + /* SCC parameter RAM */ + /*--------------------*/ + + cyg_uint16 rbase; /* RX BD base address */ + cyg_uint16 tbase; /* TX BD base address */ + cyg_uint8 rfcr; /* Rx function code */ + cyg_uint8 tfcr; /* Tx function code */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rtemp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + cyg_uint32 rcrc; /* temp receive CRC */ + cyg_uint32 tcrc; /* temp transmit CRC */ + + /*---------------------------------*/ + /* ETHERNET specific parameter RAM */ + /*---------------------------------*/ + + cyg_uint32 c_pres; /* preset CRC */ + cyg_uint32 c_mask; /* constant mask for CRC */ + cyg_uint32 crcec; /* CRC error counter */ + cyg_uint32 alec; /* alighnment error counter */ + cyg_uint32 disfc; /* discard frame counter */ + cyg_uint16 pads; /* short frame PAD characters */ + cyg_uint16 ret_lim; /* retry limit threshold */ + cyg_uint16 ret_cnt; /* retry limit counter */ + cyg_uint16 mflr; /* maximum frame length reg */ + cyg_uint16 minflr; /* minimum frame length reg */ + cyg_uint16 maxd1; /* maximum DMA1 length reg */ + cyg_uint16 maxd2; /* maximum DMA2 length reg */ + cyg_uint16 maxd; /* rx max DMA */ + cyg_uint16 dma_cnt; /* rx dma counter */ + cyg_uint16 max_b; /* max bd byte count */ + cyg_uint16 gaddr1; /* group address filter 1 */ + cyg_uint16 gaddr2; /* group address filter 2 */ + cyg_uint16 gaddr3; /* group address filter 3 */ + cyg_uint16 gaddr4; /* group address filter 4 */ + cyg_uint32 tbuf0_data0; /* save area 0 - current frm */ + cyg_uint32 tbuf0_data1; /* save area 1 - current frm */ + cyg_uint32 tbuf0_rba0; + cyg_uint32 tbuf0_crc; + cyg_uint16 tbuf0_bcnt; + cyg_uint16 paddr_h; /* physical address (MSB) */ + cyg_uint16 paddr_m; /* physical address */ + cyg_uint16 paddr_l; /* physical address (LSB) */ + cyg_uint16 p_per; /* persistence */ + cyg_uint16 rfbd_ptr; /* rx first bd pointer */ + cyg_uint16 tfbd_ptr; /* tx first bd pointer */ + cyg_uint16 tlbd_ptr; /* tx last bd pointer */ + cyg_uint32 tbuf1_data0; /* save area 0 - next frame */ + cyg_uint32 tbuf1_data1; /* save area 1 - next frame */ + cyg_uint32 tbuf1_rba0; + cyg_uint32 tbuf1_crc; + cyg_uint16 tbuf1_bcnt; + cyg_uint16 tx_len; /* tx frame length counter */ + cyg_uint16 iaddr1; /* individual address filter 1*/ + cyg_uint16 iaddr2; /* individual address filter 2*/ + cyg_uint16 iaddr3; /* individual address filter 3*/ + cyg_uint16 iaddr4; /* individual address filter 4*/ + cyg_uint16 boff_cnt; /* back-off counter */ + cyg_uint16 taddr_h; /* temp address (MSB) */ + cyg_uint16 taddr_m; /* temp address */ + cyg_uint16 taddr_l; /* temp address (LSB) */ +}; + + +/*------------------------------------------------------------------*/ +/* QMC definitions */ +/*------------------------------------------------------------------*/ + + +struct global_qmc_pram { + + cyg_uint32 mcbase; /* Multichannel Base pointer */ + cyg_uint16 qmcstate; /* Multichannel Controller state */ + cyg_uint16 mrblr; /* Maximum Receive Buffer Length */ + cyg_uint16 tx_s_ptr; /* TSATTx Pointer */ + cyg_uint16 rxptr; /* Current Time slot entry in TSATRx */ + cyg_uint16 grfthr; /* Global Receive frame threshold */ + cyg_uint16 grfcnt; /* Global Receive Frame Count */ + cyg_uint32 intbase; /* Multichannel Base address */ + cyg_uint32 intptr; /* Pointer to interrupt queue */ + cyg_uint16 rx_s_ptr; /* TSATRx Pointer */ + cyg_uint16 txptr; /* Current Time slot entry in TSATTx */ + cyg_uint32 c_mask32; /* CRC Constant (debb20e3) */ + cyg_uint16 tsatrx[32]; /* Time Slot Assignment Table Rx */ + cyg_uint16 tsattx[32]; /* Time Slot Assignment Table Tx */ + cyg_uint16 c_mask16; /* CRC Constant (f0b8) */ + +}; + + + /*------------------------------------------*/ + /* QMC HDLC channel specific parameter RAM */ + /*------------------------------------------*/ + +struct qmc_hdlc_pram { + + cyg_uint16 tbase; /* Tx Buffer Descriptors Base Address */ + cyg_uint16 chamr; /* Channel Mode Register */ + cyg_uint32 tstate; /* Tx Internal State */ + cyg_uint32 txintr; /* Tx Internal Data Pointer */ + cyg_uint16 tbptr; /* Tx Buffer Descriptor Pointer */ + cyg_uint16 txcntr; /* Tx Internal Byte Count */ + cyg_uint32 tupack; /* (Tx Temp) */ + cyg_uint32 zistate; /* Zero Insertion machine state */ + cyg_uint32 tcrc; /* Temp Transmit CRC */ + cyg_uint16 intmsk; /* Channel's interrupt mask flags */ + cyg_uint16 bdflags; + cyg_uint16 rbase; /* Rx Buffer Descriptors Base Address */ + cyg_uint16 mflr; /* Max Frame Length Register */ + cyg_uint32 rstate; /* Rx Internal State */ + cyg_uint32 rxintr; /* Rx Internal Data Pointer */ + cyg_uint16 rbptr; /* Rx Buffer Descriptor Pointer */ + cyg_uint16 rxbyc; /* Rx Internal Byte Count */ + cyg_uint32 rpack; /* (Rx Temp) */ + cyg_uint32 zdstate; /* Zero Deletion machine state */ + cyg_uint32 rcrc; /* Temp Transmit CRC */ + cyg_uint16 maxc; /* Max_length counter */ + cyg_uint16 tmp_mb; /* Temp */ +}; + + + /*-------------------------------------------------*/ + /* QMC Transparent channel specific parameter RAM */ + /*-------------------------------------------------*/ + +struct qmc_tran_pram { + + cyg_uint16 tbase; /* Tx Bufer Descriptors Base Address */ + cyg_uint16 chamr; /* Channel Mode Register */ + cyg_uint32 tstate; /* Tx Internal State */ + cyg_uint32 txintr; /* Tx Internal Data Pointer */ + cyg_uint16 tbptr; /* Tx Buffer Descriptor Pointer */ + cyg_uint16 txcntr; /* Tx Internal Byte Count */ + cyg_uint32 tupack; /* (Tx Temp) */ + cyg_uint32 zistate; /* Zero Insertion machine state */ + cyg_uint32 RESERVED8; + cyg_uint16 intmsk; /* Channel's interrupt mask flags */ + cyg_uint16 bdflags; + cyg_uint16 rbase; /* Rx Buffer Descriptors Base Address */ + cyg_uint16 tmrblr; /* Max receive buffer length */ + cyg_uint32 rstate; /* Rx Internal State */ + cyg_uint32 rxintr; /* Rx Internal Data Pointer */ + cyg_uint16 rbptr; /* Rx Buffer Descriptor Pointer */ + cyg_uint16 rxbyc; /* Rx Internal Byte Count */ + cyg_uint32 rpack; /* (Rx Temp) */ + cyg_uint32 zdstate; /* Zero Deletion machine state */ + cyg_uint32 RESERVED9; /* Temp Transmit CRC */ + cyg_uint16 trnsync; /* Max_length counter */ + cyg_uint16 RESERVED10; /* Temp */ + +}; + +/*----------------------------------------------------------*/ +/* allows multiprotocol array declaration in the memory map */ +/*----------------------------------------------------------*/ + +struct qmc_chan_pram +{ + union + { + struct qmc_hdlc_pram h; + struct qmc_tran_pram t; + }h_or_t; +}; + + + +/*--------------------------------------------------------------------*/ +/* SMC UART parameter RAM */ +/*--------------------------------------------------------------------*/ + +struct smc_uart_pram + +{ + cyg_uint16 rbase; /* Rx BD Base Address */ + cyg_uint16 tbase; /* Tx BD Base Address */ + cyg_uint8 rfcr; /* Rx function code */ + cyg_uint8 tfcr; /* Tx function code */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rtemp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + cyg_uint16 max_idl; /* Maximum IDLE Characters */ + cyg_uint16 idlc; /* Temporary IDLE Counter */ + cyg_uint16 brkln; /* Last Rx Break Length */ + cyg_uint16 brkec; /* Rx Break Condition Counter */ + cyg_uint16 brkcr; /* Break Count Register (Tx) */ + cyg_uint16 r_mask; /* Temporary bit mask */ +}; + + +/*--------------------------------------------------------------------------*/ +/* SMC Transparent mode parameter RAM */ +/*--------------------------------------------------------------------------*/ + +struct smc_trnsp_pram + +{ + cyg_uint16 rbase; /* Rx BD Base Address */ + cyg_uint16 tbase; /* Tx BD Base Address */ + cyg_uint8 rfcr; /* Rx function code */ + cyg_uint8 tfcr; /* Tx function code */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rtemp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + cyg_uint16 RESERVED11[5]; /* Reserved */ +}; + + +/*--------------------------------------------------------------------------*/ +/* SPI parameter RAM */ +/*--------------------------------------------------------------------------*/ + +#define SPI_R 0x8000 /* Ready bit in BD */ + +struct spi_pram + +{ + cyg_uint16 rbase; /* Rx BD Base Address */ + cyg_uint16 tbase; /* Tx BD Base Address */ + cyg_uint8 rfcr; /* Rx function code */ + cyg_uint8 tfcr; /* Tx function code */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rtemp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + + cyg_uint8 RESERVED12[8]; /* Reserved */ +}; + + +/*--------------------------------------------------------------------------*/ +/* I2C parameter RAM */ +/*--------------------------------------------------------------------------*/ + +struct i2c_pram + +{ + /*--------------------*/ + /* I2C parameter RAM */ + /*--------------------*/ + + cyg_uint16 rbase; /* RX BD base address */ + cyg_uint16 tbase; /* TX BD base address */ + cyg_uint8 rfcr; /* Rx function code */ + cyg_uint8 tfcr; /* Tx function code */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rtemp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + + cyg_uint8 RESERVED13[8]; +}; + +/*--------------------------------------------------------------------------*/ +/* MISC parameter RAM */ +/*--------------------------------------------------------------------------*/ + +struct misc_pram +{ + cyg_uint8 RESERVED14[16]; +}; + + + +/*--------------------------------------------------------------------------*/ +/* PIP Centronics parameter RAM */ +/*--------------------------------------------------------------------------*/ + +struct centronics_pram + +{ + cyg_uint16 rbase; /* Rx BD Base Address */ + cyg_uint16 tbase; /* Tx BD Base Address */ + cyg_uint8 fcr; /* function code */ + cyg_uint8 smask; /* Status Mask */ + cyg_uint16 mrblr; /* Rx buffer length */ + cyg_uint32 rstate; /* Rx internal state */ + cyg_uint32 rptr; /* Rx internal data pointer */ + cyg_uint16 rbptr; /* rb BD Pointer */ + cyg_uint16 rcount; /* Rx internal byte count */ + cyg_uint32 rtemp; /* Rx temp */ + cyg_uint32 tstate; /* Tx internal state */ + cyg_uint32 tptr; /* Tx internal data pointer */ + cyg_uint16 tbptr; /* Tx BD pointer */ + cyg_uint16 tcount; /* Tx byte count */ + cyg_uint32 ttemp; /* Tx temp */ + cyg_uint16 max_sl; /* Maximum Silence period */ + cyg_uint16 sl_cnt; /* Silence Counter */ + cyg_uint16 char1; /* CONTROL char 1 */ + cyg_uint16 char2; /* CONTROL char 2 */ + cyg_uint16 char3; /* CONTROL char 3 */ + cyg_uint16 char4; /* CONTROL char 4 */ + cyg_uint16 char5; /* CONTROL char 5 */ + cyg_uint16 char6; /* CONTROL char 6 */ + cyg_uint16 char7; /* CONTROL char 7 */ + cyg_uint16 char8; /* CONTROL char 8 */ + cyg_uint16 rccm; /* Rx Control Char Mask */ + cyg_uint16 rccr; /* Rx Char Control Register */ +}; + + +/*--------------------------------------------------------------------------*/ +/* IDMA parameter RAM */ +/*--------------------------------------------------------------------------*/ + +struct idma_pram + +{ + cyg_uint16 ibase; /* IDMA BD Base Address */ + cyg_uint16 dcmr; /* DMA Channel Mode Register */ + cyg_uint32 sapr; /* Source Internal Data Pointer */ + cyg_uint32 dapr; /* Destination Internal Data Pointer */ + cyg_uint16 ibptr; /* Buffer Descriptor Pointer */ + cyg_uint16 write_sp; /* No description given in manual */ + cyg_uint32 s_byte_c; /* Internal Source Byte Count */ + cyg_uint32 d_byte_c; /* Internal Destination Byte Count */ + cyg_uint32 s_state; /* Internal State */ + cyg_uint32 itemp0; /* Temp Data Storage */ + cyg_uint32 itemp1; /* Temp Data Storage */ + cyg_uint32 itemp2; /* Temp Data Storage */ + cyg_uint32 itemp3; /* Temp Data Storage */ + cyg_uint32 sr_mem; /* Data Storage for Peripherial Write */ + cyg_uint16 read_sp; /* No description given in manual */ + cyg_uint16 nodesc0; /* Diff Between Source and Destination Residue*/ + cyg_uint16 nodesc1; /* Temp Storage Address Pointer */ + cyg_uint16 nodesc2; /* SR_MEM Byte Count */ + cyg_uint32 d_state; /* Internal State */ +}; + + + +/*--------------------------------------------------------------------------*/ +/* RISC timer parameter RAM */ +/*--------------------------------------------------------------------------*/ + +struct timer_pram + +{ + /*----------------------------*/ + /* RISC timers parameter RAM */ + /*----------------------------*/ + + cyg_uint16 tm_base; /* RISC timer table base adr */ + cyg_uint16 tm_ptr; /* RISC timer table pointer */ + cyg_uint16 r_tmr; /* RISC timer mode register */ + cyg_uint16 r_tmv; /* RISC timer valid register */ + cyg_uint32 tm_cmd; /* RISC timer cmd register */ + cyg_uint32 tm_cnt; /* RISC timer internal cnt */ +}; + + +/*--------------------------------------------------------------------------*/ +/* ROM Microcode parameter RAM */ +/*--------------------------------------------------------------------------*/ + +struct ucode_pram + +{ + /*---------------------------*/ + /* RISC ucode parameter RAM */ + /*---------------------------*/ + + cyg_uint16 rev_num; /* Ucode Revision Number */ + cyg_uint16 d_ptr; /* MISC Dump area pointer */ + cyg_uint32 temp1; /* MISC Temp1 */ + cyg_uint32 temp2; /* MISC Temp2 */ +}; + + +/*---------------------------------------------------------------------------*/ +/* Example structuring of user data area of memory at 0x2000 (base of DPRAM) */ +/* Note that this area can also be used by microcodes and the QMC channel */ +/* specific parameter ram. */ +/*---------------------------------------------------------------------------*/ + +struct user_data + +{ + + volatile cyg_uint8 udata_bd_ucode[0x200]; /* user data bd's or Ucode (small) */ + volatile cyg_uint8 udata_bd_ucode2[0x200]; /* user data bd's or Ucode (medium) */ + volatile cyg_uint8 udata_bd_ucode3[0x400]; /* user data bd's or Ucode (large) */ + volatile cyg_uint8 udata_bd[0x700]; /* user data bd's*/ + volatile cyg_uint8 ucode_ext[0x100]; /* Ucode Extension ram*/ + volatile cyg_uint8 RESERVED12[0x0c00]; /* Reserved area */ + +}; + + + +/***************************************************************************/ +/* */ +/* Definitions of Embedded PowerPC (EPPC) internal memory structures, */ +/* including registers and dual-port RAM */ +/* */ +/***************************************************************************/ + +typedef struct eppc + +{ + /*-----------------------------------*/ + /* BASE + 0x0000: INTERNAL REGISTERS */ + /*-----------------------------------*/ + + /*-----*/ + /* SIU */ + /*-----*/ + + volatile cyg_uint32 siu_mcr; /* module configuration reg */ + volatile cyg_uint32 siu_sypcr; /* System protection cnt */ + cyg_uint8 RESERVED13[0x6]; + volatile cyg_uint16 siu_swsr; /* sw service */ + volatile cyg_uint32 siu_sipend; /* Interrupt pend reg */ + volatile cyg_uint32 siu_simask; /* Interrupt mask reg */ + volatile cyg_uint32 siu_siel; /* Interrupt edge level mask reg */ + volatile cyg_uint32 siu_sivec; /* Interrupt vector */ + volatile cyg_uint32 siu_tesr; /* Transfer error status */ + volatile cyg_uint8 RESERVED14[0xc]; /* Reserved area */ + volatile cyg_uint32 dma_sdcr; /* SDMA configuration reg */ + cyg_uint8 RESERVED15[0x4c]; + + /*--------*/ + /* PCMCIA */ + /*--------*/ + + volatile cyg_uint32 pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */ + volatile cyg_uint32 pcmcia_por0; /* PCMCIA Option Reg: Window 0 */ + volatile cyg_uint32 pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */ + volatile cyg_uint32 pcmcia_por1; /* PCMCIA Option Reg: Window 1 */ + volatile cyg_uint32 pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */ + volatile cyg_uint32 pcmcia_por2; /* PCMCIA Option Reg: Window 2 */ + volatile cyg_uint32 pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */ + volatile cyg_uint32 pcmcia_por3; /* PCMCIA Option Reg: Window 3 */ + volatile cyg_uint32 pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */ + volatile cyg_uint32 pcmcia_por4; /* PCMCIA Option Reg: Window 4 */ + volatile cyg_uint32 pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */ + volatile cyg_uint32 pcmcia_por5; /* PCMCIA Option Reg: Window 5 */ + volatile cyg_uint32 pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */ + volatile cyg_uint32 pcmcia_por6; /* PCMCIA Option Reg: Window 6 */ + volatile cyg_uint32 pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */ + volatile cyg_uint32 pcmcia_por7; /* PCMCIA Option Reg: Window 7 */ + volatile cyg_uint8 RESERVED16[0x20]; /* Reserved area */ + volatile cyg_uint32 pcmcia_pgcra; /* PCMCIA Slot A Control Reg */ + volatile cyg_uint32 pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */ + volatile cyg_uint32 pcmcia_pscr; /* PCMCIA Status Reg */ + volatile cyg_uint8 RESERVED17[0x4]; /* Reserved area */ + volatile cyg_uint32 pcmcia_pipr; /* PCMCIA Pins Value Reg */ + volatile cyg_uint8 RESERVED18[0x4]; /* Reserved area */ + volatile cyg_uint32 pcmcia_per; /* PCMCIA Enable Reg */ + volatile cyg_uint8 RESERVED19[0x4]; /* Reserved area */ + + /*------*/ + /* MEMC */ + /*------*/ + + volatile cyg_uint32 memc_br0; /* base register 0 */ + volatile cyg_uint32 memc_or0; /* option register 0 */ + volatile cyg_uint32 memc_br1; /* base register 1 */ + volatile cyg_uint32 memc_or1; /* option register 1 */ + volatile cyg_uint32 memc_br2; /* base register 2 */ + volatile cyg_uint32 memc_or2; /* option register 2 */ + volatile cyg_uint32 memc_br3; /* base register 3 */ + volatile cyg_uint32 memc_or3; /* option register 3 */ + volatile cyg_uint32 memc_br4; /* base register 3 */ + volatile cyg_uint32 memc_or4; /* option register 3 */ + volatile cyg_uint32 memc_br5; /* base register 3 */ + volatile cyg_uint32 memc_or5; /* option register 3 */ + volatile cyg_uint32 memc_br6; /* base register 3 */ + volatile cyg_uint32 memc_or6; /* option register 3 */ + volatile cyg_uint32 memc_br7; /* base register 3 */ + volatile cyg_uint32 memc_or7; /* option register 3 */ + volatile cyg_uint8 RESERVED20[0x24]; /* Reserved area */ + volatile cyg_uint32 memc_mar; /* Memory address */ + volatile cyg_uint32 memc_mcr; /* Memory command */ + volatile cyg_uint8 RESERVED21[0x4]; /* Reserved area */ + volatile cyg_uint32 memc_mamr; /* Machine A mode */ + volatile cyg_uint32 memc_mbmr; /* Machine B mode */ + volatile cyg_uint16 memc_mstat; /* Memory status */ + volatile cyg_uint16 memc_mptpr; /* Memory preidic timer prescalar */ + volatile cyg_uint32 memc_mdr; /* Memory data */ + volatile cyg_uint8 RESERVED22[0x80]; /* Reserved area */ + + /*---------------------------*/ + /* SYSTEM INTEGRATION TIMERS */ + /*---------------------------*/ + + volatile cyg_uint16 simt_tbscr; /* Time base stat&ctr */ + volatile cyg_uint8 RESERVED23[0x2]; /* Reserved area */ + volatile cyg_uint32 simt_tbreff0; /* Time base reference 0 */ + volatile cyg_uint32 simt_tbreff1; /* Time base reference 1 */ + volatile cyg_uint8 RESERVED24[0x14]; /* Reserved area */ + volatile cyg_uint16 simt_rtcsc; /* Realtime clk stat&cntr 1 */ + volatile cyg_uint8 RESERVED25[0x2]; /* Reserved area */ + volatile cyg_uint32 simt_rtc; /* Realtime clock */ + volatile cyg_uint32 simt_rtsec; /* Realtime alarm seconds */ + volatile cyg_uint32 simt_rtcal; /* Realtime alarm */ + volatile cyg_uint8 RESERVED26[0x10]; /* Reserved area */ + volatile cyg_uint32 simt_piscr; /* PIT stat&ctrl */ + volatile cyg_uint32 simt_pitc; /* PIT counter */ + volatile cyg_uint32 simt_pitr; /* PIT */ + volatile cyg_uint8 RESERVED27[0x34]; /* Reserved area */ + + /*---------------*/ + /* CLOCKS, RESET */ + /*---------------*/ + + volatile cyg_uint32 clkr_sccr; /* System clk cntrl */ + volatile cyg_uint32 clkr_plprcr; /* PLL reset&ctrl */ + volatile cyg_uint32 clkr_rsr; /* reset status */ + cyg_uint8 RESERVED28[0x74]; /* Reserved area */ + + /*--------------------------------*/ + /* System Integration Timers Keys */ + /*--------------------------------*/ + + volatile cyg_uint32 simt_tbscrk; /* Timebase Status&Ctrl Key */ + volatile cyg_uint32 simt_tbreff0k; /* Timebase Reference 0 Key */ + volatile cyg_uint32 simt_tbreff1k; /* Timebase Reference 1 Key */ + volatile cyg_uint32 simt_tbk; /* Timebase and Decrementer Key */ + cyg_uint8 RESERVED29[0x10]; /* Reserved area */ + volatile cyg_uint32 simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */ + + volatile cyg_uint32 simt_rtck; /* Real-Time Clock Key */ + volatile cyg_uint32 simt_rtseck; /* Real-Time Alarm Seconds Key */ + volatile cyg_uint32 simt_rtcalk; /* Real-Time Alarm Key */ + cyg_uint8 RESERVED30[0x10]; /* Reserved area */ + volatile cyg_uint32 simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */ + volatile cyg_uint32 simt_pitck; /* Periodic Interrupt Count Key */ + cyg_uint8 RESERVED31[0x38]; /* Reserved area */ + + /*----------------------*/ + /* Clock and Reset Keys */ + /*----------------------*/ + + volatile cyg_uint32 clkr_sccrk; /* System Clock Control Key */ + volatile cyg_uint32 clkr_plprcrk; /* PLL, Low Power and Reset Control Key */ + volatile cyg_uint32 clkr_rsrk; /* Reset Status Key */ + cyg_uint8 RESERVED32[0x4d4]; /* Reserved area */ + + /*-----*/ + /* I2C */ + /*-----*/ + + volatile cyg_uint8 i2c_i2mod; /* i2c mode */ + cyg_uint8 RESERVED33[3]; + volatile cyg_uint8 i2c_i2add; /* i2c address */ + cyg_uint8 RESERVED34[3]; + volatile cyg_uint8 i2c_i2brg; /* i2c brg */ + cyg_uint8 RESERVED35[3]; + volatile cyg_uint8 i2c_i2com; /* i2c command */ + cyg_uint8 RESERVED36[3]; + volatile cyg_uint8 i2c_i2cer; /* i2c event */ + cyg_uint8 RESERVED37[3]; + volatile cyg_uint8 i2c_i2cmr; /* i2c mask */ + volatile cyg_uint8 RESERVED38[0x8b]; /* Reserved area */ + + /*-----*/ + /* DMA */ + /*-----*/ + + volatile cyg_uint8 RESERVED39[0x4]; /* Reserved area */ + volatile cyg_uint32 dma_sdar; /* SDMA address reg */ + volatile cyg_uint8 RESERVED40[0x2]; /* Reserved area */ + volatile cyg_uint8 dma_sdsr; /* SDMA status reg */ + volatile cyg_uint8 RESERVED41[0x3]; /* Reserved area */ + volatile cyg_uint8 dma_sdmr; /* SDMA mask reg */ + volatile cyg_uint8 RESERVED42[0x1]; /* Reserved area */ + volatile cyg_uint8 dma_idsr1; /* IDMA1 status reg */ + volatile cyg_uint8 RESERVED43[0x3]; /* Reserved area */ + volatile cyg_uint8 dma_idmr1; /* IDMA1 mask reg */ + volatile cyg_uint8 RESERVED44[0x3]; /* Reserved area */ + volatile cyg_uint8 dma_idsr2; /* IDMA2 status reg */ + volatile cyg_uint8 RESERVED45[0x3]; /* Reserved area */ + volatile cyg_uint8 dma_idmr2; /* IDMA2 mask reg */ + volatile cyg_uint8 RESERVED46[0x13]; /* Reserved area */ + + /*--------------------------*/ + /* CPM Interrupt Controller */ + /*--------------------------*/ + + volatile cyg_uint16 cpmi_civr; /* CP interrupt vector reg */ + volatile cyg_uint8 RESERVED47[0xe]; /* Reserved area */ + volatile cyg_uint32 cpmi_cicr; /* CP interrupt configuration reg */ + volatile cyg_uint32 cpmi_cipr; /* CP interrupt pending reg */ + volatile cyg_uint32 cpmi_cimr; /* CP interrupt mask reg */ + volatile cyg_uint32 cpmi_cisr; /* CP interrupt in-service reg */ + + /*----------*/ + /* I/O port */ + /*----------*/ + + volatile cyg_uint16 pio_padir; /* port A data direction reg */ + volatile cyg_uint16 pio_papar; /* port A pin assignment reg */ + volatile cyg_uint16 pio_paodr; /* port A open drain reg */ + volatile cyg_uint16 pio_padat; /* port A data register */ + volatile cyg_uint8 RESERVED48[0x8]; /* Reserved area */ + volatile cyg_uint16 pio_pcdir; /* port C data direction reg */ + volatile cyg_uint16 pio_pcpar; /* port C pin assignment reg */ + volatile cyg_uint16 pio_pcso; /* port C special options */ + volatile cyg_uint16 pio_pcdat; /* port C data register */ + volatile cyg_uint16 pio_pcint; /* port C interrupt cntrl reg */ + cyg_uint8 RESERVED49[6]; + volatile cyg_uint16 pio_pddir; /* port D Data Direction reg */ + volatile cyg_uint16 pio_pdpar; /* port D pin assignment reg */ + cyg_uint8 RESERVED50[2]; + volatile cyg_uint16 pio_pddat; /* port D data reg */ + volatile cyg_uint8 RESERVED51[0x8]; /* Reserved area */ + + /*-----------*/ + /* CPM Timer */ + /*-----------*/ + + volatile cyg_uint16 timer_tgcr; /* timer global configuration reg */ + volatile cyg_uint8 RESERVED52[0xe]; /* Reserved area */ + volatile cyg_uint16 timer_tmr1; /* timer 1 mode reg */ + volatile cyg_uint16 timer_tmr2; /* timer 2 mode reg */ + volatile cyg_uint16 timer_trr1; /* timer 1 referance reg */ + volatile cyg_uint16 timer_trr2; /* timer 2 referance reg */ + volatile cyg_uint16 timer_tcr1; /* timer 1 capture reg */ + volatile cyg_uint16 timer_tcr2; /* timer 2 capture reg */ + volatile cyg_uint16 timer_tcn1; /* timer 1 counter reg */ + volatile cyg_uint16 timer_tcn2; /* timer 2 counter reg */ + volatile cyg_uint16 timer_tmr3; /* timer 3 mode reg */ + volatile cyg_uint16 timer_tmr4; /* timer 4 mode reg */ + volatile cyg_uint16 timer_trr3; /* timer 3 referance reg */ + volatile cyg_uint16 timer_trr4; /* timer 4 referance reg */ + volatile cyg_uint16 timer_tcr3; /* timer 3 capture reg */ + volatile cyg_uint16 timer_tcr4; /* timer 4 capture reg */ + volatile cyg_uint16 timer_tcn3; /* timer 3 counter reg */ + volatile cyg_uint16 timer_tcn4; /* timer 4 counter reg */ + volatile cyg_uint16 timer_ter1; /* timer 1 event reg */ + volatile cyg_uint16 timer_ter2; /* timer 2 event reg */ + volatile cyg_uint16 timer_ter3; /* timer 3 event reg */ + volatile cyg_uint16 timer_ter4; /* timer 4 event reg */ + volatile cyg_uint8 RESERVED53[0x8]; /* Reserved area */ + + /*----*/ + /* CP */ + /*----*/ + + volatile cyg_uint16 cp_cr; /* command register */ + volatile cyg_uint8 RESERVED54[0x2]; /* Reserved area */ + volatile cyg_uint16 cp_rccr; /* main configuration reg */ + volatile cyg_uint8 RESERVED55; /* Reserved area */ + volatile cyg_uint8 cp_resv1; /* Reserved reg */ + volatile cyg_uint32 cp_resv2; /* Reserved reg */ + volatile cyg_uint16 cp_rctr1; /* ram break register 1 */ + volatile cyg_uint16 cp_rctr2; /* ram break register 2 */ + volatile cyg_uint16 cp_rctr3; /* ram break register 3 */ + volatile cyg_uint16 cp_rctr4; /* ram break register 4 */ + volatile cyg_uint8 RESERVED56[0x2]; /* Reserved area */ + volatile cyg_uint16 cp_rter; /* RISC timers event reg */ + volatile cyg_uint8 RESERVED57[0x2]; /* Reserved area */ + volatile cyg_uint16 cp_rtmr; /* RISC timers mask reg */ + volatile cyg_uint8 RESERVED58[0x14]; /* Reserved area */ + + /*-----*/ + /* BRG */ + /*-----*/ + + volatile cyg_uint32 brgc1; /* BRG1 configuration reg */ + volatile cyg_uint32 brgc2; /* BRG2 configuration reg */ + volatile cyg_uint32 brgc3; /* BRG3 configuration reg */ + volatile cyg_uint32 brgc4; /* BRG4 configuration reg */ + + /*---------------*/ + /* SCC registers */ + /*---------------*/ + + struct scc_regs + + { + volatile cyg_uint32 scc_gsmr_l; /* SCC Gen mode (LOW) */ + volatile cyg_uint32 scc_gsmr_h; /* SCC Gen mode (HIGH) */ + volatile cyg_uint16 scc_psmr; /* protocol specific mode register */ + volatile cyg_uint8 RESERVED59[0x2]; /* Reserved area */ + volatile cyg_uint16 scc_todr; /* SCC transmit on demand */ + volatile cyg_uint16 scc_dsr; /* SCC data sync reg */ + volatile cyg_uint16 scc_scce; /* SCC event reg */ + volatile cyg_uint8 RESERVED60[0x2]; /* Reserved area */ + volatile cyg_uint16 scc_sccm; /* SCC mask reg */ + volatile cyg_uint8 RESERVED61[0x1]; /* Reserved area */ + volatile cyg_uint8 scc_sccs; /* SCC status reg */ + volatile cyg_uint8 RESERVED62[0x8]; /* Reserved area */ + + } scc_regs[4]; + + + /*-----*/ + /* SMC */ + /*-----*/ + + struct smc_regs + + { + volatile cyg_uint8 RESERVED63[0x2]; /* Reserved area */ + volatile cyg_uint16 smc_smcmr; /* SMC mode reg */ + volatile cyg_uint8 RESERVED64[0x2]; /* Reserved area */ + volatile cyg_uint8 smc_smce; /* SMC event reg */ + volatile cyg_uint8 RESERVED65[0x3]; /* Reserved area */ + volatile cyg_uint8 smc_smcm; /* SMC mask reg */ + volatile cyg_uint8 RESERVED66[0x5]; /* Reserved area */ + + } smc_regs[2]; + + + /*-----*/ + /* SPI */ + /*-----*/ + + volatile cyg_uint16 spi_spmode; /* SPI mode reg */ + volatile cyg_uint8 RESERVED67[0x4]; /* Reserved area */ + volatile cyg_uint8 spi_spie; /* SPI event reg */ + volatile cyg_uint8 RESERVED68[0x3]; /* Reserved area */ + volatile cyg_uint8 spi_spim; /* SPI mask reg */ + volatile cyg_uint8 RESERVED69[0x2]; /* Reserved area */ + volatile cyg_uint8 spi_spcom; /* SPI command reg */ + volatile cyg_uint8 RESERVED70[0x4]; /* Reserved area */ + + /*-----*/ + /* PIP */ + /*-----*/ + + volatile cyg_uint16 pip_pipc; /* pip configuration reg */ + volatile cyg_uint8 RESERVED71[0x2]; /* Reserved area */ + volatile cyg_uint16 pip_ptpr; /* pip timing parameters reg */ + volatile cyg_uint32 pip_pbdir; /* port b data direction reg */ + volatile cyg_uint32 pip_pbpar; /* port b pin assignment reg */ + volatile cyg_uint8 RESERVED72[0x2]; /* Reserved area */ + volatile cyg_uint16 pip_pbodr; /* port b open drain reg */ + volatile cyg_uint32 pip_pbdat; /* port b data reg */ + volatile cyg_uint8 RESERVED73[0x18]; /* Reserved area */ + + + /*------------------*/ + /* Serial Interface */ + /*------------------*/ + + volatile cyg_uint32 si_simode; /* SI mode register */ + volatile cyg_uint8 si_sigmr; /* SI global mode register */ + volatile cyg_uint8 RESERVED74; /* Reserved area */ + volatile cyg_uint8 si_sistr; /* SI status register */ + volatile cyg_uint8 si_sicmr; /* SI command register */ + volatile cyg_uint8 RESERVED75[0x4]; /* Reserved area */ + volatile cyg_uint32 si_sicr; /* SI clock routing */ + volatile cyg_uint32 si_sirp; /* SI ram pointers */ + volatile cyg_uint8 RESERVED76[0x10c]; /* Reserved area */ + volatile cyg_uint8 si_siram[0x200]; /* SI routing ram */ + volatile cyg_uint8 RESERVED77[0x1200]; /* Reserved area */ + + /*-----------------------------------------------------------------*/ + /* BASE + 0x2000: user data memory, microcode, or QMC channel PRAM */ + /*-----------------------------------------------------------------*/ + + union + { + struct qmc_chan_pram qcp[64]; + struct user_data ud; + cyg_uint8 RESERVED[0x1c00]; + } qcp_or_ud; + + + /*-----------------------------------------------------------------------*/ + /* BASE + 0x3c00: PARAMETER RAM. This main union defines 4 memory blocks */ + /* of an identical size. See the Parameter RAM definition in the MPC860 */ + /* user's manual. */ + /*-----------------------------------------------------------------------*/ + + /*------------------------*/ + /* Base + 0x3C00 (page 1) */ + /* + 0x3D00 (page 2) */ + /* + 0x3E00 (page 3) */ + /* + 0x3F00 (page 4) */ + /*------------------------*/ + + union + + { + struct page_of_pram + + { + /*------------------------------------------------------------*/ + /* scc parameter area - 1st memory block (protocol dependent) */ + /*------------------------------------------------------------*/ + + union + + { + struct hdlc_pram h; + struct uart_pram u; + struct bisync_pram b; + struct transparent_pram t; + struct async_hdlc_pram a; + cyg_uint8 RESERVED78[0x80]; + + } scc; + + /*----------------------------------------------------------------*/ + /* Other protocol areas for the rest of the memory blocks in each */ + /* page. */ + /*----------------------------------------------------------------*/ + + union + + { + /*---------------------------------------------------------------*/ + /* This structure defines the rest of the blocks on the 1st page */ + /*---------------------------------------------------------------*/ + + struct + + { + struct i2c_pram i2c; /* I2C */ + struct misc_pram misc; /* MISC */ + struct idma_pram idma1; /* IDMA1 */ + + } i2c_idma; + + /*---------------------------------------------------------------*/ + /* This structure defines the rest of the blocks on the 2nd page */ + /*---------------------------------------------------------------*/ + + struct + + { + struct spi_pram spi; /* SPI */ + struct timer_pram timer; /* Timers */ + struct idma_pram idma2; /* IDMA2 */ + + } spi_timer_idma; + + /*---------------------------------------------------------------*/ + /* This structure defines the rest of the blocks on the 3rd page */ + /*---------------------------------------------------------------*/ + + struct + + { + union + + { + struct smc_uart_pram u1; /* SMC1 */ + struct smc_trnsp_pram t1; /* SMC1 */ + cyg_uint8 RESERVED78[0x80]; /* declare full block */ + + } psmc1; + + } smc_dsp1; + + + /*---------------------------------------------------------------*/ + /* This structure defines the rest of the blocks on the 4th page */ + /*---------------------------------------------------------------*/ + + struct + + { + union + + { + struct smc_uart_pram u2; /* SMC2 */ + struct smc_trnsp_pram t2; /* SMC2 */ + struct centronics_pram c; /* Uses SM2's space */ + cyg_uint8 RESERVED79[0x80]; /* declare full block */ + + } psmc2; + + } smc_dsp2; + + cyg_uint8 RESERVED80[0x80]; /* declare full block */ + + } other; + + } pg; + + /*---------------------------------------------------------------*/ + /* When selecting Ethernet as protocol for an SCC, this protocol */ + /* uses a complete page of Parameter RAM memory. */ + /*---------------------------------------------------------------*/ + + struct ethernet_pram enet_scc; + + /*---------------------------------------------------------------*/ + /* When using QMC as a mode for an SCC, the QMC global parameter */ + /* ram uses from SCC BASE to BASE+AC. */ + /*---------------------------------------------------------------*/ + + struct global_qmc_pram gqp; + + /*--------------------------------------------------------*/ + /* declaration to guarantee a page of memory is allocated */ + /*--------------------------------------------------------*/ + + cyg_uint8 RESERVED83[0x100]; + + } PRAM[4]; /* end of union */ + +} EPPC; + + +/***************************************************************************/ +/* General Global Definitions */ +/***************************************************************************/ + + +#define PAGE1 0 /* SCC1 Index into SCC Param RAM Array */ +#define PAGE2 1 /* SCC2 Index into SCC Param RAM Array */ +#define PAGE3 2 /* SCC3 Index into SCC Param RAM Array */ +#define PAGE4 3 /* SCC4 Index into SCC Param RAM Array */ + +#define SCC1_REG 0 /* SCC1 Index into SCC Regs Array */ +#define SCC2_REG 1 /* SCC2 Index into SCC Regs Array */ +#define SCC3_REG 2 /* SCC3 Index into SCC Regs Array */ +#define SCC4_REG 3 /* SCC4 Index into SCC Regs Array */ + + +/*--------------------------------*/ +/* KEEP ALIVE POWER REGISTERS KEY */ +/*--------------------------------*/ + +#define KEEP_ALIVE_KEY 0x55ccaa33 + + +#define SMC2_REG 1 /* SMC Regs Array Index for SMC2 */ + +/*-------------------------*/ +/* Single buffer component */ +/*-------------------------*/ + +typedef struct BufferPool + +{ + cyg_uint8 RxBuffer; + cyg_uint8 TxBuffer; + +} LB; + + +/*--------------------------*/ +/* Buffer Descriptor Format */ +/*--------------------------*/ + +typedef struct BufferDescriptor + +{ + cyg_uint16 bd_cstatus; /* control and status */ + cyg_uint16 bd_length; /* transfer length */ + cyg_uint8 *bd_addr; /* buffer address */ + +} BD; + + +/*-------------------------------*/ +/* Buffer Descriptor Ring format */ +/*-------------------------------*/ + +typedef struct BufferDescRings + +{ + volatile BD RxBD; /* Rx BD ring */ + volatile BD TxBD; /* Tx BD ring */ + +} BDRINGS; + + +#endif /* CYGONCE_HAL_PPC_FADS_PPC_860_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/fads/current/src/quicc_smc2.c @@ -0,0 +1,446 @@ +//============================================================================= +//####UNSUPPORTEDBEGIN#### +// +// ------------------------------------------- +// This source file has been contributed to eCos/Cygnus. It may have been +// changed slightly to provide an interface consistent with those of other +// files. +// +// The functionality and contents of this file is supplied "AS IS" +// without any form of support and will not necessarily be kept up +// to date by Cygnus. +// +// The style of programming used in this file may not comply with the +// eCos programming guidelines. Please do not use as a base for other +// files. +// +// All inquiries about this file, or the functionality provided by it, +// should be directed to the 'ecos-discuss' mailing list (see +// http://sourceware.cygnus.com/ecos/intouch.html for details). +// +// Contributed by: Kevin Hester <khester@opticworks.com> +// Maintained by: <Unmaintained> +// See also: +// Motorola's "Example Software Initializing the SMC as a UART" package +// (smc2.zip) at: +// http://www.mot.com/SPS/RISC/netcomm/tools/index.html#MPC860_table +// ------------------------------------------- +// +//####UNSUPPORTEDEND#### +//============================================================================= +/*------------------------------------------------------------------------- +* FILENAME: smc2.c +* +* DESCRIPTION: +* +* The code in this module provides echo capability on SMC2. It's +* intent is to provide the beginnings of a debug port that is +* mostly compiler independent. If an ASCII terminal is connected +* at 9600,N,8,1 on Port 2 (PB3) on the ADS board with no hardware +* control, characters typed on the keyboard will be received by +* SMC2 and echoed back out the RS232 port to the ASCII terminal. +* This function was designed and tested on an ADS860 +* development board. Note that if a different baud rate is +* required, there is a header file on the netcomm website under +* the General Software category that is labelled "Asynchronous +* Baud Rate Tables". +* +* REFERENCES: +* +* 1) MPC860 Users Manual +* 2) PowerPC Microprocessor Family: The Programming Environments for +* 32-Bit Microprocessors +* +* HISTORY: +* +* 27 APR 98 jay initial release +* +*-------------------------------------------------------------------------*/ + +#include <cyg/hal/quicc_smc2.h> +#include "ppc_860.h" + +/***********************/ +/* Global Declarations */ +/***********************/ + +static EPPC *IMMR; /* IMMR base pointer */ +static BDRINGS *RxTxBD; /* buffer descriptors base pointer */ +static LB *SMC2Buffers; /* SMC2 base pointers */ + +/*---------------------*/ +/* Function Prototypes */ +/*---------------------*/ + +//static char SMC2Poll(void); +static void InitBDs(void); +//static void EchoChar(void); +static unsigned long GetIMMR(void); + + +/*----------------------------------------------------------------------------- +* +* FUNCTION NAME: cyg_smc2_init +* +* DESCRIPTION: +* +* EXTERNAL EFFECT: +* +* PARAMETERS: None +* +* RETURNS: None +* +*---------------------------------------------------------------------------*/ + +void cyg_smc2_init(unsigned long baudRate) + +{ + unsigned long *bcsr1; + unsigned long clockRate = 20 * 1000 * 1000; // 20Mhz + unsigned long divider = clockRate / (baudRate * 16) - 1; + + /*------------------------*/ + /* Establish IMMR pointer */ + /*------------------------*/ + + IMMR = (EPPC *)(GetIMMR() & 0xFFFF0000); /* MPC8xx internal register + map */ + + /*-----------------------------------------------*/ + /* Enable RS232 interface on ADS board via BCSR1 */ + /* Get the base address of BCSR */ + /*-----------------------------------------------*/ + + bcsr1 = (unsigned long *) ((IMMR->memc_br1 & 0xffff0000) + 4); + *bcsr1 &= ~(1 << 18); // turn on RS232 port 2 + + + /*-----------------------*/ + /* Allow SMC2 TX, RX out */ + /*-----------------------*/ + + IMMR->pip_pbpar |= (0x0C00); + IMMR->pip_pbdir &= 0xF3FF; + + /*------------------------------------------------*/ + /* Set Baud Rate to 9600 for 40MHz System Clock. */ + /* Enable BRG Count. */ + /*------------------------------------------------*/ + + IMMR->brgc2 = ((divider << 1) | 0x10000); + + IMMR->si_simode &= ~(0xF0000000); /* SCM2: NMSI mode */ + IMMR->si_simode |= 0x10000000; /* SCM2: Tx/Rx Clocks are BRG2 */ + + + /*----------------------------------------*/ + /* Set RXBD table start at Dual Port +800 */ + /*----------------------------------------*/ + + IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.rbase = (unsigned short) (unsigned) &RxTxBD->RxBD; + + /*----------------------------------------*/ + /* Set TXBD table start at Dual Port +808 */ + /*----------------------------------------*/ + + IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.tbase = (unsigned short) (unsigned) &RxTxBD->TxBD; + + /*---------------------------------------*/ + /* Initialize Rx and Tx Params for SMC2: */ + /* Spin until cpcr flag is cleared */ + /*---------------------------------------*/ + + for(IMMR->cp_cr = 0x00d1; IMMR->cp_cr & 0x0001;) ; + + + /*--------------------------------------*/ + /* Set RFCR,TFCR -- Rx,Tx Function Code */ + /* Normal Operation and Motorola byte */ + /* ordering */ + /*--------------------------------------*/ + + IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.rfcr = 0x18; + IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.tfcr = 0x18; + + /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ + /* Protocol Specific Parameters */ + /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ + + /*---------------------------*/ + /* MRBLR = MAX buffer length */ + /*---------------------------*/ + + IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.mrblr = 1; + + /*------------------------------------*/ + /* MAX_IDL = Disable MAX Idle Feature */ + /*------------------------------------*/ + + IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.max_idl = 0; + + /*-------------------------------------*/ + /* BRKEC = No break condition occurred */ + /*-------------------------------------*/ + + IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.brkec = 0; + + /*---------------------------------------*/ + /* BRKCR = 1 break char sent on top XMIT */ + /*---------------------------------------*/ + + IMMR->PRAM[PAGE4].pg.other.smc_dsp2.psmc2.u2.brkcr = 1; + + /*--------------------*/ + /* Initialize the BDs */ + /*--------------------*/ + + InitBDs(); + + IMMR->smc_regs[SMC2_REG].smc_smce = 0xFF; /* Clear any pending events */ + + /*--------------------------------------------------*/ + /* SMC_SMCM = Mask all interrupts, use polling mode */ + /*--------------------------------------------------*/ + + IMMR->smc_regs[SMC2_REG].smc_smcm = 0; + + IMMR->cpmi_cicr = 0; /* Disable all CPM interrups */ + IMMR->cpmi_cipr = 0xFFFFFFFF; /* Clear all pending interrupt events */ + IMMR->cpmi_cimr = 0; /* Mask all event interrupts */ + + /*------------------------------------*/ + /* 8-bit mode, no parity, 1 stop-bit */ + /* UART SMC Mode */ + /* Normal operation (no loopback), */ + /* SMC Transmitter/Receiver Enabled */ + /*------------------------------------*/ + + IMMR->smc_regs[SMC2_REG].smc_smcmr = 0x4823; + +} + + + +/*----------------------------------------------------------------------------- +* +* FUNCTION NAME: InitBDs +* +* DESCRIPTION: This function initializes the Tx and Rx Buffer Descriptors. +* +* EXTERNAL EFFECT: RxTxBD +* +* PARAMETERS: None +* +* RETURNS: None +* +*---------------------------------------------------------------------------*/ + +static void InitBDs(void) + +{ + /*--------------------------------------------------------------------*/ + /* We add 64 bytes to the start of the buffer descriptors because */ + /* this code was also tested on the monitor version of SDS debugger. */ + /* The monitor program on our target uses most of the first 64 bytes */ + /* for buffer descriptors. If you are not using the SDS monitor with */ + /* Motorola's ADS development board, you can delete 64 below and */ + /* start at the beginning of this particular block of Dual Port RAM. */ + /*--------------------------------------------------------------------*/ + + /*----------------------------------*/ + /* Get pointer to BD area on DP RAM */ + /*----------------------------------*/ + + RxTxBD = (BDRINGS *)(IMMR->qcp_or_ud.ud.udata_bd + 64); + + /*-------------------------------------------------------------------*/ + /* Establish the buffer pool in Dual Port RAM. We do this because the*/ + /* pool size is only 2 bytes (1 for Rx and 1 for Tx) and to avoid */ + /* disabling data cache for the memory region where BufferPool would */ + /* reside. The CPM does not recognize data in buffer pools once it */ + /* been cached. It's acesses are direct through DMA to external */ + /* memory. */ + /*-------------------------------------------------------------------*/ + + SMC2Buffers = (LB *)(IMMR->qcp_or_ud.ud.udata_bd + 80); + + /*-----------------------------------*/ + /* Setup Receiver Buffer Descriptors */ + /*-----------------------------------*/ + + RxTxBD->RxBD.bd_cstatus = 0xA000; /* Enable, Last BD */ + RxTxBD->RxBD.bd_length = 1; + RxTxBD->RxBD.bd_addr = &(SMC2Buffers->RxBuffer); + + + /*--------------------------------------*/ + /* Setup Transmitter Buffer Descriptors */ + /*--------------------------------------*/ + + RxTxBD->TxBD.bd_cstatus = 0x2000; /* Buffer not yet ready; Last BD */ + RxTxBD->TxBD.bd_length = 1; + RxTxBD->TxBD.bd_addr = &(SMC2Buffers->TxBuffer); + +} /* END InitBDs */ + + +#if 0 // static unused function. -jskov 19990122 +/*----------------------------------------------------------------------------- +* +* FUNCTION NAME: EchoChar +* +* DESCRIPTION: This function facilitates the echoing of a received character. +* +* EXTERNAL EFFECT: RxTxBD +* +* PARAMETERS: None +* +* RETURNS: None +* +*---------------------------------------------------------------------------*/ + +static void EchoChar(void) + +{ + char mych; + + mych = cyg_smc2_getchar(); + cyg_smc2_putchar(mych); + +} /* end EchoChar */ +#endif + +/*----------------------------------------------------------------------------- +* +* FUNCTION NAME: cyg_smc2_putchar +* +* DESCRIPTION: Output a character to SMC2 +* +* EXTERNAL EFFECT: RxTxBD +* +* PARAMETERS: ch - input character +* +* RETURNS: None +* +*---------------------------------------------------------------------------*/ + +void cyg_smc2_putchar(char ch) + +{ + /*-----------------------------------*/ + /* Loop until transmission completed */ + /*-----------------------------------*/ + + while (RxTxBD->TxBD.bd_cstatus & 0x8000); + + /*------------*/ + /* Store data */ + /*------------*/ + + *(RxTxBD->TxBD.bd_addr) = ch; + RxTxBD->TxBD.bd_length = 1; + + /*---------------*/ + /* Set Ready bit */ + /*---------------*/ + + RxTxBD->TxBD.bd_cstatus |= 0x8000; + +} + + + +/*----------------------------------------------------------------------------- +* +* FUNCTION NAME: cyg_smc2_getchar +* +* DESCRIPTION: Get a character from SMC2 +* +* EXTERNAL EFFECT: RxTxBD +* +* PARAMETERS: NONE +* +* RETURNS: A character from SMC2 +* +*---------------------------------------------------------------------------*/ + +char cyg_smc2_getchar(void) + +{ + + char ch; /* output character from SMC2 */ + + /*--------------------*/ + /* Loop if RxBD empty */ + /*--------------------*/ + + while (RxTxBD->RxBD.bd_cstatus & 0x8000); + + /*--------------*/ + /* Receive data */ + /*--------------*/ + + ch = *(RxTxBD->RxBD.bd_addr); + + /*----------------------*/ + /* Set Buffer Empty bit */ + /*----------------------*/ + + RxTxBD->RxBD.bd_cstatus |= 0x8000; + + return ch; + +} + + +#if 0 // static unused function. -jskov 19990122 +/*----------------------------------------------------------------------------- +* +* FUNCTION NAME: SMC2Poll +* +* DESCRIPTION: Poll SMC2 RxBD and check to see if a character was received +* +* EXTERNAL EFFECT: NONE +* +* PARAMETERS: NONE +* +* RETURNS: A one if there is a character available in the receive buffer, +* else zero. +* +*---------------------------------------------------------------------------*/ + +static char SMC2Poll(void) + +{ + return (RxTxBD->RxBD.bd_cstatus & 0x8000) ? 0 : 1; + +} /* END SMC2Poll */ +#endif + + +/*----------------------------------------------------------------------------- +* +* FUNCTION NAME: GetIMMR +* +* DESCRIPTION: Returns current value in the IMMR register. +* +* EXTERNAL EFFECT: NONE +* +* PARAMETERS: NONE +* +* RETURNS: The IMMR value in r3. The compiler uses r3 as the register +* containing the return value. +* +*---------------------------------------------------------------------------*/ + +static unsigned long GetIMMR(void) + +{ + unsigned long ret; + asm volatile (" mfspr %0,638 " : "=r" (ret)); /* IMMR is spr #638 */ + + return ret; +} + + +/* EOF hal/powerpc/fads/quicc_smc2.c */
--- a/packages/hal/sparclite/arch/current/ChangeLog +++ b/packages/hal/sparclite/arch/current/ChangeLog @@ -1,3 +1,8 @@ +1999-06-07 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_arch.h (hal_jmp_buf): force this to be 64-bit + aligned so that std ops in hal_setjmp(), hal_longjmp() work. + 1999-06-03 Hugo Tyson <hmt@cygnus.co.uk> * src/hal_boot.c: Add a dummy __gccmain() to prevent ctors being
--- a/packages/hal/sparclite/arch/current/include/hal_arch.h +++ b/packages/hal/sparclite/arch/current/include/hal_arch.h @@ -51,6 +51,9 @@ //-------------------------------------------------------------------------- // Processor saved states: +// +// All these structures must be doubleword (64 bit) aligned. +// The code that creates them on the stack will ensure this is so. #define HAL_THREAD_CONTEXT_GLOBAL_BASE 0 #define HAL_THREAD_CONTEXT_OUT_BASE 8 @@ -236,9 +239,11 @@ CYG_MACRO_END //--------------------------------------------------------------------------- // HAL setjmp -#define HAL_JMP_BUF_SIZE 32 // laziness; use a thread context for now +#define HAL_JMP_BUF_SIZE 32 // (words) -typedef cyg_uint32 hal_jmp_buf[HAL_JMP_BUF_SIZE]; +// this too must be doubleword aligned (64 bit) + +typedef cyg_uint64 hal_jmp_buf[ HAL_JMP_BUF_SIZE / 2 ]; externC int hal_setjmp(hal_jmp_buf env); externC void hal_longjmp(hal_jmp_buf env, int val);
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -1,3 +1,13 @@ +1999-06-10 Hugo Tyson <hmt@cygnus.co.uk> + + * src/debug/dbg_gdb.cxx (dbg_threadinfo): Report counted sleep + correctly; both COUNTSLEEP and SLEEPING are set. + +1999-06-01 Hugo Tyson <hmt@masala.cygnus.co.uk> + + * src/debug/dbg_gdb.cxx (dbg_threadinfo): Make the thread state + string a little more sensible when read as plain english. + 1999-05-27 Nick Garnett <nickg@cygnus.co.uk> * src/intr/intr.cxx (Cyg_Interrupt::chain_isr): Calls
--- a/packages/kernel/current/src/debug/dbg_gdb.cxx +++ b/packages/kernel/current/src/debug/dbg_gdb.cxx @@ -277,15 +277,24 @@ externC int dbg_threadinfo( switch( thread->get_state() & ~Cyg_Thread::SUSPENDED ) { case Cyg_Thread::RUNNING: - s = "running"; break; + if ( Cyg_Scheduler::get_current_thread() == thread ) { + s = "running"; break; + } + else if ( thread->get_state() & Cyg_Thread::SUSPENDED ) { + s = ""; sbp--; /*kill '+'*/ break; + } + else { + s = "ready"; break; + } case Cyg_Thread::SLEEPING: s = "sleeping"; break; + case Cyg_Thread::COUNTSLEEP | Cyg_Thread::SLEEPING: case Cyg_Thread::COUNTSLEEP: s = "counted sleep"; break; case Cyg_Thread::CREATING: - s = "creating"; break; + s = "creating"; sbp = statebuf; break; case Cyg_Thread::EXITED: - s = "exited"; break; + s = "exited"; sbp = statebuf; break; default: s = "unknown state"; break; }
--- a/packages/language/c/libm/current/ChangeLog +++ b/packages/language/c/libm/current/ChangeLog @@ -1,7 +1,14 @@ +1999-06-07 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mathincl/fdlibm.h: Fix for alias problem + Fix for PR 19698 + * src/PKGconf.mak: workaround no longer needed + 1999-06-04 Jonathan Larmour <jlarmour@cygnus.co.uk> * src/PKGconf.mak: Only use -fno-strict-aliasing if we have enough a recent toolchain + Default is that we have 1999-06-03 Jonathan Larmour <jlarmour@cygnus.co.uk>
--- a/packages/language/c/libm/current/src/PKGconf.mak +++ b/packages/language/c/libm/current/src/PKGconf.mak @@ -71,14 +71,4 @@ OTHER_OBJS := OTHER_TARGETS := OTHER_CLEAN := -# Work-around for PR 19698 - -ifdef CYGPKG_HAL_ARM -RECENT_TOOLCHAIN=1 -endif - -ifeq ($(RECENT_TOOLCHAIN),1) -CFLAGS += -fno-strict-aliasing -endif - include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src
--- a/packages/language/c/libm/current/src/mathincl/fdlibm.h +++ b/packages/language/c/libm/current/src/mathincl/fdlibm.h @@ -71,10 +71,11 @@ // MACRO DEFINITIONS -#define CYG_LIBM_HI(__x) (*cyg_libm_hi(&__x)) -#define CYG_LIBM_LO(__x) (*cyg_libm_lo(&__x)) -#define CYG_LIBM_HIp(__x) (*cyg_libm_hi(__x)) -#define CYG_LIBM_LOp(__x) (*cyg_libm_lo(__x)) +#define CYG_LIBM_HI(__x) (((Cyg_libm_ieee_double_shape_type *)&__x)->parts.msw) +#define CYG_LIBM_LO(__x) (((Cyg_libm_ieee_double_shape_type *)&__x)->parts.lsw) +#define CYG_LIBM_HIp(__x) (((Cyg_libm_ieee_double_shape_type *)__x)->parts.msw) +#define CYG_LIBM_LOp(__x) (((Cyg_libm_ieee_double_shape_type *)__x)->parts.lsw) + // REPLACEMENTS FOR STUFF FROM MATH.H DUE TO CONFIG OPTION @@ -102,25 +103,6 @@ matherr( struct exception * ); // Use #endif // ifdef CYGSYM_LIBM_NO_XOPEN_SVID_NAMESPACE_POLLUTION -// INLINE FUNCTIONS - -static __inline__ cyg_uint32 * -cyg_libm_hi(double *__x) -{ - Cyg_libm_ieee_double_shape_type *__y; - __y = (Cyg_libm_ieee_double_shape_type *)__x; - return &__y->parts.msw; -} - -static __inline__ cyg_uint32 * -cyg_libm_lo(double *__x) -{ - Cyg_libm_ieee_double_shape_type *__y; - __y = (Cyg_libm_ieee_double_shape_type *)__x; - return &__y->parts.lsw; -} - - // FUNCTION PROTOTYPES // IEEE-754 style elementary functions */
--- a/packages/pkgconf.tcl +++ b/packages/pkgconf.tcl @@ -2062,7 +2062,9 @@ proc pkgconf::process_arguments { } { set pkgconf::config_data(platform) $platform } - set pkgconf::config_data(base_platform) [get_base_platform $target $platform] + if { ($target != "") && ($platform != "") } { + set pkgconf::config_data(base_platform) [get_base_platform $target $platform] + } if { ($target != "") && ($platform != "") && ($pkgconf::startup_arg != "" ) } { @@ -5607,8 +5609,8 @@ endif" # Additions for the MLT puts $file "\n" - puts $file "#define CYGHWR_MEMORY_LAYOUT_LDI <pkgconf/mlt_[set pkgconf::config_data(target)]_[set pkgconf::config_data(base_platform)]_[set pkgconf::config_data(startup)].ldi>" - puts $file "#define CYGHWR_MEMORY_LAYOUT_H <pkgconf/mlt_[set pkgconf::config_data(target)]_[set pkgconf::config_data(base_platform)]_[set pkgconf::config_data(startup)].h>" + puts $file "#define CYGHWR_MEMORY_LAYOUT_LDI <pkgconf/mlt_[set pkgconf::config_data(target)]_[set pkgconf::config_data(platform)]_[set pkgconf::config_data(startup)].ldi>" + puts $file "#define CYGHWR_MEMORY_LAYOUT_H <pkgconf/mlt_[set pkgconf::config_data(target)]_[set pkgconf::config_data(platform)]_[set pkgconf::config_data(startup)].h>" # Also output details of the HAL header files that should be included puts $file "\n"