Mercurial > ecos-v2_0-branch
changeset 44:41bd4f3a90de ecos-sw-1999-10-08
Merge from eCos master repository on 1999-10-08-07:47:04-BST
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,13 @@ +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * targets: Added AEB rev C target. + +1999-10-06 Bart Veer <bartv@cygnus.co.uk> + + * pkgconf.tcl: + Allow an empty command prefix string, useful for the synthetic + target. + 1999-09-10 Jonathan Larmour <jlarmour@cygnus.co.uk> * packages: Tidy whitespace a bit
--- a/packages/NEWS +++ b/packages/NEWS @@ -36,6 +36,7 @@ **** ARM: ARM720 - Cirrus Logic CL7211 board ARM710C - Cirrus Logic CL7111 board + Sharp LH77790 (ARM7DI core) - ARM AEB-1 rev C board **** PowerPC Motorola MBX PowerPC Evaluation Board @@ -84,4 +85,8 @@ ** HAL changes +*** i386/linux + The eCos idle loop will not load the host system anymore + (except in special configurations, see linux_misc.c). + *** Common
--- a/packages/hal/arm/aeb/current/ChangeLog +++ b/packages/hal/arm/aeb/current/ChangeLog @@ -1,3 +1,16 @@ +1999-10-07 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/hal_arm_aeb.h: + * include/hal_platform_setup.h: + Use CYGHWR_HAL_ARM_AEB_REVISION_C to select revision behavior. + +1999-10-05 Jesper Skov <jskov@cygnus.co.uk> + + * include/hal_platform_setup.h: Added support for AEB rev C. + + * src/aeb_misc.c (hal_hardware_init): Use UCACHE macros. + * include/hal_cache.h: Fixed cache macros. + 1999-09-07 Jesper Skov <jskov@cygnus.co.uk> * include/plf_stub.h:
--- a/packages/hal/arm/aeb/current/include/hal_cache.h +++ b/packages/hal/arm/aeb/current/include/hal_cache.h @@ -51,24 +51,20 @@ #include <cyg/hal/hal_io.h> //----------------------------------------------------------------------------- -// Cache dimensions +// Cache dimensions - one unified cache -// Data cache -#define HAL_DCACHE_SIZE 0x800 // Size of data cache in bytes -#define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line -#define HAL_DCACHE_WAYS 4 // Associativity of the cache +#define HAL_CACHE_UNIFIED -// Instruction cache -#define HAL_ICACHE_SIZE 0x800 // Size of cache in bytes -#define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line -#define HAL_ICACHE_WAYS 4 // Associativity of the cache +#define HAL_UCACHE_SIZE 0x800 // Size of cache in bytes +#define HAL_UCACHE_LINE_SIZE 4 // Size of a cache line +#define HAL_UCACHE_WAYS 4 // Associativity of the cache -#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) -#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) +#define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS)) // Cache & SRAM control -#define CYG_DEVICE_CCR ((volatile cyg_uint8 *)0xFFFFA400) -#define CYG_DEVICE_LSCR ((volatile cyg_uint8 *)0xFFFFA404) +#define CYG_DEVICE_CCR 0xFFFFA400 +#define CYG_DEVICE_LSCR 0xFFFFA404 +#define CYG_DEVICE_CACHE_MEM 0x60000800 #define CCR_E 0x01 // Cache enabled #define CCR_S 0x02 // SRAM mode enabled @@ -79,44 +75,131 @@ #define LCSR_L 0x02 // Local SRAM mapped to high memory //----------------------------------------------------------------------------- -// Global control of data cache +// Global control of cache -// Enable the data cache -#define HAL_DCACHE_ENABLE() \ +// Enable the cache +#define HAL_UCACHE_ENABLE() \ { \ - HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_E); \ + HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_E); \ } -// Disable the data cache -#define HAL_DCACHE_DISABLE() \ +// Disable the cache +#define HAL_UCACHE_DISABLE() \ { \ - HAL_WRITE_UINT32(CYG_DEVICE_CCR, 0); \ + HAL_WRITE_UINT8(CYG_DEVICE_CCR, 0); \ } // Invalidate the entire cache -#define HAL_DCACHE_INVALIDATE_ALL() \ -{ \ - HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_I); \ +#define HAL_UCACHE_INVALIDATE_ALL() \ +{ \ + register cyg_uint8 old_ccr; \ + HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \ + HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \ + HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \ } // Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() \ +#define HAL_UCACHE_SYNC() \ { \ - cyg_uint32 *cache_SRAM = (cyg_uint32 *)0x60000800; \ - int i; \ - cyg_uint32 old_ccr; \ - HAL_READ_UINT32(CYG_DEVICE_CCR, old_ccr); \ - HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_F); \ + register volatile cyg_uint8 *cache_SRAM = \ + (volatile cyg_uint8*) CYG_DEVICE_CACHE_MEM; \ + register int i; \ + register cyg_uint8 old_ccr; \ + HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \ + HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_F); \ for (i = 0; i < HAL_DCACHE_SETS; i++) { \ *cache_SRAM = 0; \ cache_SRAM += HAL_DCACHE_LINE_SIZE; \ } \ - HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_I); \ - HAL_WRITE_UINT32(CYG_DEVICE_CCR, old_ccr); \ + HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \ + HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \ +} + +// Query the state of the cache +#define HAL_UCACHE_IS_ENABLED(_state_) \ +{ \ + cyg_uint8 __ccr; \ + HAL_READ_UINT8(CYG_DEVICE_CCR, __ccr); \ + (_state_) = (CCR_E == __ccr) ? 1 : 0; \ } -// Purge contents of data cache -#define HAL_DCACHE_PURGE_ALL() HAL_DCACHE_INVALIDATE_ALL() +// Purge contents of cache +#define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL() + +// Set the cache refill burst size +//#define HAL_UCACHE_BURST_SIZE(_size_) + +// Set the cache write mode +//#define HAL_UCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_UCACHE_WRITETHRU_MODE 0 +//#define HAL_UCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the cache +// and then lock the cache so that it stays there. +//#define HAL_UCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_UCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_UCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_UCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_UCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_UCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_UCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_UCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Data and instruction cache macros map onto the both-cache macros + +//----------------------------------------------------------------------------- +// Global control of data cache + +#define HAL_DCACHE_SIZE HAL_UCACHE_SIZE +#define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE +#define HAL_DCACHE_WAYS HAL_UCACHE_WAYS +#define HAL_DCACHE_SETS HAL_UCACHE_SETS + +// Enable the data cache +#define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC() + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) // Set the data cache refill burst size //#define HAL_DCACHE_BURST_SIZE(_size_) @@ -166,26 +249,35 @@ //#define HAL_DCACHE_ZERO( _base_ , _size_ ) //----------------------------------------------------------------------------- -// Global control of Instruction cache - use Data cache controls since they -// are not separatable. +// Global control of Instruction cache + +#define HAL_ICACHE_SIZE HAL_UCACHE_SIZE +#define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE +#define HAL_ICACHE_WAYS HAL_UCACHE_WAYS +#define HAL_ICACHE_SETS HAL_UCACHE_SETS // Enable the instruction cache -#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE() +#define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE() // Disable the instruction cache -#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE() +#define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE() // Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC(); HAL_DCACHE_INVALIDATE_ALL() +#define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() + // Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() +#define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC() + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) // Set the instruction cache refill burst size //#define HAL_ICACHE_BURST_SIZE(_size_) // Load the contents of the given address range into the instruction cache // and then lock the cache so that it stays there. + //#define HAL_ICACHE_LOCK(_base_, _size_) // Undo a previous lock operation @@ -200,6 +292,5 @@ // Invalidate cache lines in the given range without writing to memory. //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) -//----------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_CACHE_H // End of hal_cache.h
--- a/packages/hal/arm/aeb/current/include/hal_platform_setup.h +++ b/packages/hal/arm/aeb/current/include/hal_platform_setup.h @@ -43,14 +43,33 @@ // //===========================================================================*/ +// From <cyg/hal/hal_cache.h> Need to make that file assembly safe. +#define CYG_DEVICE_CCR 0xFFFFA400 +#define CCR_I 0x08 // Invalidate mode + #if CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE==4096 // Override default to a more sensible value #undef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048 #endif +#ifdef CYGHWR_HAL_ARM_AEB_REVISION_C +// AEB rev C has 256kB of memory. Cache is working (set cachable) +#define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00048000,0x00007c04 +#define AEB_BAD .long 0xFFFFA00C,0x00048000,0x01000000,0x00000000 +#else +// AEB rev B has 128kB of memory. Cache is broken (clear cachable) +#define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00028000,0x00007804 +#define AEB_BAD .long 0xFFFFA00C,0x00028000,0x01000000,0x00000000 +#endif + #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS #define PLATFORM_SETUP1 \ + ldr r1,=CYG_DEVICE_CCR ;\ + mov r2,#CCR_I ;\ + strb r2,[r1,#0] /* invalidate... */ ;\ + mov r2,#0 ;\ + strb r2,[r1,#0] /* and disable the cache. */ ;\ ldr r1,=segment_register_setups ;\ 10: ldr r2,[r1,#0] /* segment address */ ;\ cmp r2,#0 ;\ @@ -64,8 +83,8 @@ 10: ldr r2,[r1,#0] /* segment address */ add r1,r1,#16 /* next segment */ ;\ b 10b ;\ segment_register_setups: ;\ - .long 0xFFFFA008,0x00008000,0x00028000,0x00007804 /* segment 2 */ ;\ - .long 0xFFFFA00C,0x00028000,0x01000000,0x00000000 /* segment 3 */ ;\ + AEB_SRAM /* segment 2 */ ;\ + AEB_BAD /* segment 3 */ ;\ .long 0 ;\ 20: #else
--- a/packages/hal/arm/aeb/current/include/pkgconf/hal_arm_aeb.h +++ b/packages/hal/arm/aeb/current/include/pkgconf/hal_arm_aeb.h @@ -82,6 +82,13 @@ #define CYGNUM_HAL_RTC_DENOMINATOR 100 #define CYGNUM_HAL_RTC_PERIOD (240000/16) +// Board revision +#ifdef CYG_HAL_ARM_AEBC +#define CYGHWR_HAL_ARM_AEB_REVISION_C +#else +#define CYGHWR_HAL_ARM_AEB_REVISION_B +#endif + /* -------------------------------------------------------------------*/ #endif /* CYGONCE_PKGCONF_HAL_ARM_AEB_H */ /* EOF hal_arm_aeb.h */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aeb/current/include/pkgconf/mlt_arm_aebC_ram.ldi @@ -0,0 +1,47 @@ +//=========================================================================== +// +// MLT linker script export +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + ram : ORIGIN = 0xc000, LENGTH = 0x3c000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0xc000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aeb/current/include/pkgconf/mlt_arm_aebC_ram.mlt @@ -0,0 +1,11 @@ +version 0 +region ram c000 3c000 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 c000 c000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 1 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aeb/current/include/pkgconf/mlt_arm_aebC_rom.ldi @@ -0,0 +1,48 @@ +//=========================================================================== +// +// MLT linker script export +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + rom : ORIGIN = 0x04018000, LENGTH = 0x08000 + ram : ORIGIN = 0x00008000, LENGTH = 0x40000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x4018000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aeb/current/include/pkgconf/mlt_arm_aebC_rom.mlt @@ -0,0 +1,12 @@ +version 0 +region ram 8000 40000 0 ! +region rom 4018000 8000 1 ! +section data 0 1 1 1 1 1 0 0 8000 bss ! +section bss 0 4 0 1 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 4018000 4018000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aeb/current/include/pkgconf/mlt_arm_aebC_stubs.ldi @@ -0,0 +1,48 @@ +//=========================================================================== +// +// MLT linker script export +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + ram : ORIGIN = 0x8000, LENGTH = 0x4000 + rom : ORIGIN = 0x4018000, LENGTH = 0x8000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x4018000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aeb/current/include/pkgconf/mlt_arm_aebC_stubs.mlt @@ -0,0 +1,12 @@ +version 0 +region ram 8000 4000 0 ! +region rom 4018000 8000 1 ! +section data 0 1 1 1 1 1 0 0 8000 bss ! +section bss 0 4 0 1 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 4018000 4018000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data !
--- a/packages/hal/arm/aeb/current/src/aeb_misc.c +++ b/packages/hal/arm/aeb/current/src/aeb_misc.c @@ -278,9 +278,9 @@ void hal_hardware_init(void) ICTL_ICR1_CH8_HL_AL); HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, 0xFFFF); // CLear all interrupts HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, 0x0000); // All disabled - // Clear and initialize instruction cache - HAL_ICACHE_INVALIDATE_ALL(); - HAL_ICACHE_ENABLE(); + // Clear and initialize cache + HAL_UCACHE_INVALIDATE_ALL(); + HAL_UCACHE_ENABLE(); } //
--- a/packages/hal/i386/linux/current/ChangeLog +++ b/packages/hal/i386/linux/current/ChangeLog @@ -1,3 +1,12 @@ +1999-10-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/linux_misc.c: Fix some really minor spelling typos + + * src/hal_diag.c (hal_diag_read_char): Check if we were woken up by + the itimer alarm (which is used for rescheduling) - in which case + just read again. + + 1999-10-05 Jesper Skov <jskov@cygnus.co.uk> * include/pkgconf/hal_i386_linux.h: Changed to use REAL TIME as
--- a/packages/hal/i386/linux/current/src/hal_diag.c +++ b/packages/hal/i386/linux/current/src/hal_diag.c @@ -69,9 +69,21 @@ void hal_diag_write_char(char __c) } } +// Hmm... we need the definition of EINTR, which normally lives in +// <asm/errno.h> on linux. But we can't get at that here, so we just +// hard-code it. The burden of binary compatibility means x86 linux will +// never change it. +#define x86_linux_EINTR 4 + void hal_diag_read_char(char *c) { - cyg_hal_sys_read(0, c, 1); + int rc; + + // The read syscall will get woken up by the itimer alarm, but we don't + // want to stop reading if that's the case + do { + rc = cyg_hal_sys_read(0, c, 1); + } while (-x86_linux_EINTR == rc); } //-----------------------------------------------------------------------------
--- a/packages/hal/i386/linux/current/src/linux_misc.c +++ b/packages/hal/i386/linux/current/src/linux_misc.c @@ -46,19 +46,19 @@ # include <pkgconf/kernel.h> #endif -// This in not correct, but it will do. +// This is not correct, but it will do. externC int cyg_hal_sys__newselect(int,int,int,int,int); // Here we define an action to do in the idle thread. For the -// synthetic architecture it makes no sence to spin eating processor +// synthetic architecture it makes no sense to spin eating processor // time that other processes could make use of. Instead we call -// select. The itimer will still go off and kick the schedular back +// select. The itimer will still go off and kick the scheduler back // into life so giving up an escape path from the select. There is one -// catch 22. This only works if we are using the real time clock for +// catch-22: this only works if we are using the real time clock for // itimer, not the virtual clock. The virtual clock works on time the -// process actually uses. When its sitting in the select it does not +// process actually uses. When it's sitting in the select it does not // use any time, so the timer does not expire! Also we don't do a -// select when the THREAD_YIELD optin is in use since we want the +// select when the THREAD_YIELD option is in use since we want the // yield to be called regularly. void
--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -1,3 +1,8 @@ +1999-10-05 Nick Garnett <nickg@cygnus.co.uk> + + * include/basetype.h: Made definition of CYG_BYTEORDER dependent + on definition of CYGPKG_HAL_MIPS_[L|M]SBFIRST. + 1999-09-17 Jonathan Larmour <jlarmour@cygnus.co.uk> * src/vectors.S (__default_exception_vsr):
--- a/packages/hal/mips/arch/current/include/basetype.h +++ b/packages/hal/mips/arch/current/include/basetype.h @@ -46,9 +46,12 @@ //----------------------------------------------------------------------------- // Characterize the architecture -#if 0 +#if defined(CYGPKG_HAL_MIPS_MSBFIRST) +# define CYG_BYTEORDER CYG_MSBFIRST // Little endian +#elif defined(CYGPKG_HAL_MIPS_LSBFIRST) +# define CYG_BYTEORDER CYG_LSBFIRST // Big endian #else -# define CYG_BYTEORDER CYG_MSBFIRST // Big endian +# error MIPS endianess not defined by configuration #endif //-----------------------------------------------------------------------------
--- a/packages/hal/mips/tx39/current/ChangeLog +++ b/packages/hal/mips/tx39/current/ChangeLog @@ -1,3 +1,12 @@ +1999-10-06 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: Don't create extras.o here any more + +1999-10-05 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/hal_mips_tx39.h: Added define of + CYGPKG_HAL_MIPS_MSBFIRST. + 1999-09-17 Jonathan Larmour <jlarmour@cygnus.co.uk> * src/hal_diag.c: Only avoid SERIAL0 if CYG_HAL_USE_ROM_MONITOR_CYGMON
--- a/packages/hal/mips/tx39/current/include/pkgconf/hal_mips_tx39.h +++ b/packages/hal/mips/tx39/current/include/pkgconf/hal_mips_tx39.h @@ -75,6 +75,14 @@ #define CYGPKG_HAL_MIPS_TX3904 +/* ------------------------------------------------------------------- + * Characterize the CPU so that the generic architecture part can + * configure itself. + */ + +#undef CYGHWR_HAL_MIPS_FPU /* We have no FPU */ +#define CYGPKG_HAL_MIPS_MSBFIRST /* Big-endian CPU */ + /* -------------------------------------------------------------------*/ /* Workaround for TX3904 Timer TRR register problem */ /* */
--- a/packages/hal/mips/tx39/current/src/PKGconf.mak +++ b/packages/hal/mips/tx39/current/src/PKGconf.mak @@ -44,13 +44,8 @@ include $(COMPONENT_REPOSITORY)/pkgconf/ EXTRAS = $(wildcard $(PREFIX)/lib/libextras.a) -ldscript.stamp: mips_tx39.ld $(EXTRAS) -ifneq ($(EXTRAS),) - $(LD) --whole-archive $(PREFIX)/lib/libextras.a -r -o $(PREFIX)/lib/extras.o - $(CC) -E -P -Wp,-MD,ldscript.tmp -DEXTRAS=$(EXTRAS) -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< -else - $(CC) -E -P -Wp,-MD,ldscript.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< -endif +ldscript.stamp: mips_tx39.ld + $(CC) -E -P -Wp,-MD,ldscript.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< @echo > ldscript.d @echo $@ ':' $< '\' >> ldscript.d @tail -n +2 ldscript.tmp >> ldscript.d
--- a/packages/hal/mn10300/am31/current/ChangeLog +++ b/packages/hal/mn10300/am31/current/ChangeLog @@ -1,3 +1,7 @@ +1999-10-06 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: Don't create extras.o here any more + 1999-09-10 Jonathan Larmour <jlarmour@cygnus.co.uk> * src/var_misc.c (cyg_hal_dcache_store): Condition on
--- a/packages/hal/mn10300/am31/current/src/PKGconf.mak +++ b/packages/hal/mn10300/am31/current/src/PKGconf.mak @@ -44,13 +44,8 @@ include $(COMPONENT_REPOSITORY)/pkgconf/ EXTRAS = $(wildcard $(PREFIX)/lib/libextras.a) -ldscript.stamp: mn10300_am31.ld $(EXTRAS) -ifneq ($(EXTRAS),) - $(LD) -EL --whole-archive $(PREFIX)/lib/libextras.a -r -o $(PREFIX)/lib/extras.o - $(CC) -E -P -Wp,-MD,ldscript.tmp -DEXTRAS=$(EXTRAS) -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< -else - $(CC) -E -P -Wp,-MD,ldscript.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< -endif +ldscript.stamp: mn10300_am31.ld + $(CC) -E -P -Wp,-MD,ldscript.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< @echo > ldscript.d @echo $@ ':' $< '\' >> ldscript.d @tail -n +2 ldscript.tmp >> ldscript.d
--- a/packages/io/serial/current/ChangeLog +++ b/packages/io/serial/current/ChangeLog @@ -1,3 +1,7 @@ +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + 1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct
--- a/packages/io/serial/current/tests/ser_test_protocol.inl +++ b/packages/io/serial/current/tests/ser_test_protocol.inl @@ -94,8 +94,8 @@ # define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY0_DEV # endif #endif -#if defined(CYGPKG_HAL_ARM_AEB) \ - && defined(CYGPKG_IO_SERIAL_ARM_AEB) \ +#if defined(CYGPKG_HAL_ARM_AEB) || defined(CYGPKG_HAL_ARM_AEBC) \ + && defined(CYGPKG_IO_SERIAL_ARM_AEB) \ && defined(CYGPKG_IO_SERIAL_ARM_AEB_SERIAL1) # define TEST_CRASH_ID "armaeb" # define TEST_SER_DEV CYGDAT_IO_SERIAL_ARM_AEB_SERIAL1_NAME
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -1,3 +1,8 @@ + +1999-10-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/kcache1.c: Reduced memory footprint. + 1999-09-25 Jesper Skov <jskov@cygnus.co.uk> * tests/stress_threads.c: Added date header and flush() calls.
--- a/packages/kernel/current/tests/kcache1.c +++ b/packages/kernel/current/tests/kcache1.c @@ -30,7 +30,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): dsm -// Contributors: dsm, nickg +// Contributors: dsm, nickg // Date: 1998-06-18 //####DESCRIPTIONEND#### */ @@ -51,11 +51,12 @@ // ------------------------------------------------------------------------- // If the HAL does not supply this, we supply our own version -#ifdef HAL_DCACHE_SYNC +#ifndef HAL_DCACHE_PURGE_ALL +# ifdef HAL_DCACHE_SYNC -# define HAL_DCACHE_PURGE_ALL() HAL_DCACHE_SYNC() +#define HAL_DCACHE_PURGE_ALL() HAL_DCACHE_SYNC() -#else +# else static cyg_uint8 dca[HAL_DCACHE_SIZE + HAL_DCACHE_LINE_SIZE*2]; @@ -70,6 +71,7 @@ CYG_MACRO_START } \ CYG_MACRO_END +# endif #endif // ------------------------------------------------------------------------- @@ -82,14 +84,12 @@ static cyg_handle_t thread[NTHREADS]; static cyg_thread thread_obj[NTHREADS]; static char stack[NTHREADS][STACKSIZE]; -#define MAXSIZE 1<<18 - -volatile char m[MAXSIZE]; - #ifndef MAX_STRIDE #define MAX_STRIDE 64 #endif +volatile char m[(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE)*MAX_STRIDE+1]; + // ------------------------------------------------------------------------- static void time0(register cyg_uint32 stride)
--- a/packages/language/c/libc/current/ChangeLog +++ b/packages/language/c/libc/current/ChangeLog @@ -1,3 +1,18 @@ +1999-10-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/libc.h: Add CYGSEM_LIBC_MAIN_STACK_FROM_SYSTEM to allow + the user to supply their own stack. + Rename CYGNUM_LIBC_MAIN_STACK_SIZE to + CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE and reparent under + CYGSEM_LIBC_MAIN_STACK_FROM_SYSTEM + Add CYGNUM_LIBC_MAIN_THREAD_PRIORITY to provide main() thread + priority + + * src/support/mainthread.cxx: Add support for user-supplied stack + Allow user to specify thread priority + + These changes fix CR 101069 + 1999-10-01 Jonathan Larmour <jlarmour@cygnus.co.uk> * include/pkgconf/libc.h (CYGDAT_LIBC_STDIO_DEFAULT_CONSOLE): Change
--- a/packages/language/c/libc/current/include/pkgconf/libc.h +++ b/packages/language/c/libc/current/include/pkgconf/libc.h @@ -1041,8 +1041,24 @@ parent CYGPKG_LIBC_STARTUP } - cdl_option CYGNUM_LIBC_MAIN_STACK_SIZE { - display "main()'s thread stack size" + cdl_component CYGSEM_LIBC_MAIN_STACK_FROM_SYSTEM { + display "System provides stack for main()'s thread" + description "This option controls whether the stack of + main()'s thread is provided by the application or + provided by the system. When disabled, the + application must declare a pointer variable + cyg_libc_main_stack which is a pointer to an + appropriately aligned region of memory. The + application must also declare a variable of + type `int' called cyg_libc_main_stack_size + which contains the size of the stack in bytes. + This must be a multiple of 8." + type boolean + parent CYGSEM_LIBC_STARTUP_MAIN_THREAD + } + + cdl_option CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE { + display "main()'s default thread stack size" description "With an eCos kernel, when the cyg_iso_c_start() function is used to invoke the user-supplied main() function in an ISO C compatible fashion, @@ -1055,7 +1071,20 @@ etc." type count legal_values 16 to 0x7fffffff - parent CYGSEM_LIBC_STARTUP_MAIN_THREAD + parent CYGSEM_LIBC_MAIN_STACK_FROM_SYSTEM + } + + cdl_option CYGNUM_LIBC_MAIN_THREAD_PRIORITY { + display "Priority of main()'s thread" + description "This option is used to provide the thread + priority which main()'s thread runs at. Be + sure to check that this number is appropriate + for the kernel scheduler chosen. Different + kernel schedulers impose different restrictions + on the usable priorities." + type count + legal_values 0 to 0x7fffffff + parent CYGSEM_LIBC_STARTUP_MAIN_THREAD } cdl_component CYGFUN_LIBC_ATEXIT { @@ -1158,7 +1187,9 @@ #define CYGSEM_LIBC_STARTUP_MAIN_THREAD #ifdef CYGSEM_LIBC_STARTUP_MAIN_THREAD -#define CYGNUM_LIBC_MAIN_STACK_SIZE 8192 +# define CYGSEM_LIBC_MAIN_STACK_FROM_SYSTEM +# define CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE 8192 +# define CYGNUM_LIBC_MAIN_THREAD_PRIORITY 16 #endif #define CYGFUN_LIBC_ATEXIT
--- a/packages/language/c/libc/current/src/support/mainthread.cxx +++ b/packages/language/c/libc/current/src/support/mainthread.cxx @@ -93,29 +93,40 @@ static cyg_libc_dummy_constructor_class CYG_INIT_PRIORITY(PREDEFAULT); #endif +#ifdef CYGSEM_LIBC_MAIN_STACK_FROM_SYSTEM + // override stack size on some platforms #ifdef CYGNUM_HAL_STACK_SIZE_TYPICAL -# if CYGNUM_LIBC_MAIN_STACK_SIZE < CYGNUM_HAL_STACK_SIZE_TYPICAL -# undef CYGNUM_LIBC_MAIN_STACK_SIZE -# define CYGNUM_LIBC_MAIN_STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL +# if CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE < CYGNUM_HAL_STACK_SIZE_TYPICAL +# undef CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE +# define CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL # endif #endif -// Make this weak so that users can override this from their own code -// if they really want. FIXME: but its still allocated -cyg_uint8 cyg_libc_main_stack[ CYGNUM_LIBC_MAIN_STACK_SIZE ] - CYGBLD_ATTRIB_WEAK; +static cyg_uint8 cyg_libc_main_stack[ CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE ]; + +#else // !ifdef CYGSEM_LIBC_MAIN_STACK_FROM_SYSTEM + +extern char *cyg_libc_main_stack; +extern int cyg_libc_main_stack_size; + +#endif // !ifdef CYGSEM_LIBC_MAIN_STACK_FROM_SYSTEM // GLOBALS // let the main thread be global so people can play with it (e.g. suspend // or resume etc.) if that's what they want to do -Cyg_Thread cyg_libc_main_thread CYGBLD_ATTRIB_WEAK CYG_INIT_PRIORITY(LIBC) = - Cyg_Thread(CYG_SCHED_DEFAULT_INFO, +Cyg_Thread cyg_libc_main_thread CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_LIBC) = + Cyg_Thread(CYGNUM_LIBC_MAIN_THREAD_PRIORITY, &cyg_libc_invoke_main, (CYG_ADDRWORD) 0, "main", - (CYG_ADDRESS) &cyg_libc_main_stack, - CYGNUM_LIBC_MAIN_STACK_SIZE); + (CYG_ADDRESS) &cyg_libc_main_stack[0], +#ifdef CYGSEM_LIBC_MAIN_STACK_FROM_SYSTEM + CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE +#else + cyg_libc_main_stack_size +#endif + ); #endif // ifdef CYGSEM_LIBC_STARTUP_MAIN_THREAD
--- a/packages/pkgconf.tcl +++ b/packages/pkgconf.tcl @@ -1312,10 +1312,6 @@ According to the packages file this pack continue } - if { $pkgconf::target_data($target,prefix) == "" } { - fatal_error "The targets file $filename does not list a command prefix for the $target architecture." - } - foreach platform $pkgconf::target_data($target,known_platforms) { if { [llength $pkgconf::target_data($target,$platform,startup)] == 0 } { fatal_error \ @@ -5488,7 +5484,10 @@ proc pkgconf::produce_misc_files { } { } else { set command_prefix $pkgconf::target_data($pkgconf::config_data(target),prefix) } - + if {"" != $command_prefix} { + set command_prefix "${command_prefix}-" + } + puts $file "" puts $file "COMPONENT_REPOSITORY\t\t:= [get_pathname_for_make $pkgconf::component_repository]" puts $file "BUILD_TREE\t\t\t:= [get_pathname_for_make $pkgconf::build_tree]" @@ -5511,11 +5510,11 @@ proc pkgconf::produce_misc_files { } { puts $file "EXEEXT\t\t\t\t:= .exe" } puts $file "" - puts $file "PKGCONF_CC\t\t\t:= $command_prefix-gcc" - puts $file "PKGCONF_CXX\t\t\t:= $command_prefix-gcc" - puts $file "PKGCONF_AR\t\t\t:= $command_prefix-ar" - puts $file "PKGCONF_LD\t\t\t:= $command_prefix-ld" - puts $file "PKGCONF_OBJCOPY\t\t\t:= $command_prefix-objcopy" + puts $file "PKGCONF_CC\t\t\t:= ${command_prefix}gcc" + puts $file "PKGCONF_CXX\t\t\t:= ${command_prefix}gcc" + puts $file "PKGCONF_AR\t\t\t:= ${command_prefix}ar" + puts $file "PKGCONF_LD\t\t\t:= ${command_prefix}ld" + puts $file "PKGCONF_OBJCOPY\t\t\t:= ${command_prefix}objcopy" puts $file "" foreach flag $pkgconf::known_compiler_flags {
--- a/packages/targets +++ b/packages/targets @@ -248,6 +248,23 @@ target arm { LDLANGFLAGS "-Wl,--gc-sections -Wl,-static" } } + platform aebC { + alias { "ARM Eval Board (AEB) rev C" } + startup { ram rom stubs } + packages { + CYGPKG_HAL_ARM_AEB + } + base_platform aeb + cflags { + ARCHFLAGS "-mcpu=arm7di" + ERRFLAGS "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef" + CXXERRFLAGS "-Woverloaded-virtual" + DBGFLAGS "-g -O2" + LANGFLAGS "-ffunction-sections -fdata-sections" + CXXLANGFLAGS "-fno-rtti -fno-exceptions -fvtable-gc -finit-priority" + LDLANGFLAGS "-Wl,--gc-sections -Wl,-static" + } + } platform cl7111 { alias { "Cirrus Logic Eval Board (CL7111)" } startup { ram rom stubs }