ecos-v3_0-branch: packages/hal/mips/arch/current/include/hal

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 2863:7d8c61e6225c default tip

* Added execute permissions to files missed in conversion from CVS

author	alexs
date	Thu, 26 Mar 2009 20:39:18 +0000
parents	74dbf4c3f2e1
children

rev	line source
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1 #ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 #define CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	6 // hal_cache.h
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	7 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	8 // HAL cache control API
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 //=============================================================================
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	11 // ####ECOSGPLCOPYRIGHTBEGIN####
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	12 // -------------------------------------------
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	13 // This file is part of eCos, the Embedded Configurable Operating System.
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	15 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	16 // eCos is free software; you can redistribute it and/or modify it under
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	17 // the terms of the GNU General Public License as published by the Free
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	18 // Software Foundation; either version 2 or (at your option) any later
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	19 // version.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	20 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	21 // eCos is distributed in the hope that it will be useful, but WITHOUT
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	24 // for more details.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	25 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	26 // You should have received a copy of the GNU General Public License
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	29 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	30 // As a special exception, if other files instantiate templates or use
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	31 // macros or inline functions from this file, or you compile this file
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	32 // and link it with other works to produce a work based on this file,
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	33 // this file does not by itself cause the resulting work to be covered by
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	34 // the GNU General Public License. However the source code for this file
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	35 // must still be made available in accordance with section (3) of the GNU
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	36 // General Public License v2.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	37 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	38 // This exception does not invalidate any other reasons why a work based
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	39 // on this file might be covered by the GNU General Public License.
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	40 // -------------------------------------------
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 1656 diff changeset	41 // ####ECOSGPLCOPYRIGHTEND####
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	42 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	43 //#####DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	44 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	45 // Author(s): nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	46 // Contributors: nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	47 // Date: 1998-02-17
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	48 // Purpose: Cache control API
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	49 // Description: The macros defined here provide the HAL APIs for handling
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	50 // cache control operations.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	51 // Usage:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	52 // #include <cyg/hal/hal_cache.h>
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	53 // ...
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	54 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	55 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	56 //####DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	57 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	58 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	59
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	60 #include <pkgconf/hal.h>
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	61 #include <cyg/infra/cyg_type.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	62
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	63 #include <cyg/hal/var_cache.h>
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	64
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	65 // Use this macro to allow the assembler to accept "cache" instructions,
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	66 // which are MIPS ISA 3. This is useful if someone is compiling
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	67 // with -mips2, but the architecture is really MIPS ISA 3.
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	68
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	69 #define _hal_asm_mips_cpp_stringize( _x_ ) #_x_
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	70 #define _HAL_ASM_SET_MIPS_ISA( _isal_ ) asm volatile ( \
121 6bd9d475ed4b Merge from eCos master repository on 2000-09-04-20:50:20-BST jlarmour parents: 92 diff changeset	71 ".set mips" _hal_asm_mips_cpp_stringize(_isal_) )
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	72
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	73
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	74 //=============================================================================
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	75 // Default Implementation. This uses the standard MIPS CP0 registers and
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	76 // cache instructions. Note that not all variants will have all of the
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	77 // functionality defined here.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	78
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	79 //-----------------------------------------------------------------------------
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	80 // Cache dimensions.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	81 // These really should be defined in var_cache.h. If they are not, then provide
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	82 // a set of numbers that are typical of many variants.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	83
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	84 #ifndef HAL_DCACHE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	85
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	86 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	87 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	88 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	89 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	90
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	91 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	92 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	93 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	94 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	95
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	96 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	97 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	98
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	99 #endif
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	100
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	101 // Defines for various R4000+ MIPS cache operations
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	102 // this is a 5 bit field with bits 4-2 defining the operation
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	103 // and bits 1-0 defining which cache is being operated on
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	104 #define HAL_MIPS_CACHE_INDEX_INVALIDATE_I 0x00 /* 0 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	105 #define HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_D 0x01 /* 0 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	106 #define HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_S 0x03 /* 0 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	107 #define HAL_MIPS_CACHE_INDEX_LOAD_TAG_I 0x04 /* 1 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	108 #define HAL_MIPS_CACHE_INDEX_LOAD_TAG_D 0x05 /* 1 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	109 #define HAL_MIPS_CACHE_INDEX_LOAD_TAG_S 0x07 /* 1 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	110 #define HAL_MIPS_CACHE_INDEX_STORE_TAG_I 0x08 /* 2 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	111 #define HAL_MIPS_CACHE_INDEX_STORE_TAG_D 0x09 /* 2 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	112 #define HAL_MIPS_CACHE_INDEX_STORE_TAG_S 0x0b /* 2 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	113 #define HAL_MIPS_CACHE_HIT_INVALIDATE_I 0x10 /* 4 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	114 #define HAL_MIPS_CACHE_HIT_INVALIDATE_D 0x11 /* 4 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	115 #define HAL_MIPS_CACHE_HIT_INVALIDATE_S 0x13 /* 4 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	116 #define HAL_MIPS_CACHE_FILL_I 0x14 /* 5 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	117 #define HAL_MIPS_CACHE_HIT_WRITEBACK_INV_D 0x15 /* 5 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	118 #define HAL_MIPS_CACHE_HIT_WRITEBACK_INV_S 0x17 /* 5 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	119
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	120 // there seems to be different uses for operation
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	121 // code 6 depending on CPU
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	122 #define HAL_MIPS_CACHE_HIT_WRITEBACK_D 0x19 /* 6 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	123
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	124 #define HAL_MIPS_CACHE_INDEX_LOAD_DATA_I 0x18 /* 6 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	125 #define HAL_MIPS_CACHE_INDEX_LOAD_DATA_D 0x19 /* 6 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	126 #define HAL_MIPS_CACHE_INDEX_LOAD_DATA_S 0x1b /* 6 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	127
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	128 // there seems to be different uses for operation
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	129 // code 7 depending on CPU
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	130 #define HAL_MIPS_CACHE_FETCH_AND_LOCK_I 0x1c /* 7 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	131 #define HAL_MIPS_CACHE_FETCH_AND_LOCK_D 0x1d /* 7 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	132
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	133 #define HAL_MIPS_CACHE_INDEX_STORE_DATA_I 0x1c /* 7 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	134 #define HAL_MIPS_CACHE_INDEX_STORE_DATA_D 0x1d /* 7 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	135 #define HAL_MIPS_CACHE_INDEX_STORE_DATA_S 0x1f /* 7 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	136
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	137
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	138 //-----------------------------------------------------------------------------
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	139 // Cache instruction uses LSBs or MSBs (depending on the
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	140 // implementation) of the virtual address to specify which WAY to
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	141 // affect. The _ALL_WAYS macro defines the necessary cache instructions
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	142 // to affect all ways.
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	143
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	144 #ifdef HAL_MIPS_CACHE_INSN_USES_LSB
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	145 # define _IWAY(_n_) (_n_)
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	146 # define _DWAY(_n_) (_n_)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	147 #else
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	148 # define _IWAY(_n_) ((_n_)*HAL_ICACHE_SIZE/HAL_ICACHE_WAYS)
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	149 # define _DWAY(_n_) ((_n_)*HAL_DCACHE_SIZE/HAL_DCACHE_WAYS)
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	150 #endif
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	151
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	152 #if (HAL_DCACHE_WAYS == 1)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	153 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	154 asm volatile ("cache %0,0(%1);" \
124 0ec04793409a Merge from eCos master repository on 2000-09-11-03:00:13-BST jlarmour parents: 121 diff changeset	155 : : "I" ((_cmd_) \| 1), "r"(_addr_) )
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	156 #elif (HAL_DCACHE_WAYS == 2)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	157 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	158 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	159 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	160 : : "I" ((_cmd_) \| 1), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	161 "I" (_DWAY(1)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	162 #elif (HAL_DCACHE_WAYS == 4)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	163 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	164 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	165 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	166 "cache %0,%3(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	167 "cache %0,%4(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	168 : : "I" ((_cmd_) \| 1), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	169 "I" (_DWAY(1)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	170 "I" (_DWAY(2)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	171 "I" (_DWAY(3)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	172 #else
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	173 # error "Unsupported number of ways"
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	174 #endif
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	175
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	176 #if (HAL_ICACHE_WAYS == 1)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	177 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	178 asm volatile ("cache %0,0(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	179 : : "I" (_cmd_), "r"(_addr_) )
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	180 #elif (HAL_ICACHE_WAYS == 2)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	181 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	182 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	183 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	184 : : "I" (_cmd_), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	185 "I" (_IWAY(1)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	186 #elif (HAL_ICACHE_WAYS == 4)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	187 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	188 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	189 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	190 "cache %0,%3(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	191 "cache %0,%4(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	192 : : "I" (_cmd_), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	193 "I" (_IWAY(1)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	194 "I" (_IWAY(2)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	195 "I" (_IWAY(3)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	196 #else
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	197 # error "Unsupported number of ways"
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	198 #endif
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	199
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	200 //-----------------------------------------------------------------------------
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	201 // Address adjustment.
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	202 // Given an address and a size, these macros return the first
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	203 // cacheline containing the requested range and a terminating address.
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	204
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	205 #define HAL_DCACHE_START_ADDRESS(_addr_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	206 (((CYG_ADDRESS)(_addr_)) & ~(HAL_DCACHE_LINE_SIZE-1))
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	207
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	208 #define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	209 ((CYG_ADDRESS)((_addr_) + (_asize_)))
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	210
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	211 #define HAL_ICACHE_START_ADDRESS(_addr_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	212 (((CYG_ADDRESS)(_addr_)) & ~(HAL_ICACHE_LINE_SIZE-1))
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	213
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	214 #define HAL_ICACHE_END_ADDRESS(_addr_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	215 ((CYG_ADDRESS)((_addr_) + (_asize_)))
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	216
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	217 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	218 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	219
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	220 // Enable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	221 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	222 #ifndef HAL_DCACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	223 #define HAL_DCACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	224 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	225
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	226 // Disable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	227 #ifndef HAL_DCACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	228 #define HAL_DCACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	229 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	230
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	231 #ifndef HAL_DCACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	232 #define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	233 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	234
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	235 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	236 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	237 // is not quite what we want, but there is no index-invalidate operation
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	238 // available.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	239 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	240 #define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	241 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	242
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	243 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	244 // This uses the index-writeback-invalidate operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	245 #ifndef HAL_DCACHE_SYNC_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	246 #define HAL_DCACHE_SYNC() \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	247 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	248 register CYG_ADDRESS _baddr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	249 register CYG_ADDRESS _addr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	250 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	251 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	252 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	253 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_D, _addr_); } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	254 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	255 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	256 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	257
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	258 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	259 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	260
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	261 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	262 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	263
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	264 //#define HAL_DCACHE_WRITETHRU_MODE 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	265 //#define HAL_DCACHE_WRITEBACK_MODE 1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	266
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	267 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	268 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	269 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	270 #ifndef HAL_DCACHE_LOCK_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	271 #define HAL_DCACHE_LOCK(_base_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	272 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	273 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	274 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	275 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	276 HAL_DCACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	277 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	278 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	279 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	280 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_FETCH_AND_LOCK_D, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	281 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	282 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	283 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	284 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	285
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	286 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	287 // Do this by flushing the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	288 #ifndef HAL_DCACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	289 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	290 HAL_DCACHE_FLUSH( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	291 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	292
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	293 // Unlock entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	294 #ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	295 #define HAL_DCACHE_UNLOCK_ALL() \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	296 HAL_DCACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	297 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	298
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	299 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	300 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	301
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	302 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	303 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	304 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	305
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	306 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	307 // for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	308 // This uses the hit-writeback-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	309 #ifndef HAL_DCACHE_FLUSH_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	310 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	311 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	312 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	313 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	314 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	315 HAL_DCACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	316 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	317 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	318 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	319 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_WRITEBACK_INV_D, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	320 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	321 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	322 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	323 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	324
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	325 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	326 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	327 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	328 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	329 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	330 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	331 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	332 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	333 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	334 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_INVALIDATE_D, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	335 _HAL_ASM_SET_MIPS_ISA(0); \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	336 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	337 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	338
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	339 // Write dirty cache lines to memory for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	340 // This uses the hit-writeback cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	341 #ifndef HAL_DCACHE_STORE_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	342 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	343 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	344 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	345 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	346 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	347 HAL_DCACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	348 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	349 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	350 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	351 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_WRITEBACK_D, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	352 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	353 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	354 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	355 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	356
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	357 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	358 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	359 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	360
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	361 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	362 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	363 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	364
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	365 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	366 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	367
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	368 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	369 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	370
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	371 // Enable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	372 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	373 #ifndef HAL_ICACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	374 #define HAL_ICACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	375 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	376
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	377 // Disable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	378 #ifndef HAL_ICACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	379 #define HAL_ICACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	380 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	381
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	382 #ifndef HAL_ICACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	383 #define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	384 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	385
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	386 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	387 // This uses the index-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	388 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	389 #define HAL_ICACHE_INVALIDATE_ALL() \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	390 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	391 register CYG_ADDRESS _baddr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	392 register CYG_ADDRESS _addr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	393 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	394 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	395 { _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_INDEX_INVALIDATE_I, _addr_); } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	396 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	397 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	398 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	399
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	400 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	401 // Simply force the cache to reload.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	402 #ifndef HAL_ICACHE_SYNC_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	403 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	404 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	405
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	406 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	407 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	408
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	409 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	410 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	411 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	412 #ifndef HAL_ICACHE_LOCK_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	413 #define HAL_ICACHE_LOCK(_base_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	414 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	415 register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	416 register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	417 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	418 HAL_ICACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	419 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	420 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	421 for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	422 { _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_FETCH_AND_LOCK_I, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	423 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	424 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	425 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	426 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	427
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	428 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	429 // Do this by invalidating the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	430 #ifndef HAL_ICACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	431 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	432 HAL_ICACHE_INVALIDATE( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	433 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	434
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	435 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	436 //#define HAL_ICACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	437
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	438 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	439 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	440
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	441 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	442 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	443 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	444 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	445 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	446 register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	447 register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	448 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	449 for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	450 { _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_INVALIDATE_I, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	451 _HAL_ASM_SET_MIPS_ISA(0); \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	452 CYG_MACRO_END
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	453 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	454
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	455 //-----------------------------------------------------------------------------
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	456 // Check that a supported configuration has actually defined some macros.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	457
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	458 #ifndef HAL_DCACHE_ENABLE
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	459
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	460 #error Unsupported MIPS configuration
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	461
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	462 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	463
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	464 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	465 #endif // ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	466 // End of hal_cache.h

Mercurial > ecos-v3_0-branch

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 2863:7d8c61e6225c default tip