Mercurial > ecos-v3_0-branch
annotate packages/hal/powerpc/adder/current/src/adder.S @ 2863:7d8c61e6225c default tip
* Added execute permissions to files missed in conversion from CVS
| author | alexs |
|---|---|
| date | Thu, 26 Mar 2009 20:39:18 +0000 |
| parents | 74dbf4c3f2e1 |
| children |
| rev | line source |
|---|---|
| 432 | 1 ##============================================================================= |
| 2 ## | |
| 3 ## adder.S | |
| 4 ## | |
| 5 ## ADDER board hardware setup | |
| 6 ## | |
| 7 ##============================================================================= | |
|
2729
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
8 ## ####ECOSGPLCOPYRIGHTBEGIN#### |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
9 ## ------------------------------------------- |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
10 ## This file is part of eCos, the Embedded Configurable Operating System. |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
| 432 | 12 ## |
|
2729
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
13 ## eCos is free software; you can redistribute it and/or modify it under |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
14 ## the terms of the GNU General Public License as published by the Free |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
15 ## Software Foundation; either version 2 or (at your option) any later |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
16 ## version. |
| 432 | 17 ## |
|
2729
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
18 ## eCos is distributed in the hope that it will be useful, but WITHOUT |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
19 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
21 ## for more details. |
| 432 | 22 ## |
|
2729
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
23 ## You should have received a copy of the GNU General Public License |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
24 ## along with eCos; if not, write to the Free Software Foundation, Inc., |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
25 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 432 | 26 ## |
|
2729
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
27 ## As a special exception, if other files instantiate templates or use |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
28 ## macros or inline functions from this file, or you compile this file |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
29 ## and link it with other works to produce a work based on this file, |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
30 ## this file does not by itself cause the resulting work to be covered by |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
31 ## the GNU General Public License. However the source code for this file |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
32 ## must still be made available in accordance with section (3) of the GNU |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
33 ## General Public License v2. |
| 432 | 34 ## |
|
2729
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
35 ## This exception does not invalidate any other reasons why a work based |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
36 ## on this file might be covered by the GNU General Public License. |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
37 ## ------------------------------------------- |
|
74dbf4c3f2e1
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
jlarmour
parents:
1453
diff
changeset
|
38 ## ####ECOSGPLCOPYRIGHTEND#### |
| 432 | 39 ##============================================================================= |
| 40 #######DESCRIPTIONBEGIN#### | |
| 41 ## | |
| 42 ## Author(s): hmt | |
| 43 ## Contributors:hmt, gthomas | |
| 44 ## Date: 1999-06-08 | |
| 45 ## Purpose: ADDER board hardware setup | |
| 46 ## Description: This file contains any code needed to initialize the | |
| 47 ## hardware on a ADDER PPC860 board. | |
| 48 ## | |
| 49 ######DESCRIPTIONEND#### | |
| 50 ## | |
| 51 ##============================================================================= | |
| 52 | |
| 53 #include <pkgconf/hal.h> | |
| 54 | |
| 55 #include <cyg/hal/arch.inc> /* register symbols et al */ | |
| 56 #include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */ | |
| 57 /* registers, IMM layout... */ | |
| 58 #include <cyg/hal/quicc/ppc8xx.h> /* more of the same */ | |
| 59 | |
| 60 #------------------------------------------------------------------------------ | |
| 61 # this is controlled with one define for tidiness: | |
| 62 # (and it is undefined by default) | |
| 63 | |
| 64 //#define CYGPRI_RAM_START_PROGRAMS_UPMS | |
| 65 | |
| 66 #if defined(CYG_HAL_STARTUP_ROM) \ | |
| 67 || defined(CYG_HAL_STARTUP_ROMRAM) \ | |
| 68 || defined(CYGPRI_RAM_START_PROGRAMS_UPMS) | |
| 69 # define CYGPRI_DO_PROGRAM_UPMS | |
| 70 #endif | |
| 71 | |
| 72 /* The intention is that we only set up the UPMs in ROM start, be it actual | |
| 73 * ROM application start or Stub ROMs that we built from the same sources. | |
| 74 * | |
| 75 * The alternative approach - in which we have reliability doubts - is to | |
| 76 * program the UPMs with *old* timing data in StubROM start, then | |
| 77 * *reprogram* them with *new* timing data in RAM start - and of course | |
| 78 * program with *new* timing data in plain ROM application start. | |
| 79 * (Re-programming from new to new timing data fails - hence the suspicion | |
| 80 * of reprogramming _at_all_, hence this private configuration) | |
| 81 * | |
| 82 * With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour | |
| 83 * - programming the UPMs exactly once - is obtained. Define it to get the | |
| 84 * latter, untrusted behaviour. | |
| 85 */ | |
| 86 | |
| 87 #------------------------------------------------------------------------------ | |
| 88 | |
| 89 FUNC_START( hal_hardware_init ) | |
| 90 | |
| 91 # Throughout this routine, r4 is the base address of the control | |
| 92 # registers. r3 and r5 are scratch in general. | |
| 93 | |
| 94 lwi r4,CYGARC_REG_IMM_BASE # base address of control registers | |
| 95 mtspr CYGARC_REG_IMMR,r4 | |
|
1453
0e3378e69a2a
Fix some issues with network debugging by not clearing caches on startup
gthomas
parents:
862
diff
changeset
|
96 |
|
0e3378e69a2a
Fix some issues with network debugging by not clearing caches on startup
gthomas
parents:
862
diff
changeset
|
97 #ifndef CYG_HAL_STARTUP_RAM |
|
0e3378e69a2a
Fix some issues with network debugging by not clearing caches on startup
gthomas
parents:
862
diff
changeset
|
98 |
| 432 | 99 #define CACHE_UNLOCKALL 0x0a00 |
| 100 #define CACHE_DISABLE 0x0400 | |
| 101 #define CACHE_INVALIDATEALL 0x0c00 | |
| 102 #define CACHE_ENABLE 0x0200 | |
| 103 #define CACHE_ENABLEBIT 0x8000 | |
| 104 | |
| 105 #define CACHE_FORCEWRITETHROUGH 0x0100 | |
| 106 #define CACHE_NOWRITETHROUGH 0x0300 | |
| 107 #define CACHE_CLEAR_LE_SWAP 0x0700 | |
| 108 | |
| 109 # DATA CACHE | |
| 110 mfspr r3,CYGARC_REG_DC_CST /* clear error bits */ | |
| 111 lis r3,CACHE_UNLOCKALL | |
| 112 sync | |
| 113 mtspr CYGARC_REG_DC_CST,r3 /* unlock all lines */ | |
| 114 | |
| 115 lis r3,CACHE_INVALIDATEALL | |
| 116 sync | |
| 117 mtspr CYGARC_REG_DC_CST,r3 /* invalidate all lines */ | |
| 118 | |
| 119 lis r3,CACHE_DISABLE | |
| 120 sync | |
| 121 mtspr CYGARC_REG_DC_CST,r3 /* disable */ | |
| 122 | |
| 123 lis r3,CACHE_FORCEWRITETHROUGH | |
| 124 sync | |
| 125 mtspr CYGARC_REG_DC_CST,r3 /* set force-writethrough mode */ | |
| 126 | |
| 127 lis r3,CACHE_CLEAR_LE_SWAP | |
| 128 sync | |
| 129 mtspr CYGARC_REG_DC_CST,r3 /* clear little-endian swap mode */ | |
| 130 /* (dunno what this is, but it sounds like a bad thing) */ | |
| 131 | |
| 132 # INSTRUCTION CACHE (no writeback modes) | |
| 133 mfspr r3,CYGARC_REG_IC_CST /* clear error bits */ | |
| 134 lis r3,CACHE_UNLOCKALL | |
| 135 mtspr CYGARC_REG_IC_CST,r3 /* unlock all lines */ | |
| 136 isync | |
| 137 lis r3,CACHE_INVALIDATEALL | |
| 138 mtspr CYGARC_REG_IC_CST,r3 /* invalidate all lines */ | |
| 139 isync | |
| 140 lis r3,CACHE_DISABLE | |
| 141 mtspr CYGARC_REG_IC_CST,r3 /* disable */ | |
| 142 isync | |
| 143 | |
| 144 sync | |
|
1453
0e3378e69a2a
Fix some issues with network debugging by not clearing caches on startup
gthomas
parents:
862
diff
changeset
|
145 |
|
0e3378e69a2a
Fix some issues with network debugging by not clearing caches on startup
gthomas
parents:
862
diff
changeset
|
146 #endif // ! CYG_HAL_STARTUP_RAM |
| 432 | 147 |
| 148 /* | |
| 149 * SIU Initialization. | |
| 150 */ | |
| 151 lwi r3,0x00610400 | |
| 152 stw r3,SIUMCR(r4) | |
| 153 | |
| 154 #ifdef CYG_HAL_STARTUP_ROMRAM | |
| 155 // Need to set the PC into the FLASH (ROM) before the address map changes | |
| 156 lwi r3,10f | |
| 157 lwi r5,0xFE000000 | |
| 158 or r3,r3,r5 | |
| 159 mtctr r3 | |
| 160 bctr | |
| 161 10: | |
| 162 #endif | |
| 163 | |
| 164 /* | |
| 165 * Enable bus monitor. Disable Watchdog timer. | |
| 166 */ | |
| 167 lwi r3,0xffffff88 | |
| 168 stw r3,SYPCR(r4) | |
| 169 | |
| 170 /* | |
| 171 * Clear REFA & REFB. Enable but freeze timebase. | |
| 172 */ | |
| 173 lwi r3,0x0000 // FIXME: should this be 0x0000 or 0x00C2 | |
| 174 sth r3,TBSCR(r4) | |
| 175 | |
| 176 /* | |
| 177 * Unlock some RTC registers (see section 5.11.2) | |
| 178 */ | |
| 179 lwi r3,0x55ccaa33 | |
| 180 stw r3,RTCSCK(r4) | |
| 181 stw r3,RTCK(r4) | |
| 182 stw r3,RTSECK(r4) | |
| 183 stw r3,RTCALK(r4) | |
| 184 | |
| 185 /* | |
| 186 * Clear SERC & ALR. RTC runs on freeze. Enable RTC. | |
| 187 */ | |
| 188 li r3,0x0000 // FIXME: should this be 0x0000 or 0x00C3 | |
| 189 sth r3,RTCSC(r4) | |
| 190 | |
| 191 /* | |
| 192 * Clear periodic timer interrupt status. | |
| 193 * Enable periodic timer and stop it on freeze. | |
| 194 */ | |
| 195 li r3,0x0001 // FIXME: should this be 0x0001 or 0x0083 | |
| 196 sth r3,PISCR(r4) | |
| 197 | |
| 198 #ifdef CYGPRI_DO_PROGRAM_UPMS | |
| 199 /* | |
| 200 * Perform UPM programming by writing to its 64 RAM locations. | |
| 201 * Note that UPM initialization must be done before the Bank Register | |
| 202 * initialization. Otherwise, system may hang when writing to Bank | |
| 203 * Registers in certain cases. | |
| 204 */ | |
| 205 lis r5,__upmtbl_start@h | |
| 206 ori r5,r5,__upmtbl_start@l | |
| 207 lis r6,__upmtbl_end@h | |
| 208 ori r6,r6,__upmtbl_end@l | |
| 209 sub r7,r6,r5 /* size of table */ | |
| 210 srawi r7,r7,2 /* in words */ | |
| 211 | |
| 212 li r6,0x00000000 /* Command - OP=Write, UPMA, MAD=0 */ | |
| 213 1: | |
| 214 lwz r3,0(r5) /* get data from table */ | |
| 215 stw r3,MDR(r4) /* store the data to MD register */ | |
| 216 stw r6,MCR(r4) /* issue command to MCR register */ | |
| 217 addi r5,r5,4 /* next entry in the table */ | |
| 218 addi r6,r6,1 /* next MAD address */ | |
| 219 cmpw r6,r7 /* done yet ? */ | |
| 220 blt 1b | |
| 221 #endif // CYGPRI_DO_PROGRAM_UPMS | |
| 222 | |
| 223 /* | |
| 224 * Set refresh timer prescaler to divide by 8. | |
| 225 */ | |
| 226 li r3,PTP_DIV32 | |
| 227 sth r3,MPTPR(r4) | |
| 228 | |
| 229 /* | |
| 230 * See Table 15-16 MPC860 User's Manual. | |
| 231 * | |
| 232 // Set the value of Machine A Mode Register (MAMR) to $5E802114. | |
| 233 // Field PTA (bits 0-7) = 94 | |
| 234 // Field PTAE (bit 8) = 1 | |
| 235 // Field AMA (bits 9-11) = 0 | |
| 236 // Field Reserved (bit 12) = 0 | |
| 237 // Field DSA (bits 13-14) = 0 | |
| 238 // Field Reserved (bit 15) = 0 | |
| 239 // Field G0CLA (bits 16-18) = 1 | |
| 240 // Field GPL_A4DIS (bit 19) = 0 | |
| 241 // Field RLFA (bits 20-23) = 1 | |
| 242 // Field WLFA (bits 24-27) = 1 | |
| 243 // Field TLFA (bits 28-31) = 4 | |
| 244 */ | |
| 245 | |
| 246 // | |
| 247 // PTA field is (System Clock in MHz * Refresh rate in us) / Prescale | |
| 248 // e.g. ((14*3.6864)*62.5)/32 => 100.8 => 101 | |
| 249 // | |
|
862
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
250 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
251 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 48) |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
252 #define PLPRCR_VALUE 0x32594000 // MFI=9 MFN=6 MFD=9 PDF=0 S=1 OSCLK=10MEG |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
253 #define MAMR_PTA 93 //sysclk * 62.5e-6 /32 |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
254 #endif |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
255 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 50) |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
256 #define PLPRCR_VALUE 0xD05A4000 // MFI=10 MFN=0 MFD=1 PDF=0 S=1 OSCLK=10MEG |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
257 #define MAMR_PTA 97 //sysclk * 62.5e-6 /32 |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
258 #endif |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
259 #else |
| 432 | 260 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 47) |
|
862
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
261 #define PLPRCR_VALUE 0x00C04000 // MFI=9 MFN=6 MFD=9 PDF=0 S=1 OSCLK=10MEG |
| 432 | 262 #define MAMR_PTA 94 |
| 263 #endif | |
|
862
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
264 #endif |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
265 |
| 432 | 266 //#define MAMR_PTA (((((((PLPRCR_PTX+1)*3686400)*625)/10000000)+31)/32)&0xFF) |
| 267 lwi r3,0x00802114|(MAMR_PTA<<24) | |
| 268 stw r3,MAMR(r4) | |
| 269 stw r3,MBMR(r4) | |
| 270 | |
| 271 /* | |
| 272 * Base Register initialization. | |
| 273 */ | |
| 274 | |
| 275 /* BOOT ROM */ | |
| 276 lwi r3,0xFE000801 # 16-bit, GPCM | |
| 277 lwi r5,0xFF800774 # 7 wait states, up to 8MB | |
| 278 stw r3,BR0(r4) | |
| 279 stw r5,OR0(r4) | |
| 280 | |
| 281 /* Misc I/O, 16 bit port */ | |
| 282 lwi r3,0xFA100801 | |
| 283 lwi r5,0xFFFF8730 | |
| 284 stw r3,BR2(r4) | |
| 285 stw r5,OR2(r4) | |
| 286 | |
| 287 /* ONBOARD DRAM */ | |
| 288 lwi r3,0x00000081 # 32-bit, UPMA | |
| 289 lwi r5,0xFF800E00 | |
| 290 stw r3,BR1(r4) | |
| 291 stw r5,OR1(r4) | |
| 292 | |
| 293 /* DRAM DIMM BANK1 */ | |
| 294 lwi r3,0x00000080 # 32-bit, UPMA, INVALID | |
| 295 lwi r5,0xFFFF87FC | |
| 296 stw r3,BR3(r4) | |
| 297 stw r5,OR3(r4) | |
| 298 | |
| 299 #if 0 | |
| 300 /* NVRAM */ | |
| 301 lwi r3,0xfa000401 # 8-bit, GPCM | |
| 302 lwi r5,0xffe00930 | |
| 303 stw r3,BR4(r4) | |
| 304 stw r5,OR4(r4) | |
| 305 | |
| 306 /* PCI BRIDGE MEM/IO */ | |
| 307 lwi r3,0x80000001 # 32-bit, GPCM | |
| 308 lwi r5,0xa0000108 | |
| 309 stw r3,BR5(r4) | |
| 310 stw r5,OR5(r4) | |
| 311 | |
| 312 /* PCI BRIDGE REGISTERS */ | |
| 313 lwi r3,0xfa210001 # 32-bit, GPCM | |
| 314 lwi r5,0xffff0108 | |
| 315 stw r3,BR6(r4) | |
| 316 stw r5,OR6(r4) | |
| 317 | |
| 318 /* FLASH */ | |
| 319 lwi r3,0xfc000001 # 32-bit, GPCM | |
| 320 lwi r5,0xff800940 | |
| 321 stw r3,BR7(r4) | |
| 322 stw r5,OR7(r4) | |
| 323 #endif | |
| 324 | |
| 325 /* | |
| 326 * SYSTEM CLOCK CONTROL REGISTER | |
| 327 // Set the value of System Clock and Reset Control Register (SCCR) to $00400000. | |
| 328 // Field Reserved (bit 0) = 0 | |
| 329 // Field COM (bits 1-2) = 0 | |
| 330 // Field Reserved (bits 3-5) = 0 | |
| 331 // Field TBS (bit 6) = 0 | |
| 332 // Field RTDIV (bit 7) = 0 | |
| 333 // Field RTSEL (bit 8) = 0 | |
| 334 // Field CRQEN (bit 9) = 1 | |
| 335 // Field PRQEN (bit 10) = 0 | |
| 336 // Field Reserved (bits 11-12) = 0 | |
| 337 // Field EBDF (bits 13-14) = 0 | |
| 338 // Field Reserved (bits 15-16) = 0 | |
| 339 // Field DFSYNC (bits 17-18) = 0 | |
| 340 // Field DFBRG (bits 19-20) = 0 | |
| 341 // Field DFNL (bits 21-23) = 0 | |
| 342 // Field DFNH (bits 24-26) = 0 | |
| 343 // Field Reserved (bits 27-31) = 0 | |
| 344 */ | |
| 345 lwi r3,0x00400000 | |
| 346 stw r3,SCCR(r4) | |
| 347 | |
| 348 /* | |
| 349 * PLL, LOW POWER, AND RESET CONTROL REGISTER | |
| 350 // Set the value of PLL, Low Power and Reset Control Register (PLPRCR) to $00C04000. | |
| 351 // Field MF (bits 0-11) = 12 | |
| 352 // Field Reserved (bits 12-15) = 0 | |
| 353 // Field SPLSS (bit 16) = 0 | |
| 354 // Field TEXPS (bit 17) = 1 | |
| 355 // Field Reserved (bit 18) = 0 | |
| 356 // Field TMIST (bit 19) = 0 | |
| 357 // Field Reserved (bit 20) = 0 | |
| 358 // Field CSRC (bit 21) = 0 | |
| 359 // Field LPM (bits 22-23) = 0 | |
| 360 // Field CSR (bit 24) = 0 | |
| 361 // Field LOLRE (bit 25) = 0 | |
| 362 // Field FIOPD (bit 26) = 0 | |
| 363 // Field Reserved (bits 27-31) = 0 | |
| 364 */ | |
|
862
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
365 // lwi r3,0x04000|(PLPRCR_PTX<<20) |
|
725ba4e57f0c
Add support for A&M Adder-II (by extending Adder platform)
gthomas
parents:
432
diff
changeset
|
366 lwi r3,PLPRCR_VALUE |
| 432 | 367 stw r3,PLPRCR(r4) |
| 368 | |
| 369 lwi r3,0x40000 | |
| 370 mtctr r3 | |
| 371 10: nop | |
| 372 bdnz 10b | |
| 373 | |
| 374 /* SDRAM Initialization Sequence, UPMA, CS1 */ | |
| 375 li r3,0 | |
| 376 stw r3,MAR(r4) | |
| 377 | |
| 378 lwi r3,0x80002115; /* run precharge from loc 21 (0x15) */ | |
| 379 stw r3,MCR(r4) | |
| 380 | |
| 381 lwi r3,0x80002830; /* run refresh 8 times */ | |
| 382 stw r3,MCR(r4) | |
| 383 | |
| 384 lwi r3,0x88; /* MR 88 for high range */ | |
| 385 stw r3,MAR(r4) | |
| 386 | |
| 387 lwi r3,0x80002116; /* run MRS pattern from loc 22 (0x16) */ | |
| 388 stw r3,MCR(r4) | |
| 389 | |
| 390 # mask interrupt sources in the SIU | |
| 391 lis r2,0 | |
| 392 lwi r3,CYGARC_REG_IMM_SIMASK | |
| 393 stw r2,0(r3) | |
| 394 | |
| 395 # set the decrementer to maxint | |
| 396 lwi r2,0 | |
| 397 not r2,r2 | |
| 398 mtdec r2 | |
| 399 | |
| 400 # and enable the timebase and decrementer to make sure | |
| 401 li r2,1 # TBEnable and not TBFreeze | |
| 402 lwi r3,CYGARC_REG_IMM_TBSCR | |
| 403 sth r2,0(r3) | |
| 404 | |
| 405 #ifdef CYG_HAL_STARTUP_ROM | |
| 406 # move return address to where the ROM is | |
| 407 mflr r3 | |
| 408 lwi r4,0x00FFFFFF // CAUTION!! Assumes only low 16M for ROM | |
| 409 and r3,r3,r4 | |
| 410 oris r3,r3,CYGMEM_REGION_rom>>16 | |
| 411 mtlr r3 | |
| 412 #endif | |
| 413 | |
| 414 #ifdef CYG_HAL_STARTUP_ROMRAM | |
| 415 // Copy image from ROM to RAM | |
| 416 mflr r3 | |
| 417 lwi r4,0xFE000000 | |
| 418 lwi r5,0x01FFFFFF // ROM/FLASH base | |
| 419 and r3,r3,r5 // segment relative | |
| 420 lwi r6,_hal_hardware_init_done | |
| 421 mtlr r6 | |
| 422 sub r6,r3,r6 // Absolute address | |
| 423 add r6,r6,r4 // FLASH address | |
| 424 lwi r7,0 // where to copy to | |
| 425 lwi r8,__ram_data_end | |
| 426 10: lwz r5,0(r6) | |
| 427 stw r5,0(r7) | |
| 428 addi r6,r6,4 | |
| 429 addi r7,r7,4 | |
| 430 cmplw r7,r8 | |
| 431 bne 10b | |
| 432 #endif | |
| 433 blr | |
| 434 FUNC_END( hal_hardware_init ) | |
| 435 | |
| 436 | |
| 437 #ifdef CYGPRI_DO_PROGRAM_UPMS | |
| 438 # ------------------------------------------------------------------------- | |
| 439 # this table initializes the User Programmable Machine (UPM) nastiness | |
| 440 # in the QUICC to control DRAM timing. | |
| 441 | |
| 442 __upmtbl_start: | |
| 443 // single read (offset 0x00 in upm ram) | |
| 444 .long 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00 | |
| 445 .long 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04 | |
| 446 // burst read (offset 0x08 in upm ram) | |
| 447 .long 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00 | |
| 448 .long 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44 | |
| 449 .long 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35 | |
| 450 .long 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35 | |
| 451 // single write (offset 0x18 in upm ram) | |
| 452 .long 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47 | |
| 453 .long 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 454 // burst write (offset 0x20 in upm ram) | |
| 455 .long 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00 | |
| 456 .long 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04 | |
| 457 .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 458 .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 459 // refresh (offset 0x30 in upm ram) | |
| 460 .long 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 461 .long 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04 | |
| 462 .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 463 // exception (offset 0x3C in upm ram) | |
| 464 .long 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 465 __upmtbl_end: | |
| 466 #endif // CYGPRI_DO_PROGRAM_UPMS | |
| 467 | |
| 468 #------------------------------------------------------------------------------ | |
| 469 # end of adder.S |