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comparison packages/hal/sh/edk/current/cdl/hal_sh_edk7708.cdl @ 128:0c2b7be0d798 ecos-sw-2000-10-12

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Merge from eCos master repository on 2000-10-12-08:46:24-BST
author jlarmour
date Thu, 12 Oct 2000 20:31:43 +0000
parents 84e4bde58b26
children
comparison
equal deleted inserted replaced
127:67f0ef5f8ee9 128:0c2b7be0d798
111 description " 111 description "
112 The EDK/7708 board has only one serial port. This option 112 The EDK/7708 board has only one serial port. This option
113 chooses which port will be used for diagnostic output." 113 chooses which port will be used for diagnostic output."
114 } 114 }
115 115
116 cdl_option CYGHWR_HAL_SH_BOARD_SPEED { 116 cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {
117 display "Development board clock speed (MHz)" 117 display "SH on-chip platform clock controls"
118 flavor data
119 calculated 15
120 description " 118 description "
121 The EDK/7708 board uses a 15MHz crystal." 119 The various clocks used by the system are derived from
122 } 120 these options."
123
124 # Real-time clock/counter specifics
125 cdl_component CYGNUM_HAL_RTC_CONSTANTS {
126 display "Real-time clock constants."
127 description "
128 Using TMU counter 0, clocked at p/4, with peripheral clock
129 sourced directly from the 15MHz crystal (which is the
130 default setup on the EDK). This means 150000/4
131 oscillations in 1/100 second."
132 flavor none 121 flavor none
133 122 no_define
134 cdl_option CYGNUM_HAL_RTC_NUMERATOR { 123
135 display "Real-time clock numerator" 124 cdl_option CYGHWR_HAL_SH_OOC_XTAL {
136 flavor data 125 display "SH clock crystal"
137 calculated 1000000000 126 flavor data
138 } 127 legal_values 8000000 to 50000000
139 cdl_option CYGNUM_HAL_RTC_DENOMINATOR { 128 default_value 15000000
140 display "Real-time clock denominator" 129 no_define
141 flavor data 130 description "
142 calculated 100 131 This option specifies the frequency of the crystal all
143 } 132 other clocks are derived from."
144 cdl_option CYGNUM_HAL_RTC_PERIOD { 133 }
145 display "Real-time clock period" 134
146 flavor data 135 cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {
147 calculated { CYGHWR_HAL_SH_BOARD_SPEED*1000000/CYGNUM_HAL_RTC_DENOMINATOR/4 } 136 display "SH clock PLL circuit 1"
137 flavor data
138 default_value 1
139 legal_values { 0 1 2 4 }
140 description "
141 This selects the multiplication factor provided by
142 PLL1. If PLL1 is disabled via CAP1, this option should
143 be set to zero."
144 }
145
146 cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {
147 display "SH clock PLL circuit 2"
148 flavor data
149 default_value 4
150 legal_values { 0 1 4 }
151 no_define
152 description "
153 This selects the multiplication factor provided by
154 PLL2. If PLL2 is disabled via CAP2, this option should
155 be set to zero."
156 }
157
158 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 {
159 display "SH clock divider 1"
160 flavor data
161 default_value 1
162 legal_values { 1 2 3 4 }
163 description "
164 This divider option affects the CPU core clock."
165 }
166
167 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_2 {
168 display "SH clock divider 2"
169 flavor data
170 default_value 4
171 legal_values { 1 2 3 4 }
172 description "
173 This divider option affects the peripheral clock."
174 }
175
176 cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE {
177 display "SH clock mode"
178 flavor data
179 default_value 2
180 legal_values { 0 1 2 3 4 7 }
181 description "
182 This option must mirror the clock mode hardwired on
183 the MD0-MD2 pins of the CPU in order to correctly
184 initialize the FRQCR register."
148 } 185 }
149 } 186 }
150 187
151 cdl_component CYGBLD_GLOBAL_OPTIONS { 188 cdl_component CYGBLD_GLOBAL_OPTIONS {
152 display "Global build options" 189 display "Global build options"
153 flavor none 190 flavor none
154 parent CYGPKG_NONE 191 parent CYGPKG_NONE
192 no_define
155 description " 193 description "
156 Global build options including control over 194 Global build options including control over
157 compiler flags, linker flags and choice of toolchain." 195 compiler flags, linker flags and choice of toolchain."
158 196
159 197