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comparison packages/devs/serial/i386/pc/current/src/pc_serial.h @ 82:6736c52df507 ecos-sw-2000-04-14

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Merge from eCos master repository on 2000-04-14-13:35:46-BST
author jlarmour
date Tue, 18 Apr 2000 21:51:55 +0000
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81:89fef2181d7d 82:6736c52df507
1 #ifndef CYGONCE_I386_PC_SERIAL_H
2 #define CYGONCE_I386_PC_SERIAL_H
3
4 // ====================================================================
5 //
6 // pc_serial.h
7 //
8 // Device I/O - Description of i386/PC 8250/16550 serial hardware
9 //
10 // ====================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Red Hat eCos Public License
15 // Version 1.0 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://sourceware.cygnus.com/ecos
18 //
19 // Software distributed under the License is distributed on an
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Configurable Operating System,
25 // released September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Red Hat.
28 // Portions created by Red Hat are
29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
30 // All Rights Reserved.
31 // -------------------------------------------
32 //
33 //####COPYRIGHTEND####
34 // ====================================================================
35 //#####DESCRIPTIONBEGIN####
36 //
37 // Author(s): gthomas
38 // Contributors: gthomas, pjo
39 // Date: 1999-02-04
40 // Purpose: Internal interfaces for serial I/O drivers
41 // Description:
42 //
43 //####DESCRIPTIONEND####
44 //
45 // ====================================================================
46
47 // Description of serial ports on i386/PC 8250/16550
48
49
50 // Receive control registers
51 #define RHR 0 // Receive holding register
52 #define ISR 2 // Interrupt status register
53 #define LSR 5 // Line status register
54 #define MSR 6 // Modem status register
55 #define SCR 7 // Scratch register
56
57 // Transmit control registers
58 #define THR 0 // Transmit holding register
59 #define IER 1 // Interrupt enable register
60 #define FCR 2 // FIFO control register
61 #define LCR 3 // Line control register
62 #define MCR 4 // Modem control register
63 #define LDL 0 // LSB of baud rate
64 #define MDL 1 // MSB of baud rate
65
66 // Interrupt Enable Register
67 #define IER_RCV 0x01
68 #define IER_XMT 0x02
69 #define IER_LS 0x04
70 #define IER_MS 0x08
71
72 // Line Control Register
73 #define LCR_WL5 0x00 // Word length
74 #define LCR_WL6 0x01
75 #define LCR_WL7 0x02
76 #define LCR_WL8 0x03
77 #define LCR_SB1 0x00 // Number of stop bits
78 #define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words
79 #define LCR_SB2 0x04
80 #define LCR_PN 0x00 // Parity mode - none
81 #define LCR_PE 0x0C // Parity mode - even
82 #define LCR_PO 0x08 // Parity mode - odd
83 #define LCR_PM 0x28 // Forced "mark" parity
84 #define LCR_PS 0x38 // Forced "space" parity
85 #define LCR_DL 0x80 // Enable baud rate latch
86
87 // Line Status Register
88 #define LSR_RSR 0x01
89 #define LSR_THE 0x20
90
91 // Modem Control Register
92 #define MCR_DTR 0x01
93 #define MCR_RTS 0x02
94 #define MCR_INT 0x0C // Enable interrupts
95 #define MCR_LOOP 0x10 // Loopback mode.
96
97
98 // FIFO control register
99 #define FCR_FE 0x01 // Fifo enable
100 #define FCR_RFR 0x02 // Receiver fifo reset
101 #define FCR_TFR 0x04 // Transmitter fifo reset
102 #define FCR_RT14 0xC0
103 #define FCR_RT8 0x80
104 #define FCR_RT4 0x40
105 #define FCR_RT1 0x00
106
107 // FIFO lengths
108 #define PC16550_FIFO_TX_LENGTH (16 /*only for s16550a*/)
109 #define PC16550_FIFO_RX_LENGTH (16 /*only for s16550a*/)
110
111 // Interrupt status register
112 #define ISR_Tx 0x02
113 #define ISR_Rx 0x04
114
115 static unsigned char select_word_length[] = {
116 LCR_WL5, // 5 bits / word (char)
117 LCR_WL6,
118 LCR_WL7,
119 LCR_WL8
120 };
121
122 static unsigned char select_stop_bits[] = {
123 0,
124 LCR_SB1, // 1 stop bit
125 LCR_SB1_5, // 1.5 stop bit
126 LCR_SB2 // 2 stop bits
127 };
128
129 static unsigned char select_parity[] = {
130 LCR_PN, // No parity
131 LCR_PE, // Even parity
132 LCR_PO, // Odd parity
133 LCR_PM, // Mark parity
134 LCR_PS, // Space parity
135 };
136
137 // Baud rate values, based on raw 24MHz clock
138
139 static unsigned short select_baud[] = {
140 0, // Unused
141 2304, // 50
142 1536, // 75
143 1047, // 110
144 857, // 134.5
145 768, // 150
146 576, // 200
147 384, // 300
148 192, // 600
149 96, // 1200
150 64, // 1800
151 48, // 2400
152 32, // 3600
153 24, // 4800
154 16, // 7200
155 12, // 9600
156 8, // 14400
157 6, // 19200
158 3, // 38400
159 2, // 57600
160 1, // 115200
161 0, // 230400
162 };
163
164 #endif // CYGONCE_I386_PC_SERIAL_H