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comparison packages/io/serial/current/tests/ser_test_protocol.inl @ 115:6ed91473a1cd ecos-sw-2000-08-21

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Merge from eCos master repository on 2000-08-21-22:40:54-BST
author jlarmour
date Fri, 25 Aug 2000 17:32:38 +0000
parents ff3f181b64bd
children 0ec04793409a
comparison
equal deleted inserted replaced
114:5ad2b71d525e 115:6ed91473a1cd
230 # define TEST_SER_DEV CYGDAT_IO_SERIAL_V85X_V850_SERIAL0_NAME 230 # define TEST_SER_DEV CYGDAT_IO_SERIAL_V85X_V850_SERIAL0_NAME
231 # if defined(CYGPKG_IO_SERIAL_TTY_TTY0) 231 # if defined(CYGPKG_IO_SERIAL_TTY_TTY0)
232 # define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY0_DEV 232 # define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY0_DEV
233 # endif 233 # endif
234 #endif 234 #endif
235 #if defined(CYGPKG_IO_SERIAL_LOOP) \
236 && defined(CYGPKG_IO_SERIAL_LOOP_SERIAL0)
237 # define TEST_CRASH_ID "loop"
238 # define TEST_SER_DEV CYGDAT_IO_SERIAL_LOOP_SERIAL0_NAME
239 # if defined(CYGPKG_IO_SERIAL_TTY_TTY0)
240 # define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY0_DEV
241 # endif
242 #endif
235 243
236 // We can't rely on haldiag for ser_filter detection - it may not define 244 // We can't rely on haldiag for ser_filter detection - it may not define
237 // a working character reading function. 245 // a working character reading function.
238 #ifndef TEST_SER_DEV 246 #ifndef TEST_SER_DEV
239 # define SER_NOP_TEST 247 # define SER_NOP_TEST
301 #define TEST_CRASH_HOST_DUPLEX_BAD "%d:%d:%02x:%02x", 0xf020 309 #define TEST_CRASH_HOST_DUPLEX_BAD "%d:%d:%02x:%02x", 0xf020
302 // command#, index, expected char, actual 310 // command#, index, expected char, actual
303 311
304 //---------------------------------------------------------------------------- 312 //----------------------------------------------------------------------------
305 // The data in buffer and the cmd buffer 313 // The data in buffer and the cmd buffer
306 #define IN_BUFFER_SIZE 1024 314 #ifndef IN_BUFFER_SIZE
315 # define IN_BUFFER_SIZE 1024
316 #endif
307 cyg_uint8 in_buffer[IN_BUFFER_SIZE]; 317 cyg_uint8 in_buffer[IN_BUFFER_SIZE];
308 318
309 cyg_int8 cmd_buffer[128]; 319 cyg_int8 cmd_buffer[128];
310 320
311 //---------------------------------------------------------------------------- 321 //----------------------------------------------------------------------------
320 TEST_RETURN_OK = ENOERR, 330 TEST_RETURN_OK = ENOERR,
321 TEST_RETURN_NA 331 TEST_RETURN_NA
322 } cyg_test_return_t; 332 } cyg_test_return_t;
323 333
324 typedef struct ser_cfg { 334 typedef struct ser_cfg {
325 cyg_serial_baud_rate_t baud_rate; 335 cyg_serial_baud_rate_t baud_rate;
326 cyg_serial_word_length_t data_bits; 336 cyg_serial_word_length_t data_bits;
327 cyg_serial_stop_bits_t stop_bits; 337 cyg_serial_stop_bits_t stop_bits;
328 cyg_serial_parity_t parity; 338 cyg_serial_parity_t parity;
339 cyg_uint32 flags;
329 // etc... 340 // etc...
330 } cyg_ser_cfg_t; 341 } cyg_ser_cfg_t;
331 342
332 typedef enum { 343 typedef enum {
333 OPT_SERIAL_DEBUG = 0, 344 OPT_SERIAL_DEBUG = 0,
374 // A few predefined configurations. These must all be valid for any 385 // A few predefined configurations. These must all be valid for any
375 // given target until change_config is behaving correctly. 386 // given target until change_config is behaving correctly.
376 cyg_ser_cfg_t test_configs[] = { 387 cyg_ser_cfg_t test_configs[] = {
377 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && !defined(CYGPKG_HAL_ARM_PID) 388 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && !defined(CYGPKG_HAL_ARM_PID)
378 { CYGNUM_SERIAL_BAUD_9600, CYGNUM_SERIAL_WORD_LENGTH_8, 389 { CYGNUM_SERIAL_BAUD_9600, CYGNUM_SERIAL_WORD_LENGTH_8,
379 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }, 390 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE,
391 CYGNUM_SERIAL_FLOW_NONE },
380 #endif 392 #endif
381 393
382 #if !defined(CYGPKG_HAL_MN10300_AM31) && \ 394 #if !defined(CYGPKG_HAL_MN10300_AM31) && \
383 !defined(CYGPKG_HAL_MN10300_AM33) && \ 395 !defined(CYGPKG_HAL_MN10300_AM33)
384 1
385 { CYGNUM_SERIAL_BAUD_14400, CYGNUM_SERIAL_WORD_LENGTH_8, 396 { CYGNUM_SERIAL_BAUD_14400, CYGNUM_SERIAL_WORD_LENGTH_8,
386 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }, 397 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE,
398 CYGNUM_SERIAL_FLOW_NONE },
387 #endif 399 #endif
388 400
389 { CYGNUM_SERIAL_BAUD_19200, CYGNUM_SERIAL_WORD_LENGTH_8, 401 { CYGNUM_SERIAL_BAUD_19200, CYGNUM_SERIAL_WORD_LENGTH_8,
390 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }, 402 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE,
403 CYGNUM_SERIAL_FLOW_NONE },
391 404
392 #if !defined(CYGPKG_HAL_SPARCLITE_SLEB) && \ 405 #if !defined(CYGPKG_HAL_SPARCLITE_SLEB) && \
393 !defined(CYGPKG_HAL_ARM_AEB) 406 !defined(CYGPKG_HAL_ARM_AEB)
394 { CYGNUM_SERIAL_BAUD_38400, CYGNUM_SERIAL_WORD_LENGTH_8, 407 { CYGNUM_SERIAL_BAUD_38400, CYGNUM_SERIAL_WORD_LENGTH_8,
395 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }, 408 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE,
409 CYGNUM_SERIAL_FLOW_NONE },
396 #endif 410 #endif
397 411
398 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && \ 412 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && \
399 !defined(CYGPKG_HAL_ARM_AEB) && \ 413 !defined(CYGPKG_HAL_ARM_AEB) && \
400 !defined(CYGPKG_HAL_SPARCLITE_SLEB) && \ 414 !defined(CYGPKG_HAL_SPARCLITE_SLEB) && \
401 !defined(CYGPKG_HAL_MN10300_AM33) && \ 415 !defined(CYGPKG_HAL_MN10300_AM33)
402 1
403 { CYGNUM_SERIAL_BAUD_57600, CYGNUM_SERIAL_WORD_LENGTH_8, 416 { CYGNUM_SERIAL_BAUD_57600, CYGNUM_SERIAL_WORD_LENGTH_8,
404 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }, 417 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE,
418 CYGNUM_SERIAL_FLOW_NONE },
405 #endif 419 #endif
406 420
407 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && \ 421 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && \
408 !defined(CYGPKG_HAL_ARM_PID) && \ 422 !defined(CYGPKG_HAL_ARM_PID) && \
409 !defined(CYGPKG_HAL_ARM_AEB) && \ 423 !defined(CYGPKG_HAL_ARM_AEB) && \
410 !defined(CYGPKG_HAL_MN10300_STDEVAL1) && \ 424 !defined(CYGPKG_HAL_MN10300_STDEVAL1) && \
411 !defined(CYGPKG_HAL_ARM_CMA230) && \ 425 !defined(CYGPKG_HAL_ARM_CMA230) && \
412 !defined(CYGPKG_HAL_ARM_EDB7XXX) && \ 426 !defined(CYGPKG_HAL_ARM_EDB7XXX) && \
413 !defined(CYGPKG_HAL_SPARCLITE_SLEB) 427 !defined(CYGPKG_HAL_SPARCLITE_SLEB)
414 { CYGNUM_SERIAL_BAUD_115200, CYGNUM_SERIAL_WORD_LENGTH_8, 428 { CYGNUM_SERIAL_BAUD_115200, CYGNUM_SERIAL_WORD_LENGTH_8,
415 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }, 429 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE,
430 CYGNUM_SERIAL_FLOW_NONE },
416 #endif 431 #endif
417 432
418 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && \ 433 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && \
419 !defined(CYGPKG_HAL_ARM_AEB) && \ 434 !defined(CYGPKG_HAL_ARM_AEB) && \
420 !defined(CYGPKG_HAL_ARM_PID) 435 !defined(CYGPKG_HAL_ARM_PID)
421 // One stop bit, even parity 436 // One stop bit, even parity
422 { CYGNUM_SERIAL_BAUD_19200, CYGNUM_SERIAL_WORD_LENGTH_8, 437 { CYGNUM_SERIAL_BAUD_19200, CYGNUM_SERIAL_WORD_LENGTH_8,
423 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_EVEN }, 438 CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_EVEN,
439 CYGNUM_SERIAL_FLOW_NONE },
424 #endif 440 #endif
425 441
426 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && \ 442 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && \
427 !defined(CYGPKG_HAL_ARM_AEB) && \ 443 !defined(CYGPKG_HAL_ARM_AEB) && \
428 !defined(CYGPKG_HAL_ARM_PID) 444 !defined(CYGPKG_HAL_ARM_PID)
429 // Two stop bits, even parity 445 // Two stop bits, even parity
430 { CYGNUM_SERIAL_BAUD_19200, CYGNUM_SERIAL_WORD_LENGTH_8, 446 { CYGNUM_SERIAL_BAUD_19200, CYGNUM_SERIAL_WORD_LENGTH_8,
431 CYGNUM_SERIAL_STOP_2, CYGNUM_SERIAL_PARITY_EVEN }, 447 CYGNUM_SERIAL_STOP_2, CYGNUM_SERIAL_PARITY_EVEN,
448 CYGNUM_SERIAL_FLOW_NONE },
432 #endif 449 #endif
433 450
434 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) 451 #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904)
435 // Two stop bits, no parity 452 // Two stop bits, no parity
436 { CYGNUM_SERIAL_BAUD_19200, CYGNUM_SERIAL_WORD_LENGTH_8, 453 { CYGNUM_SERIAL_BAUD_19200, CYGNUM_SERIAL_WORD_LENGTH_8,
437 CYGNUM_SERIAL_STOP_2, CYGNUM_SERIAL_PARITY_NONE }, 454 CYGNUM_SERIAL_STOP_2, CYGNUM_SERIAL_PARITY_NONE,
455 CYGNUM_SERIAL_FLOW_NONE },
438 #endif 456 #endif
439 }; 457 };
440 458
441 //---------------------------------------------------------------------------- 459 //----------------------------------------------------------------------------
442 // Macros to help extract values from the argument string. 460 // Macros to help extract values from the argument string.
586 // can handle the config. 604 // can handle the config.
587 // If not, return error. 605 // If not, return error.
588 // 606 //
589 // Then query the host for its capability to use the config: 607 // Then query the host for its capability to use the config:
590 // Format out: 608 // Format out:
591 // "@CONFIG:<baud rate code>:<#data bits>:<#stop bits>:<parity on/off>!" 609 // "@CONFIG:<baud rate code>:<#data bits>:<#stop bits>:<parity on/off>:<flow control code>!"
592 // Format in: 610 // Format in:
593 // OK/ER 611 // OK/ER
594 // 612 //
595 // On ER, return error. 613 // On ER, return error.
596 // 614 //
632 p1 = itoa(p1, cfg->data_bits); 650 p1 = itoa(p1, cfg->data_bits);
633 *p1++ = ':'; 651 *p1++ = ':';
634 p1 = itoa(p1, cfg->stop_bits); 652 p1 = itoa(p1, cfg->stop_bits);
635 *p1++ = ':'; 653 *p1++ = ':';
636 p1 = itoa(p1, cfg->parity); 654 p1 = itoa(p1, cfg->parity);
655 *p1++ = ':';
656 p1 = itoa(p1, cfg->flags);
637 *p1++ = '!'; 657 *p1++ = '!';
638 *p1 = 0; // note: we may append to this later 658 *p1 = 0; // note: we may append to this later
639 659
640 // Tell user what we're up to. 660 // Tell user what we're up to.
641 CYG_TEST_INFO(&cmd_buffer[1]); 661 CYG_TEST_INFO(&cmd_buffer[1]);
654 674
655 new_cfg.baud = cfg->baud_rate; 675 new_cfg.baud = cfg->baud_rate;
656 new_cfg.word_length = cfg->data_bits; 676 new_cfg.word_length = cfg->data_bits;
657 new_cfg.stop = cfg->stop_bits; 677 new_cfg.stop = cfg->stop_bits;
658 new_cfg.parity = cfg->parity; 678 new_cfg.parity = cfg->parity;
679 new_cfg.flags = cfg->flags;
659 680
660 res = cyg_io_set_config(handle, CYG_IO_SET_CONFIG_SERIAL_INFO, 681 res = cyg_io_set_config(handle, CYG_IO_SET_CONFIG_SERIAL_INFO,
661 &new_cfg, &len); 682 &new_cfg, &len);
662 cyg_thread_delay(10); // Some chips don't like changes to happen to fast... 683 cyg_thread_delay(10); // Some chips don't like changes to happen to fast...
663 684
849 // To Do: 870 // To Do:
850 // MODE_DUPLEX_ECHO: 871 // MODE_DUPLEX_ECHO:
851 // The current implementation is simple and may not stress the 872 // The current implementation is simple and may not stress the
852 // driver enough. Also, it's command packet format doesn't match 873 // driver enough. Also, it's command packet format doesn't match
853 // that of the other modes. 874 // that of the other modes.
875
854 cyg_test_return_t 876 cyg_test_return_t
855 test_binary(cyg_io_handle_t handle, int size, cyg_mode_t mode) 877 test_binary(cyg_io_handle_t handle, int size, cyg_mode_t mode)
856 { 878 {
857 const char cmd[] = "@BINARY:"; 879 const char cmd[] = "@BINARY:";
858 int msglen; 880 int msglen;
919 Tcyg_io_read(handle, &in_buffer[0], &chunk_len); 941 Tcyg_io_read(handle, &in_buffer[0], &chunk_len);
920 942
921 for (i = 0; i < tx_len; i++) { 943 for (i = 0; i < tx_len; i++) {
922 ADD_CRC_BYTE(xcrc, in_buffer[i]); 944 ADD_CRC_BYTE(xcrc, in_buffer[i]);
923 } 945 }
924 946
925 // Echo data back. 947 // Echo data back.
926 chunk_len = size; 948 chunk_len = size;
927 Tcyg_io_write(handle, &in_buffer[0], &chunk_len); 949 Tcyg_io_write(handle, &in_buffer[0], &chunk_len);
928 950
929 // Now read host side's status 951 // Now read host side's status