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comparison packages/hal/powerpc/ppc40x/current/include/var_regs.h @ 136:a9ac27ec7abc ecos-sw-2000-11-17

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Merge from eCos master repository on 2000-11-17-18:24:25-GMT
author jlarmour
date Fri, 17 Nov 2000 23:16:43 +0000
parents d2f49caf9e38
children 52c99470ec11
comparison
equal deleted inserted replaced
135:3bc2abeae9ff 136:a9ac27ec7abc
60 60
61 //-------------------------------------------------------------------------- 61 //--------------------------------------------------------------------------
62 // MMU control. 62 // MMU control.
63 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS 63 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
64 64
65 #define EVPR 982 // Exception vector prefix 65 #define SPR_EVPR 982 // Exception vector prefix
66 #define M_PID 945 // Process ID 66 #define SPR_PID 945 // Process ID
67 67
68 #define M_EPN_EPNMASK 0xfffff000 // effective page no mask 68 #define M_EPN_EPNMASK 0xfffff000 // effective page no mask
69 #define M_EPN_EV 0x00000040 // entry valid 69 #define M_EPN_EV 0x00000040 // entry valid
70 #define M_EPN_SIZE(n) (n<<7) // entry size (0=1K, 1=4K, ... 7=16M) 70 #define M_EPN_SIZE(n) (n<<7) // entry size (0=1K, 1=4K, ... 7=16M)
71 71
83 #define CYGARC_TLBRE(_id_, _hi_, _lo_) \ 83 #define CYGARC_TLBRE(_id_, _hi_, _lo_) \
84 asm volatile ("tlbre %0,%2,0; tlbre %1,%2,1" : "=r"(_hi_), "=r"(_lo_) : "r"(_id_)); 84 asm volatile ("tlbre %0,%2,0; tlbre %1,%2,1" : "=r"(_hi_), "=r"(_lo_) : "r"(_id_));
85 85
86 #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS 86 #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
87 87
88 //--------------------------------------------------------------------------
89 // Device control register access macros.
90 #define CYGARC_MTDCR(_tbr_, _v_) \
91 asm volatile ("mtdcr %0, %1;" :: "I" (_tbr_), "r" (_v_));
92 #define CYGARC_MFDCR(_tbr_, _v_) \
93 asm volatile ("mfdcr %0, %1;" : "=r" (_v_) : "I" (_tbr_));
94
95 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
96
97 // Interrupt control (device) registers
98 #define DCR_EXIER 66
99 #define DCR_EXISR 64
100 #define DCR_IOCR 160
101
102 // Timer control (special) registers
103 #define SPR_PIT 987
104 #define SPR_TCR 986
105 #define SPR_TSR 984
106
107 // Interval and watchdog timer control
108 #define TCR_WP 0xC0000000 // Watchdog timer period
109 #define TCR_WP_17 0x00000000 // 2^17 clocks
110 #define TCR_WP_21 0x40000000 // 2^21 clocks
111 #define TCR_WP_25 0x80000000 // 2^25 clocks
112 #define TCR_WP_29 0xC0000000 // 2^29 clocks
113 #define TCR_WRC 0x30000000 // Reset control
114 #define TCR_WRC_None 0x00000000 // No reset on timeout
115 #define TCR_WRC_Core 0x10000000 // Reset core on timeout
116 #define TCR_WRC_Chip 0x20000000 // Reset chip on timeout
117 #define TCR_WRC_System 0x30000000 // Reset system on timeout
118 #define TCR_WIE 0x08000000 // Watchdog interrupt enable
119 #define TCR_PIE 0x04000000 // Programmable timer interrupt
120 #define TCR_FP 0x03000000 // Fixed timer interval
121 #define TCR_FP_9 0x00000000 // 2^9 clocks
122 #define TCR_FP_13 0x01000000 // 2^13 clocks
123 #define TCR_FP_17 0x02000000 // 2^17 clocks
124 #define TCR_FP_21 0x03000000 // 2^21 clocks
125 #define TCR_FIE 0x00800000 // Fixed timer interrupt
126 #define TCR_ARE 0x00400000 // Auto-reload enable
127
128 // Interval and watchdog status
129 #define TSR_ENW 0x80000000 // Enable next watchdog
130 #define TSR_WIS 0x40000000 // Watchdog interrupt pending
131 #define TSR_WRS 0x30000000 // Watchdog reset state
132 #define TSR_WRS_None 0x00000000 // No watchdog reset
133 #define TSR_WRS_Core 0x10000000 // Core reset by watchdog
134 #define TSR_WRS_Chip 0x20000000 // Chip reset by watchdog
135 #define TSR_WRS_System 0x30000000 // System reset by watchdog
136 #define TSR_PIS 0x08000000 // Programmable timer interrupt
137 #define TSR_FIS 0x04000000 // Fixed timer interrupt
138
139 #endif // CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
140
88 //----------------------------------------------------------------------------- 141 //-----------------------------------------------------------------------------
89 #endif // ifdef CYGONCE_HAL_VAR_REGS_H 142 #endif // ifdef CYGONCE_HAL_VAR_REGS_H
90 // End of var_regs.h 143 // End of var_regs.h