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comparison packages/hal/fr30/mb91301/current/include/variant.inc @ 2557:cab33d750f3a

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* include/variant.inc: * include/var_cache.h: Support the cache of the mb91301 variant, uses it as 4 kb instruction cache.
author asl
date Mon, 22 Sep 2008 18:22:15 +0000
parents 24cb6e989e05
children 74dbf4c3f2e1
comparison
equal deleted inserted replaced
2556:dcf60bb1f255 2557:cab33d750f3a
174 ## registers for clock settings 174 ## registers for clock settings
175 ## 175 ##
176 .equ FR30_MB91301_RTC_TMRLR, 0x50 176 .equ FR30_MB91301_RTC_TMRLR, 0x50
177 .equ FR30_MB91301_RTC_TMR, 0x52 177 .equ FR30_MB91301_RTC_TMR, 0x52
178 .equ FR30_MB91301_RTC_TMCSR, 0x56 178 .equ FR30_MB91301_RTC_TMCSR, 0x56
179 179 ##-----------------------------------------------------------------------------
180 180 ## registers for cache settings
181 ##
182 .equ FR30_MB91301_CACHE_ISIZE, 0x307
183 .equ FR30_MB91301_CACHE_ICHCR, 0x3e7
181 184
182 ##------------------------------------------------------------------------------ 185 ##------------------------------------------------------------------------------
183 ## CPU initialisation macro 186 ## CPU initialisation macro
184 ## This is mainly for setting clock speeds. 187 ## This is mainly for setting clock speeds.
185 ##------------------------------------------------------------------------------ 188 ##------------------------------------------------------------------------------
335 #define CYGPKG_HAL_FR30_TIMER_DEFINED 338 #define CYGPKG_HAL_FR30_TIMER_DEFINED
336 339
337 #endif 340 #endif
338 341
339 #------------------------------------------------------------------------------ 342 #------------------------------------------------------------------------------
343 # Cache initialization. We use 4 kb Cache, although not so documented.
344 # The processor manual is not clear about this.
345 # r0 and r1 are polluted
346
347 #ifndef CYGPKG_HAL_FR30_CACHE_DEFINED
348 #define CYGPKG_HAL_FR30_CACHE_DEFINED
349
350 .macro hal_cache_init
351
352 ldi:20 #FR30_MB91301_CACHE_ICHCR, r0
353 # set (CYG_HAL_FR30_CACHE_ICHCR_RAM | CYG_HAL_FR30_CACHE_ICHCR_FLSH |
354 # CYG_HAL_FR30_CACHE_ICHCR_ELKR | CYG_HAL_FR30_CACHE_ICHCR_ENAB)
355 ldi:20 #0x87, r1
356 stb r1, @r0
357 .endm
358
359 #endif
360
361 #------------------------------------------------------------------------------
340 #endif // ifndef CYGONCE_HAL_VARIANT_INC 362 #endif // ifndef CYGONCE_HAL_VARIANT_INC
341 # end of variant.inc 363 # end of variant.inc