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comparison packages/hal/mips/ref4955/current/include/platform.inc @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children e0c0827131d1
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133:98d71f4d8243 134:d2f49caf9e38
1 #ifndef CYGONCE_HAL_PLATFORM_INC
2 #define CYGONCE_HAL_PLATFORM_INC
3 ##=============================================================================
4 ##
5 ## platform.inc
6 ##
7 ## REF4955/TX4955 board assembler header file
8 ##
9 ##=============================================================================
10 #####COPYRIGHTBEGIN####
11 #
12 # -------------------------------------------
13 # The contents of this file are subject to the Red Hat eCos Public License
14 # Version 1.1 (the "License"); you may not use this file except in
15 # compliance with the License. You may obtain a copy of the License at
16 # http://www.redhat.com/
17 #
18 # Software distributed under the License is distributed on an "AS IS"
19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
20 # License for the specific language governing rights and limitations under
21 # the License.
22 #
23 # The Original Code is eCos - Embedded Configurable Operating System,
24 # released September 30, 1998.
25 #
26 # The Initial Developer of the Original Code is Red Hat.
27 # Portions created by Red Hat are
28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
29 # All Rights Reserved.
30 # -------------------------------------------
31 #
32 #####COPYRIGHTEND####
33 ##=============================================================================
34 #######DESCRIPTIONBEGIN####
35 ##
36 ## Author(s): nickg
37 ## Contributors:nickg,jskov
38 ## Date: 2000-05-15
39 ## Purpose: REF4955/TX4955 board definitions.
40 ## Description: This file contains various definitions and macros that are
41 ## useful for writing assembly code for the REF4955/TX4955 board.
42 ## Usage:
43 ## #include <cyg/hal/platform.inc>
44 ## ...
45 ##
46 ##
47 ######DESCRIPTIONEND####
48 ##
49 ##=============================================================================
50
51 #include <cyg/hal/mips.inc>
52 #include <cyg/hal/plf_defs.inc>
53
54
55 #------------------------------------------------------------------------------
56 # Macro for copying vectors to RAM if necessary.
57 #if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
58
59 .macro hal_vectors_init
60 # If we don~t play nice with a ROM monitor, copy the required
61 # vectors into the proper location.
62 la t0,0x80000000 # dest addr
63 la t1,utlb_vector # source addr
64 la t3,utlb_vector_end # end dest addr
65 1:
66 lw v0,0(t1) # get word
67 addi t1,t1,4
68 sw v0,0(t0) # write word
69 addi t0,t0,4
70 bne t1,t3,1b
71 nop
72
73 la t0,0x80000180 # dest addr
74 la t1,other_vector # source addr
75 la t3,other_vector_end # end dest addr
76 1:
77 lw v0,0(t1) # get word
78 addi t1,t1,4
79 sw v0,0(t0) # write word
80 addi t0,t0,4
81 bne t1,t3,1b
82 nop
83
84 .set mips3 # Set ISA to MIPS 3 to allow cache insns
85 # Now clear the region in the caches
86 la t0,0x80000000 # dest addr
87 ori t1,t0,0x200 # source addr
88 1: cache 0x01,0(t0) # Flush word from data cache
89 cache 0x01,1(t0)
90 cache 0x01,2(t0)
91 cache 0x01,3(t0)
92 nop
93 cache 0x00,0(t0) # Invalidate icache for word
94 cache 0x00,1(t0)
95 cache 0x00,2(t0)
96 cache 0x00,3(t0)
97 nop
98 addi t0,t0,0x20
99 bne t0,t1,1b
100 nop
101 .set mips0 # reset ISA to default
102
103 .endm
104
105 #else
106
107 .macro hal_vectors_init
108 .endm
109
110 #endif
111
112 #------------------------------------------------------------------------------
113 # Monitor initialization.
114
115 #ifndef CYGPKG_HAL_MIPS_MON_DEFINED
116
117 #if defined(CYG_HAL_STARTUP_ROM) || \
118 ( defined(CYG_HAL_STARTUP_RAM) && \
119 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
120
121 # If we are starting up from ROM, or we are starting in
122 # RAM and NOT using a ROM monitor, initialize the VSR table.
123
124 .macro hal_mon_init
125 hal_vectors_init
126 # Set default exception VSR for all vectors
127 ori a0,zero,CYGNUM_HAL_VSR_COUNT
128 la a1,__default_exception_vsr
129 la a2,hal_vsr_table
130 1: sw a1,0(a2)
131 addi a2,a2,4
132 addi a0,a0,-1
133 bne a0,zero,1b
134 nop
135
136 # Now set special VSRs
137 la a0,hal_vsr_table
138 # Set interrupt VSR
139 la a1,__default_interrupt_vsr
140 sw a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0)
141 # Add special handler on breakpoint vector to allow GDB and
142 # GCC to both use 'break' without conflicts.
143 la a1,__break_vsr_springboard
144 sw a1,CYGNUM_HAL_VECTOR_BREAKPOINT*4(a0)
145 # Set exception handler on special vectors
146 # FIXME: Should use proper definitions
147 la a1,__default_exception_vsr
148 sw a1,32*4(a0) # debug
149 sw a1,33*4(a0) # utlb
150 sw a1,34*4(a0) # nmi
151 .endm
152
153 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
154
155 # Initialize the VSR table entries
156 # We only take control of the interrupt vector,
157 # the rest are left to the ROM for now...
158
159 .macro hal_mon_init
160 hal_vectors_init
161 # Set interrupt VSR
162 la a0,hal_vsr_table
163 la a1,__default_interrupt_vsr
164 sw a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0)
165 .endm
166
167 #else
168
169 .macro hal_mon_init
170 hal_vectors_init
171 .endm
172
173 #endif
174
175 #define CYGPKG_HAL_MIPS_MON_DEFINED
176 #endif
177
178 #------------------------------------------------------------------------------
179
180 #if !defined(CYG_HAL_STARTUP_RAM)
181 .macro hal_memc_init
182 // Only initialize the SDRAM controller when running in ROM
183 .extern hal_memc_setup
184 lar t0,hal_memc_setup
185 jalr t0
186 nop
187 .endm
188 #define CYGPKG_HAL_MIPS_MEMC_DEFINED
189 #endif
190
191 #------------------------------------------------------------------------------
192 # Decide whether the VSR table is defined externally, or is to be defined
193 # here.
194
195 ## ISR tables are defined in platform.S
196 #define CYG_HAL_MIPS_ISR_TABLES_DEFINED
197
198 ## VSR table is at a fixed RAM address defined by the linker script
199 #define CYG_HAL_MIPS_VSR_TABLE_DEFINED
200
201 ##-----------------------------------------------------------------------------
202 ## For chaining, use the calculated cause vector number.
203
204 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
205 .macro hal_intc_translate inum,vnum
206 move \vnum,\inum # Vector == interrupt number
207 .endm
208 #define CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
209 #endif
210
211 ##-----------------------------------------------------------------------------
212 #ifdef CYG_STARTUP_ROM
213
214 ## Initial SR value for use in ROM:
215 ## CP0 usable
216 ## Vectors in RAM
217 ## FP registers are 32 bit
218 ## All hw ints disabled
219 #define INITIAL_SR 0x30000000
220
221 #else
222
223 ## Initial SR value for use standalone:
224 ## CP0 usable
225 ## Vectors to RAM
226 ## FP registers are 32 bit
227 ## All hw ints disabled
228 #define INITIAL_SR 0x30000000
229
230 #endif
231
232 #------------------------------------------------------------------------------
233 #endif // ifndef CYGONCE_HAL_PLATFORM_INC
234 # end of platform.inc