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comparison packages/hal/sh/arch/current/include/hal_cache.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
parents 0c2b7be0d798
children e0c0827131d1
comparison
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133:98d71f4d8243 134:d2f49caf9e38
48 //####DESCRIPTIONEND#### 48 //####DESCRIPTIONEND####
49 // 49 //
50 //============================================================================= 50 //=============================================================================
51 51
52 #include <pkgconf/system.h> 52 #include <pkgconf/system.h>
53 #include <pkgconf/hal.h>
54 #include <cyg/infra/cyg_type.h>
55 #include <cyg/hal/hal_io.h> // HAL_READ/WRITE macros
56 53
57 #include CYGBLD_HAL_CPU_MODULES_H // cache module specs 54 #include <cyg/hal/var_cache.h> // get variant cache handling
58 55
59 #include <cyg/hal/sh_regs.h> // CYGARC_REG_ definitions
60
61 //-----------------------------------------------------------------------------
62 // Cache dimensions - one unified cache
63
64 #define HAL_CACHE_UNIFIED
65
66 #define HAL_UCACHE_SIZE CYGARC_SH_MOD_CAC_SIZE
67 #define HAL_UCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_LINE_SIZE
68 #define HAL_UCACHE_WAYS CYGARC_SH_MOD_CAC_WAYS
69
70 // Cache addressing information
71 #define CYGARC_REG_CACHE_ADDRESS_BASE CYGARC_SH_MOD_CAC_ADDRESS_BASE
72 #define CYGARC_REG_CACHE_ADDRESS_TOP CYGARC_SH_MOD_CAC_ADDRESS_TOP
73 #define CYGARC_REG_CACHE_ADDRESS_STEP CYGARC_SH_MOD_CAC_ADDRESS_STEP
74
75 // Writing this to a cache address entry forces a flush of the line if
76 // it is dirty.
77 #define CYGARC_REG_CACHE_ADDRESS_FLUSH CYGARC_SH_MOD_CAC_ADDRESS_FLUSH
78
79 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
80
81 //-----------------------------------------------------------------------------
82 // Global control of cache
83
84 // This is all handled in assembly (see vectors.S) due to a requirement about
85 // not fiddling the cache from cachable memory.
86
87 externC void cyg_hal_cache_enable(void);
88 externC void cyg_hal_cache_disable(void);
89 externC void cyg_hal_cache_invalidate_all(void);
90 externC void cyg_hal_cache_sync(void);
91 externC void cyg_hal_cache_sync_region(cyg_haladdress base,
92 cyg_haladdrword len);
93 externC void cyg_hal_cache_write_mode(int mode);
94
95 // Enable the cache
96 #define HAL_UCACHE_ENABLE() cyg_hal_cache_enable()
97
98 // Disable the cache
99 #define HAL_UCACHE_DISABLE() cyg_hal_cache_disable()
100
101 // Invalidate the entire cache
102 #define HAL_UCACHE_INVALIDATE_ALL() cyg_hal_cache_invalidate_all()
103
104 // Synchronize the contents of the cache with memory.
105 #define HAL_UCACHE_SYNC() cyg_hal_cache_sync()
106
107 // Query the state of the cache (does not affect the caching)
108 #define HAL_UCACHE_IS_ENABLED(_state_) \
109 CYG_MACRO_START \
110 HAL_READ_UINT32(CYGARC_REG_CCR, (_state_)); \
111 (_state_) &= ~CYGARC_REG_CCR_CE; \
112 CYG_MACRO_END
113
114 // Set the cache refill burst size
115 //#define HAL_UCACHE_BURST_SIZE(_size_)
116
117 // Set the cache write mode
118 #define HAL_UCACHE_WRITE_MODE( _mode_ ) \
119 CYG_MACRO_START \
120 cyg_uint32 _m_; \
121 if (HAL_UCACHE_WRITETHRU_MODE == _mode_) \
122 _m_ = CYGARC_REG_CCR_WT; \
123 else \
124 _m_ = CYGARC_REG_CCR_CB; \
125 cyg_hal_cache_write_mode(_m_); \
126 CYG_MACRO_END
127
128 #define HAL_UCACHE_WRITETHRU_MODE 0
129 #define HAL_UCACHE_WRITEBACK_MODE 1
130
131 // This macro allows the client to specify separate modes for the two
132 // regions.
133 #define HAL_UCACHE_WRITE_MODE_SH( _mode_ ) cyg_hal_cache_write_mode(_mode_)
134
135 // Load the contents of the given address range into the cache
136 // and then lock the cache so that it stays there.
137 //#define HAL_UCACHE_LOCK(_base_, _size_)
138
139 // Undo a previous lock operation
140 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
141
142 // Unlock entire cache
143 //#define HAL_UCACHE_UNLOCK_ALL()
144
145 //-----------------------------------------------------------------------------
146 // Cache line control
147
148 // Allocate cache lines for the given address range without reading its
149 // contents from memory.
150 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
151
152 // Write dirty cache lines to memory and invalidate the cache entries
153 // for the given address range.
154 #define HAL_UCACHE_FLUSH( _base_ , _size_ ) \
155 cyg_hal_cache_sync_region(_base_, _size_)
156
157 // Invalidate cache lines in the given range without writing to memory.
158 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
159
160 // Write dirty cache lines to memory for the given address range.
161 //#define HAL_UCACHE_STORE( _base_ , _size_ )
162
163
164 // Preread the given range into the cache with the intention of reading
165 // from it later.
166 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
167
168 // Preread the given range into the cache with the intention of writing
169 // to it later.
170 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
171
172 // Allocate and zero the cache lines associated with the given range.
173 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
174
175
176 //-----------------------------------------------------------------------------
177 // Data and instruction cache macros map onto the both-cache macros
178
179 //-----------------------------------------------------------------------------
180 // Global control of data cache
181
182 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
183 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
184 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
185 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
186
187 // Enable the data cache
188 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
189
190 // Disable the data cache
191 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
192
193 // Invalidate the entire cache
194 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
195
196 // Synchronize the contents of the cache with memory.
197 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
198
199 // Query the state of the data cache
200 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
201
202 // Set the data cache refill burst size
203 //#define HAL_DCACHE_BURST_SIZE(_size_)
204
205 // Set the data cache write mode
206 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
207
208 //#define HAL_DCACHE_WRITETHRU_MODE 0
209 //#define HAL_DCACHE_WRITEBACK_MODE 1
210
211 // Load the contents of the given address range into the data cache
212 // and then lock the cache so that it stays there.
213 //#define HAL_DCACHE_LOCK(_base_, _size_)
214
215 // Undo a previous lock operation
216 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
217
218 // Unlock entire cache
219 //#define HAL_DCACHE_UNLOCK_ALL()
220
221 //-----------------------------------------------------------------------------
222 // Data cache line control
223
224 // Allocate cache lines for the given address range without reading its
225 // contents from memory.
226 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
227
228 // Write dirty cache lines to memory and invalidate the cache entries
229 // for the given address range.
230 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_, _size_ )
231
232 // Invalidate cache lines in the given range without writing to memory.
233 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
234
235 // Write dirty cache lines to memory for the given address range.
236 //#define HAL_DCACHE_STORE( _base_ , _size_ )
237
238 // Preread the given range into the cache with the intention of reading
239 // from it later.
240 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
241
242 // Preread the given range into the cache with the intention of writing
243 // to it later.
244 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
245
246 // Allocate and zero the cache lines associated with the given range.
247 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
248
249 //-----------------------------------------------------------------------------
250 // Global control of Instruction cache
251
252 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
253 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
254 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
255 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
256
257 // Enable the instruction cache
258 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
259
260 // Disable the instruction cache
261 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
262
263 // Invalidate the entire cache
264 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
265
266
267 // Synchronize the contents of the cache with memory.
268 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
269
270 // Query the state of the instruction cache
271 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
272
273 // Set the instruction cache refill burst size
274 //#define HAL_ICACHE_BURST_SIZE(_size_)
275
276 // Load the contents of the given address range into the instruction cache
277 // and then lock the cache so that it stays there.
278
279 //#define HAL_ICACHE_LOCK(_base_, _size_)
280
281 // Undo a previous lock operation
282 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
283
284 // Unlock entire cache
285 //#define HAL_ICACHE_UNLOCK_ALL()
286
287 //-----------------------------------------------------------------------------
288 // Instruction cache line control
289
290 // Invalidate cache lines in the given range without writing to memory.
291 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
292
293 //-----------------------------------------------------------------------------
294 #endif // ifndef CYGONCE_HAL_CACHE_H 56 #endif // ifndef CYGONCE_HAL_CACHE_H
295 // End of hal_cache.h 57 // End of hal_cache.h