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comparison packages/hal/sh/arch/current/include/hal_intr.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
parents 0c2b7be0d798
children e0c0827131d1
comparison
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133:98d71f4d8243 134:d2f49caf9e38
49 //####DESCRIPTIONEND#### 49 //####DESCRIPTIONEND####
50 // 50 //
51 //========================================================================== 51 //==========================================================================
52 52
53 #include <pkgconf/hal.h> 53 #include <pkgconf/hal.h>
54 #include CYGBLD_HAL_CPU_MODULES_H // INTC module selection 54
55 #include <cyg/hal/var_intr.h>
55 56
56 // More include statements below. First part of this file must be 57 // More include statements below. First part of this file must be
57 // usable for both assembly and C files, so only use defines here. 58 // usable for both assembly and C files, so only use defines here.
58 59
59 //-------------------------------------------------------------------------- 60 //--------------------------------------------------------------------------
60 // SH3 exception vectors. These correspond to VSRs and are the values 61 // SH exception vectors. These correspond to VSRs and are the values
61 // to use for HAL_VSR_GET/SET 62 // to use for HAL_VSR_GET/SET
62 // 63 //
63 // Note that exceptions are decoded - there is a VSR slot for each exception 64 // Note that exceptions are decoded - there is a VSR slot for each exception
64 // source, while interrupts are handled via the same VSR. 65 // source, while interrupts are handled via the same VSR.
65 66
70 #define CYGNUM_HAL_VECTOR_INITIAL_WRITE 4 // initial page write 71 #define CYGNUM_HAL_VECTOR_INITIAL_WRITE 4 // initial page write
71 #define CYGNUM_HAL_VECTOR_TLBERROR_ACCESS 5 // TLB prot violation l 72 #define CYGNUM_HAL_VECTOR_TLBERROR_ACCESS 5 // TLB prot violation l
72 #define CYGNUM_HAL_VECTOR_TLBERROR_WRITE 6 // TLB prot violation s 73 #define CYGNUM_HAL_VECTOR_TLBERROR_WRITE 6 // TLB prot violation s
73 #define CYGNUM_HAL_VECTOR_DATA_ACCESS 7 // address error (load) 74 #define CYGNUM_HAL_VECTOR_DATA_ACCESS 7 // address error (load)
74 #define CYGNUM_HAL_VECTOR_DATA_WRITE 8 // address error (store) 75 #define CYGNUM_HAL_VECTOR_DATA_WRITE 8 // address error (store)
75 // define CYGNUM_HAL_VECTOR_RESERVED_9 9 76 // RESERVED 9-10
76 // define CYGNUM_HAL_VECTOR_RESERVED_10 10
77 #define CYGNUM_HAL_VECTOR_TRAP 11 // unconditional trap 77 #define CYGNUM_HAL_VECTOR_TRAP 11 // unconditional trap
78 #define CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION 12 // reserved instruction 78 #define CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION 12 // reserved instruction
79 #define CYGNUM_HAL_VECTOR_ILLEGAL_SLOT_INSTRUCTION 13 79 #define CYGNUM_HAL_VECTOR_ILLEGAL_SLOT_INSTRUCTION 13
80 // illegal instruction in delay slot 80 // illegal instruction in delay slot
81 // define CYGNUM_HAL_VECTOR_RESERVED_14 14 81 #define CYGNUM_HAL_VECTOR_NMI 14 // NMI
82 #define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 15 // user breakpoint 82 #define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 15 // user breakpoint
83 83
84 #define CYG_VECTOR_IS_INTERRUPT(v) \
85 (CYGNUM_HAL_VECTOR_INSTRUCTION_BP < (v))
86
87 #define CYGNUM_HAL_VECTOR_INTERRUPT 16 // all interrupts 84 #define CYGNUM_HAL_VECTOR_INTERRUPT 16 // all interrupts
88 85
86 #ifndef CYG_VECTOR_IS_INTERRUPT
87 # define CYG_VECTOR_IS_INTERRUPT(v) (CYGNUM_HAL_VECTOR_INSTRUCTION_BP < (v))
88 #endif
89
89 #define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_POWERON 90 #define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_POWERON
90 #define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_INTERRUPT 91 #ifndef CYGNUM_HAL_VSR_MAX
92 # define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_INTERRUPT
93 #endif
91 #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 ) 94 #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 )
92 95
93 #define CYGNUM_HAL_VSR_EXCEPTION_COUNT (CYGNUM_HAL_VECTOR_INSTRUCTION_BP-CYGNUM_HAL_VECTOR_POWERON+1) 96 #ifndef CYGNUM_HAL_VSR_EXCEPTION_COUNT
94 97 # define CYGNUM_HAL_VSR_EXCEPTION_COUNT (CYGNUM_HAL_VECTOR_INSTRUCTION_BP-CYGNUM_HAL_VECTOR_POWERON+1)
95 98 #endif
96 99
97 // The decoded interrupts. 100 // The decoded interrupts.
98 #define CYGNUM_HAL_INTERRUPT_NMI 0 101 #define CYGNUM_HAL_INTERRUPT_NMI 0
99 #define CYGNUM_HAL_INTERRUPT_RESERVED_1E0 1 102 #define CYGNUM_HAL_INTERRUPT_RESERVED_1E0 1
100 #define CYGNUM_HAL_INTERRUPT_LVL0 2 103 #define CYGNUM_HAL_INTERRUPT_LVL0 2
126 #define CYGNUM_HAL_INTERRUPT_SCI_TEI 28 129 #define CYGNUM_HAL_INTERRUPT_SCI_TEI 28
127 #define CYGNUM_HAL_INTERRUPT_WDT_ITI 29 130 #define CYGNUM_HAL_INTERRUPT_WDT_ITI 29
128 #define CYGNUM_HAL_INTERRUPT_REF_RCMI 30 131 #define CYGNUM_HAL_INTERRUPT_REF_RCMI 30
129 #define CYGNUM_HAL_INTERRUPT_REF_ROVI 31 132 #define CYGNUM_HAL_INTERRUPT_REF_ROVI 31
130 133
131 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_REF_ROVI 134 #ifndef CYGNUM_HAL_ISR_MAX
132 135 # define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_REF_ROVI
133 //---------------------------------------------------------------------------- 136 #endif
134 // Additional vectors provided by INTC V2 137
135
136 //#ifdef CYGARC_SH_MOD_INTC_V2 // FIXME
137 #define CYGNUM_HAL_INTERRUPT_RESERVED_5C0 32
138 #define CYGNUM_HAL_INTERRUPT_HUDI_HUDI 33
139 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 34
140 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ1 35
141 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ2 36
142 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ3 37
143 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ4 38
144 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ5 39
145 #define CYGNUM_HAL_INTERRUPT_RESERVED_6C0 40
146 #define CYGNUM_HAL_INTERRUPT_RESERVED_6E0 41
147 #define CYGNUM_HAL_INTERRUPT_PINT_PINT07 42
148 #define CYGNUM_HAL_INTERRUPT_PINT_PINT8F 43
149 #define CYGNUM_HAL_INTERRUPT_RESERVED_740 44
150 #define CYGNUM_HAL_INTERRUPT_RESERVED_760 45
151 #define CYGNUM_HAL_INTERRUPT_RESERVED_780 46
152 #define CYGNUM_HAL_INTERRUPT_RESERVED_7A0 47
153 #define CYGNUM_HAL_INTERRUPT_RESERVED_7C0 48
154 #define CYGNUM_HAL_INTERRUPT_RESERVED_7E0 59
155 #define CYGNUM_HAL_INTERRUPT_DMAC_DEI0 50
156 #define CYGNUM_HAL_INTERRUPT_DMAC_DEI1 51
157 #define CYGNUM_HAL_INTERRUPT_DMAC_DEI2 52
158 #define CYGNUM_HAL_INTERRUPT_DMAC_DEI3 53
159 #define CYGNUM_HAL_INTERRUPT_IRDA_ERI1 54
160 #define CYGNUM_HAL_INTERRUPT_IRDA_RXI1 55
161 #define CYGNUM_HAL_INTERRUPT_IRDA_BRI1 56
162 #define CYGNUM_HAL_INTERRUPT_IRDA_TXI1 57
163 #define CYGNUM_HAL_INTERRUPT_SCIF_ERI2 58
164 #define CYGNUM_HAL_INTERRUPT_SCIF_RXI2 59
165 #define CYGNUM_HAL_INTERRUPT_SCIF_BRI2 60
166 #define CYGNUM_HAL_INTERRUPT_SCIF_TXI2 61
167 #define CYGNUM_HAL_INTERRUPT_ADC_ADI 62
168
169 #ifdef CYGARC_SH_MOD_INTC_V2 // FIXME
170
171 #undef CYGNUM_HAL_ISR_MAX
172 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_ADC_ADI
173
174 #endif // CYGARC_SH_MOD_INTC_V2
175
176 //----------------------------------------------------------------------------
177 // Additional vectors provided by INTC V3
178
179 //#ifdef CYGARC_SH_MOD_INTC_V3 // FIXME
180 #define CYGNUM_HAL_INTERRUPT_LCDC_LCDI 63
181 #define CYGNUM_HAL_INTERRUPT_PCC_PCC0 64
182 #define CYGNUM_HAL_INTERRUPT_PCC_PCC1 65
183
184 #ifdef CYGARC_SH_MOD_INTC_V3 // FIXME
185
186 #undef CYGNUM_HAL_ISR_MAX
187 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_PCC_PCC1
188
189 #endif // CYGARC_SH_MOD_INTC_V3
190
191 // CYGNUM_HAL_ISR_COUNT must match CYG_ISR_TABLE_SIZE defined in vectors.S.
192 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_NMI 138 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_NMI
193 #define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 ) 139 #define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1 )
194 140
141 // The vector used by the Real time clock
142 #ifndef CYGNUM_HAL_INTERRUPT_RTC
143 # define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMU0_TUNI0
144 #endif
145
146 //--------------------------------------------------------------------------
195 // Exception vectors. These are the values used when passed out to an 147 // Exception vectors. These are the values used when passed out to an
196 // external exception handler using cyg_hal_deliver_exception() 148 // external exception handler using cyg_hal_deliver_exception()
197 149
198 // The exception indexes are EXPEVT/0x20 150 // The exception indexes are EXPEVT/0x20. Variants may define additional
151 // exception vectors.
199 152
200 #define CYGNUM_HAL_EXCEPTION_POWERON 0 // power-on 153 #define CYGNUM_HAL_EXCEPTION_POWERON 0 // power-on
201 #define CYGNUM_HAL_EXCEPTION_RESET 1 // reset 154 #define CYGNUM_HAL_EXCEPTION_RESET 1 // reset
202 #define CYGNUM_HAL_EXCEPTION_TLBMISS_ACCESS 2 // TLB-miss/invalid load 155 #define CYGNUM_HAL_EXCEPTION_TLBMISS_ACCESS 2 // TLB-miss/invalid load
203 #define CYGNUM_HAL_EXCEPTION_TLBMISS_WRITE 3 // TLB-miss/invalid store 156 #define CYGNUM_HAL_EXCEPTION_TLBMISS_WRITE 3 // TLB-miss/invalid store
204 #define CYGNUM_HAL_EXCEPTION_INITIAL_WRITE 4 // initial page write 157 #define CYGNUM_HAL_EXCEPTION_INITIAL_WRITE 4 // initial page write
205 #define CYGNUM_HAL_EXCEPTION_TLBERROR_ACCESS 5 // TLB prot violation l 158 #define CYGNUM_HAL_EXCEPTION_TLBERROR_ACCESS 5 // TLB prot violation l
206 #define CYGNUM_HAL_EXCEPTION_TLBERROR_WRITE 6 // TLB prot violation s 159 #define CYGNUM_HAL_EXCEPTION_TLBERROR_WRITE 6 // TLB prot violation s
207 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS 7 // address error (load) 160 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS 7 // address error (load)
208 #define CYGNUM_HAL_EXCEPTION_DATA_WRITE 8 // address error (store) 161 #define CYGNUM_HAL_EXCEPTION_DATA_WRITE 8 // address error (store)
209 // define CYGNUM_HAL_EXCEPTION_RESERVED_9 9
210 // define CYGNUM_HAL_EXCEPTION_RESERVED_10 10
211 #define CYGNUM_HAL_EXCEPTION_TRAP 11 // unconditional trap 162 #define CYGNUM_HAL_EXCEPTION_TRAP 11 // unconditional trap
212 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION 12 // reserved instruction 163 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION 12 // reserved instruction
213 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_SLOT_INSTRUCTION 13 164 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_SLOT_INSTRUCTION 13
214 // illegal instruction in delay slot 165 // illegal instruction in delay slot
215 // define CYGNUM_HAL_EXCEPTION_RESERVED_14 14
216 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP 15 // user breakpoint 166 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP 15 // user breakpoint
217 167
218 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_POWERON 168 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_POWERON
219 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP 169
170 #ifndef CYGNUM_HAL_EXCEPTION_MAX
171 # define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP
172 #endif
173
220 #define CYGNUM_HAL_EXCEPTION_COUNT \ 174 #define CYGNUM_HAL_EXCEPTION_COUNT \
221 ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 ) 175 ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
222
223 // The vector used by the Real time clock
224 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMU0_TUNI0
225 176
226 #ifndef __ASSEMBLER__ 177 #ifndef __ASSEMBLER__
227 178
228 #include <cyg/infra/cyg_type.h> 179 #include <cyg/infra/cyg_type.h>
229 180