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comparison packages/hal/sh/sh3/current/include/mod_regs_ubc.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
parents
children 0d2b193a635f
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133:98d71f4d8243 134:d2f49caf9e38
1 //=============================================================================
2 //
3 // mod_regs_ubc.h
4 //
5 // UBC (user break controller) Module register definitions
6 //
7 //=============================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Red Hat eCos Public License
12 // Version 1.1 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://www.redhat.com/
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos - Embedded Configurable Operating System,
22 // released September 30, 1998.
23 //
24 // The Initial Developer of the Original Code is Red Hat.
25 // Portions created by Red Hat are
26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
27 // All Rights Reserved.
28 // -------------------------------------------
29 //
30 //####COPYRIGHTEND####
31 //=============================================================================
32 //#####DESCRIPTIONBEGIN####
33 //
34 // Author(s): jskov
35 // Contributors:jskov
36 // Date: 2000-10-30
37 //
38 //####DESCRIPTIONEND####
39 //
40 //=============================================================================
41
42 //--------------------------------------------------------------------------
43 // User Break Control
44 #define CYGARC_REG_BRCR 0xffffff98 // 16 bit
45
46 #define CYGARC_REG_BARA 0xffffffb0 // 32 bit
47 #define CYGARC_REG_BAMRA 0xffffffb4 // 8 bit (v1) / 32 bit
48 #define CYGARC_REG_BBRA 0xffffffb8 // 16 bit
49 #define CYGARC_REG_BASRA 0xffffffe4 // 8 bit
50
51 #define CYGARC_REG_BARB 0xffffffa0 // 32 bit
52 #define CYGARC_REG_BAMRB 0xffffffa4 // 8 bit (v1) / 32 bit
53 #define CYGARC_REG_BASRB 0xffffffe8 // 8 bit
54 #define CYGARC_REG_BBRB 0xffffffa8 // 16 bit
55 #define CYGARC_REG_BDRB 0xffffff90 // 32 bit
56 #define CYGARC_REG_BDMRB 0xffffff94 // 32 bit
57
58
59 #define CYGARC_REG_BRCR_CMFA 0x8000 // condition match flag A
60 #define CYGARC_REG_BRCR_CMFB 0x4000 // condition match flag B
61 #define CYGARC_REG_BRCR_PCBA 0x0400 // post execute channel A
62 #define CYGARC_REG_BRCR_DBEB 0x0080 // data break enable B
63 #define CYGARC_REG_BRCR_PCBB 0x0040 // post execute channel B
64 #define CYGARC_REG_BRCR_SEQ 0x0008 // sequence condition select
65
66 #if (CYGARC_SH_MOD_UBC == 1)
67 #define CYGARC_REG_BAMRA_BASMA 0x04 // BASRA masked
68 #define CYGARC_REG_BAMRA_BARA_UNMASKED 0x00 // BARA not masked
69 #define CYGARC_REG_BAMRA_BARA_10BIT 0x01 // Lowest 10 bit masked
70 #define CYGARC_REG_BAMRA_BARA_12BIT 0x02 // Lowest 12 bit masked
71 #define CYGARC_REG_BAMRA_BARA_MASKED 0x03 // All bits masked
72 #else
73 // mask is fully configurable in other versions of the UBC
74 #endif
75
76 #define CYGARC_REG_BBRA_DFETCH 0x0020 // Break on DFETCH
77 #define CYGARC_REG_BBRA_IFETCH 0x0010 // Break on IFETCH
78 #define CYGARC_REG_BBRA_WRITE 0x0008 // Break on WRITE
79 #define CYGARC_REG_BBRA_READ 0x0004 // Break on READ
80 #define CYGARC_REG_BBRA_SIZE_LONG 0x0003 // Break on long access
81 #define CYGARC_REG_BBRA_SIZE_WORD 0x0002 // Break on word access
82 #define CYGARC_REG_BBRA_SIZE_BYTE 0x0001 // Break on byte access
83 #define CYGARC_REG_BBRA_SIZE_ANY 0x0000 // Break on any size
84
85
86 //----------------------------------------------------------------------------
87 // Other types
88 #if (CYGARC_SH_MOD_UBC >= 3)
89 #define CYGARC_REG_BETR 0xffffff9c // 16 bit
90 #define CYGARC_REG_BRSR 0xffffffac // 32 bit
91 #define CYGARC_REG_BRDR 0xffffffbc // 32 bit
92
93 #define CYGARC_REG_BBRA_DMA 0x0080 // Break on DMAC cycle
94 #define CYGARC_REG_BBRA_CPU 0x0040 // Break on CPU cycle
95 #endif