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comparison packages/hal/sh/sh3/current/include/variant.inc @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children 289bf90c6a9b
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133:98d71f4d8243 134:d2f49caf9e38
1 #ifndef CYGONCE_HAL_VARIANT_INC
2 #define CYGONCE_HAL_VARIANT_INC
3 ##=============================================================================
4 ##
5 ## variant.inc
6 ##
7 ## SH3 variant assembler header file
8 ##
9 ##=============================================================================
10 #####COPYRIGHTBEGIN####
11 #
12 # -------------------------------------------
13 # The contents of this file are subject to the Red Hat eCos Public License
14 # Version 1.1 (the "License"); you may not use this file except in
15 # compliance with the License. You may obtain a copy of the License at
16 # http://www.redhat.com/
17 #
18 # Software distributed under the License is distributed on an "AS IS"
19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
20 # License for the specific language governing rights and limitations under
21 # the License.
22 #
23 # The Original Code is eCos - Embedded Configurable Operating System,
24 # released September 30, 1998.
25 #
26 # The Initial Developer of the Original Code is Red Hat.
27 # Portions created by Red Hat are
28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
29 # All Rights Reserved.
30 # -------------------------------------------
31 #
32 #####COPYRIGHTEND####
33 ##=============================================================================
34 #######DESCRIPTIONBEGIN####
35 ##
36 ## Author(s): jskov
37 ## Contributors:jskov
38 ## Date: 2000-10-30
39 ## Purpose: SH3 variant definitions and init code
40 ## Description: This file contains various definitions and macros that are
41 ## useful for writing assembly code for the SH3 CPU family.
42 ## Usage:
43 ## #include <cyg/hal/variant.inc>
44 ## ...
45 ##
46 ##
47 ######DESCRIPTIONEND####
48 ##
49 ##=============================================================================
50
51 #include <pkgconf/hal.h>
52 #include <cyg/hal/sh_regs.h>
53
54 #===========================================================================
55 # SR initialization value
56 # zero all bits except:
57 # MD = Processor operation mode field (privileged mode)
58 # I0-3 = Mask out all interrupts but NMI.
59 #
60 # When saving or restoring the state of an exception or interrupt, the bit
61 # CYGARC_REG_SR_RB is also set, switching the register bank. When this bit
62 # is set, interrupts must be disabled.
63 #
64 # Note: We could also use the BL bit to prevent interrupts, but that would
65 # also prevent the use of breakpoints.
66
67 #define CYG_SR (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK)
68 #define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB)
69
70 ##-----------------------------------------------------------------------------
71 ## Hardware init macros
72 #ifndef CYGPKG_HAL_SH_POST_RESET_INIT
73 .macro hal_post_reset_init
74 # Initialize CPU
75 mov.l $nCYG_SR,r1 ! Put CPU in a well-known state
76 ldc r1,sr
77 mov #0,r0
78 mov #CYGARC_REG_CCR,r1 ! Disable cache
79 mov.l r0,@r1
80 mov #CYGARC_REG_MMUCR,r1 ! Disable MMU
81 mov.l r0,@r1
82 mov #CYGARC_REG_BBRA,r1 ! Disable UBC Channel A
83 mov.w r0,@r1
84 mov #CYGARC_REG_BBRB,r1 ! Disable UBC Channel B
85 mov.w r0,@r1
86 mov #CYGARC_REG_BRCR,r1 ! Reset UBC common register
87 mov.w r0,@r1
88 mov.l $CYGARC_REG_TSTR,r1 ! Disable timers
89 mov.b r0,@r1
90 mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources
91 mov.w r0,@r1
92 mov.l $CYGARC_REG_IPRB,r1
93 mov.w r0,@r1
94 #if (CYGARC_SH_MOD_INTC >= 2)
95 mov.l $CYGARC_REG_IPRC,r1
96 mov.w r0,@r1
97 mov.l $CYGARC_REG_IPRD,r1
98 mov.w r0,@r1
99 mov.l $CYGARC_REG_IPRE,r1
100 mov.w r0,@r1
101 #if (CYGARC_SH_MOD_INTC >= 3)
102 mov.l $CYGARC_REG_IPRF,r1
103 mov.w r0,@r1
104 #endif
105 mov.w $nCYG_ICR1_INIT,r0
106 mov.l $CYGARC_REG_ICR1,r1 ! Set interrupt controller to IRQ mode
107 mov.w r0,@r1
108 #endif
109 mov.w $nCYG_WTCSR,r0 ! Clear watchdog
110 mov #CYGARC_REG_WTCSR,r1
111 mov.w r0,@r1
112
113 # Initialize VBR if necessary
114 #if !defined(CYG_HAL_STARTUP_RAM) || \
115 ( defined(CYG_HAL_STARTUP_RAM) && \
116 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
117 mov.l $__reset,r1 ! Set VBR
118 ldc r1,vbr
119 #endif
120 bra 1f
121 nop
122
123 $nCYG_WTCSR:
124 .word 0xa500 ! clear all CSR bits
125
126 .align 2
127 $nCYG_SR:
128 .long CYG_SR
129 $CYGARC_REG_TSTR:
130 .long CYGARC_REG_TSTR
131 $CYGARC_REG_IPRA:
132 .long CYGARC_REG_IPRA
133 $CYGARC_REG_IPRB:
134 .long CYGARC_REG_IPRB
135 #if (CYGARC_SH_MOD_INTC >= 2)
136 $CYGARC_REG_IPRC:
137 .long CYGARC_REG_IPRC
138 $CYGARC_REG_IPRD:
139 .long CYGARC_REG_IPRD
140 $CYGARC_REG_IPRE:
141 .long CYGARC_REG_IPRE
142 $CYGARC_REG_ICR1:
143 .long CYGARC_REG_ICR1
144 $nCYG_ICR1_INIT:
145 .word CYGARC_REG_ICR1_INIT
146 .align 2
147 #endif
148 #if (CYGARC_SH_MOD_INTC >= 3)
149 $CYGARC_REG_IPRF:
150 .long CYGARC_REG_IPRF
151 #endif
152 $__reset:
153 .long __reset
154
155 1:
156 .endm
157 #define CYGPKG_HAL_SH_POST_RESET_INIT
158 #endif
159
160 ##-----------------------------------------------------------------------------
161 ## Interrupt decode macros
162 .macro hal_intc_decode tmp,inum
163 #if (CYGARC_SH_MOD_INTC >= 2)
164 mov.l $nCYGARC_REG_INTEVT2,\tmp
165 #else
166 mov #CYGARC_REG_INTEVT,\tmp
167 #endif
168 mov.l @\tmp,\inum
169 mov #-5,\tmp ! divide cause by 0x20
170 shld \tmp,\inum
171 add #-14,\inum ! adjust so NMI becomes 0
172
173 .endm
174
175 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
176 .macro hal_intc_translate inum,vnum
177 mov #0,\vnum ! Just vector zero is supported
178 .endm
179 #else
180 .macro hal_intc_translate inum,vnum
181 mov \inum,\vnum ! Vector == interrupt number
182 shll2 \vnum ! get from vector number to ISR index
183 .endm
184 #endif
185
186 #------------------------------------------------------------------------------
187 #endif // CYGONCE_HAL_VARIANT_INC
188 # end of variant.inc