--- a/packages/devs/eth/rltk/8139/current/src/if_8139.c
+++ b/packages/devs/eth/rltk/8139/current/src/if_8139.c
@@ -183,24 +183,24 @@ void rltk8139_print_state(struct eth_drv
 #define EEPROM_PG_EEDI          0x02
 #define EEPROM_PG_EEDO          0x01
 #define EEPROM_WR_BUSY_RETRIES  100   // ready wait re-try count
-
-#define	EEPROM_MASK(_param0_,_param1_)            ((_param0_ & _param1_) ? EEPROM_PG_EEDI : 0 )
-
-
-#define EEPROM_WR_DATA(_addr_,_txdata_)           HAL_WRITE_UINT8(_addr_,_txdata_);
-
-#define EEPROM_WR_DATAPULSE(_addr_,_txdata_)      HAL_WRITE_UINT8(_addr_,_txdata_); \
+
+#define	EEPROM_MASK(_param0_,_param1_)            ((_param0_ & _param1_) ? EEPROM_PG_EEDI : 0 )
+
+
+#define EEPROM_WR_DATA(_addr_,_txdata_)           HAL_WRITE_UINT8(_addr_,_txdata_);
+
+#define EEPROM_WR_DATAPULSE(_addr_,_txdata_)      HAL_WRITE_UINT8(_addr_,_txdata_); \
                                                   cyg_thread_delay(0); \
-                                                  HAL_WRITE_UINT8(_addr_,_txdata_ | EEPROM_PG_EESK);
-
-#define EEPROM_RD_DATA(_addr_,_txdata_,_rxdata_)  { \
+                                                  HAL_WRITE_UINT8(_addr_,_txdata_ | EEPROM_PG_EESK);
+
+#define EEPROM_RD_DATA(_addr_,_txdata_,_rxdata_)  { \
                                                   cyg_uint16  read_data; \
-                                                  HAL_WRITE_UINT8(_addr_,_txdata_); \
-                                                  cyg_thread_delay(1); \
+                                                  HAL_WRITE_UINT8(_addr_,_txdata_); \
+                                                  cyg_thread_delay(1); \
                                                   HAL_READ_UINT8(_addr_, read_data); \
-                                                  _rxdata_ <<= 1; \
-                                                  _rxdata_ |= ((read_data & EEPROM_PG_EEDO) ? 0x0001 : 0x0000 ); \
-                                                  HAL_WRITE_UINT8(_addr_,_txdata_ | EEPROM_PG_EESK); }
+                                                  _rxdata_ <<= 1; \
+                                                  _rxdata_ |= ((read_data & EEPROM_PG_EEDO) ? 0x0001 : 0x0000 ); \
+                                                  HAL_WRITE_UINT8(_addr_,_txdata_ | EEPROM_PG_EESK); }
 #endif
 
 /*
@@ -1296,11 +1296,11 @@ rltk8139_deliver(struct eth_drv_sc *sc)
     rltk8139_reset(sc);
     return;
   }
-
+
   if (status & IR_FUN) {
     /*
-     * Packet underrun or link change interrupt.
-     * A cable was packet underrun or re-connected ?
+     * Packet underrun or link change interrupt.
+     * A cable was packet underrun or re-connected ?
      */
 #ifdef DEBUG_RLTK8139_DRIVER
     diag_printf("rltk8139_deliver(%s): packet underrun or link change\n",
@@ -1380,8 +1380,8 @@ rltk8139_print_state(struct eth_drv_sc *
 }
 #endif
 
-
-#ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
+
+#ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
 /*
  * Read mac_address from EEPROM.
  */
@@ -1391,45 +1391,45 @@ rltk8139_eeprom_read( char *rtl_addr, cy
 cyg_uint8   read_data;                   // read from eeprom bit data
 cyg_uint8   org_param;                   // original register parameter
 cyg_uint8   mask_bit8;                   // mask bit
-int         icount;                      // for loop counter
-
+int         icount;                      // for loop counter
+
     // get old parameter
     HAL_READ_UINT8( rtl_addr, org_param );
-
-    // ready
+
+    // ready
     EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON );
-
-    // set command
+
+    // set command
     mask_bit8 = 0x04;
-    for(icount = 0; icount < 3; icount++){
+    for(icount = 0; icount < 3; icount++){
         EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_cmd ));
-        mask_bit8 >>= 1;
+        mask_bit8 >>= 1;
     }
 
-    // set address
+    // set address
     mask_bit8 = 0x20;
     for(icount = 0; icount < 6; icount++){
         EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_addr ));
-        mask_bit8 >>= 1;
-    }
-
-    // read data
-    read_data = 0;
-    for(icount = 0; icount < 16; icount++){
+        mask_bit8 >>= 1;
+    }
+
+    // read data
+    read_data = 0;
+    for(icount = 0; icount < 16; icount++){
         EEPROM_RD_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS, read_data );
-    }
-
-    // close
+    }
+
+    // close
     EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
     EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
-
+
     // put old parameter
     HAL_WRITE_UINT8(rtl_addr, org_param);
-
+
     return(read_data);
 }
-
-
+
+
 /*
  * Write in mac_address at EEPROM.
  */
@@ -1440,16 +1440,16 @@ cyg_uint8   read_data;                  
 cyg_uint8   org_param;                   // original register parameter
 cyg_uint8   mask_bit8;                   // mask bit
 cyg_uint16  mask_bit16;                  // mask bit for write data
-int         icount;                      // for loop counter
-
+int         icount;                      // for loop counter
+
     // get old parameter
     HAL_READ_UINT8( rtl_addr, org_param );
-
-    // ready
+
+    // ready
     EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
     EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EESK );
     EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
-
+
     // set EWEN (eeprom write enable)
     EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_PG_EEDI );
     EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
@@ -1461,39 +1461,39 @@ int         icount;                     
     EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
     EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
     EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON );
-
-    // set command
+
+    // set command
     mask_bit8 = 0x04;
     for(icount = 0; icount < 3; icount++){
         EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_cmd ));
-        mask_bit8 >>= 1;
+        mask_bit8 >>= 1;
     }
 
-    // set address
+    // set address
     mask_bit8 = 0x20;
     for(icount = 0; icount < 6; icount++){
         EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_addr ));
-        mask_bit8 >>= 1;
-    }
-
-    // set data
+        mask_bit8 >>= 1;
+    }
+
+    // set data
     mask_bit16 = 0x8000;
     for(icount = 0; icount < 16; icount++){
         EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit16, src_data ));
-        mask_bit16 >>= 1;
-    }
-
-    // close
+        mask_bit16 >>= 1;
+    }
+
+    // close
     EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
     EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EESK );
     EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
-
+
     // write ready check
     EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
-
-    // wait busy disable
-    icount = 0;
-    while( 1 ){
+
+    // wait busy disable
+    icount = 0;
+    while( 1 ){
         cyg_thread_delay( 1 );
         HAL_WRITE_UINT8( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_PG_EESK );
         HAL_WRITE_UINT8( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
@@ -1501,13 +1501,13 @@ int         icount;                     
         if(( read_data & EEPROM_PG_EEDO ) != 0 ){
             break;
         }
-        if( icount++ >= EEPROM_WR_BUSY_RETRIES ){
+        if( icount++ >= EEPROM_WR_BUSY_RETRIES ){
             diag_printf("EEPROM write wait error adr=0x%02x data=0x%04x\n", eeprom_addr, src_data );
-            break;
-        }
+            break;
+        }
     }
     HAL_WRITE_UINT8( rtl_addr, EEPROM_PG_ON );
-
+
     // put old parameter
     HAL_WRITE_UINT8( rtl_addr, org_param );
 }