Mercurial > ecos-v3_0-branch
view packages/hal/arm/pid/current/include/hal_cache.h @ 64:c38311975d4f ecos-sw-2000-01-28
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
| author | jlarmour |
|---|---|
| date | Fri, 28 Jan 2000 04:59:39 +0000 |
| parents | 443894e2e912 |
| children | bf00f99aec69 |
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#ifndef CYGONCE_HAL_CACHE_H #define CYGONCE_HAL_CACHE_H //============================================================================= // // hal_cache.h // // HAL cache control API // //============================================================================= //####COPYRIGHTBEGIN#### // // ------------------------------------------- // The contents of this file are subject to the Red Hat eCos Public License // Version 1.0 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://sourceware.cygnus.com/ecos // // Software distributed under the License is distributed on an // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the // License for the specific language governing rights and limitations under // the License. // // The Original Code is eCos - Embedded Configurable Operating System, // released September 30, 1998. // // The Initial Developer of the Original Code is Red Hat. // Portions created by Red Hat are // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. // All Rights Reserved. // ------------------------------------------- // //####COPYRIGHTEND#### //============================================================================= //#####DESCRIPTIONBEGIN#### // // Author(s): nickg, gthomas // Contributors: nickg, gthomas // Date: 1998-09-28 // Purpose: Cache control API // Description: The macros defined here provide the HAL APIs for handling // cache control operations. // Usage: // #include <cyg/hal/hal_cache.h> // ... // // //####DESCRIPTIONEND#### // //============================================================================= #include <cyg/infra/cyg_type.h> //----------------------------------------------------------------------------- // Cache dimensions // Data cache #define HAL_DCACHE_SIZE 0 // Size of data cache in bytes #define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line #define HAL_DCACHE_WAYS 0 // Associativity of the cache // Instruction cache #define HAL_ICACHE_SIZE 0 // Size of cache in bytes #define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line #define HAL_ICACHE_WAYS 0 // Associativity of the cache #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) //----------------------------------------------------------------------------- // Global control of data cache // Enable the data cache #define HAL_DCACHE_ENABLE() // Disable the data cache #define HAL_DCACHE_DISABLE() // Invalidate the entire cache #define HAL_DCACHE_INVALIDATE_ALL() // Synchronize the contents of the cache with memory. #define HAL_DCACHE_SYNC() // Purge contents of data cache #define HAL_DCACHE_PURGE_ALL() // Set the data cache refill burst size //#define HAL_DCACHE_BURST_SIZE(_size_) // Set the data cache write mode //#define HAL_DCACHE_WRITE_MODE( _mode_ ) //#define HAL_DCACHE_WRITETHRU_MODE 0 //#define HAL_DCACHE_WRITEBACK_MODE 1 // Load the contents of the given address range into the data cache // and then lock the cache so that it stays there. //#define HAL_DCACHE_LOCK(_base_, _size_) // Undo a previous lock operation //#define HAL_DCACHE_UNLOCK(_base_, _size_) // Unlock entire cache //#define HAL_DCACHE_UNLOCK_ALL() //----------------------------------------------------------------------------- // Data cache line control // Allocate cache lines for the given address range without reading its // contents from memory. //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) // Write dirty cache lines to memory and invalidate the cache entries // for the given address range. //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) // Invalidate cache lines in the given range without writing to memory. //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) // Write dirty cache lines to memory for the given address range. //#define HAL_DCACHE_STORE( _base_ , _size_ ) // Preread the given range into the cache with the intention of reading // from it later. //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) // Preread the given range into the cache with the intention of writing // to it later. //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) // Allocate and zero the cache lines associated with the given range. //#define HAL_DCACHE_ZERO( _base_ , _size_ ) //----------------------------------------------------------------------------- // Global control of Instruction cache // Enable the instruction cache #define HAL_ICACHE_ENABLE() // Disable the instruction cache #define HAL_ICACHE_DISABLE() // Invalidate the entire cache #define HAL_ICACHE_INVALIDATE_ALL() // Synchronize the contents of the cache with memory. #define HAL_ICACHE_SYNC() // Set the instruction cache refill burst size //#define HAL_ICACHE_BURST_SIZE(_size_) // Load the contents of the given address range into the instruction cache // and then lock the cache so that it stays there. //#define HAL_ICACHE_LOCK(_base_, _size_) // Undo a previous lock operation //#define HAL_ICACHE_UNLOCK(_base_, _size_) // Unlock entire cache //#define HAL_ICACHE_UNLOCK_ALL() //----------------------------------------------------------------------------- // Instruction cache line control // Invalidate cache lines in the given range without writing to memory. //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) //----------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_CACHE_H // End of hal_cache.h
