# HG changeset patch # User asl # Date 1216752736 0 # Node ID db4d5a0ddeb4a0b204f3ac008bdea3eb361d82d6 # Parent a530d38027e362ded471c1bb512b8738237d8a6c * cdl/hal_arm_lpc2xxx.cdl: Added option CYGHWR_HAL_ARM_LPC2XXX_VARIANT_VERSION to identify the variant version because some on-chip peripherals changed slightly in newer veriants. CYGNUM_HAL_ARM_LPC2XXX_PCLK is the pre calculated peripheral clock value. CYGNUM_HAL_ARM_LPC2XXX_XCLK is the pre calculated XCLK value. * include/lpc2xxx_misc.h: Added HAL_LPC2XXX_INIT_CAN() macro fo initialisation of CAN channels (required by CAN driver). Added CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK to define the CAN peripheral clock for CAN driver. * include/lpc2xxx_misc.c: Removed functions hal_lpc_get_cclk() hal_lpc_get_pclk() and hal_lpc_get_xclk() because they are not required and all clock values (CCLK, PCLK and XCLK) are configuration values and pre calculated in CDL file. Added hal_lpc_can_init() function for initialisation of CAN channels. * cdl/hal_arm_lpc2xxx.cdl: add suffix option to denote different versions of LPC2XXX * : dos2unix everything.... diff --git a/packages/hal/arm/lpc2xxx/var/current/ChangeLog b/packages/hal/arm/lpc2xxx/var/current/ChangeLog --- a/packages/hal/arm/lpc2xxx/var/current/ChangeLog +++ b/packages/hal/arm/lpc2xxx/var/current/ChangeLog @@ -1,3 +1,27 @@ +2008-07-21 Uwe Kindler + + * cdl/hal_arm_lpc2xxx.cdl: Added option + CYGHWR_HAL_ARM_LPC2XXX_VARIANT_VERSION to identify the variant version + because some on-chip peripherals changed slightly in newer veriants. + CYGNUM_HAL_ARM_LPC2XXX_PCLK is the pre calculated peripheral clock + value. CYGNUM_HAL_ARM_LPC2XXX_XCLK is the pre calculated XCLK + value. + * include/lpc2xxx_misc.h: Added HAL_LPC2XXX_INIT_CAN() macro fo + initialisation of CAN channels (required by CAN driver). Added + CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK to define the CAN peripheral clock + for CAN driver. + * include/lpc2xxx_misc.c: Removed functions hal_lpc_get_cclk() + hal_lpc_get_pclk() and hal_lpc_get_xclk() because they are not + required and all clock values (CCLK, PCLK and XCLK) are + configuration values and pre calculated in CDL file. + Added hal_lpc_can_init() function for initialisation of CAN + channels. + +2008-05-23 Alexey Shusharin + + * cdl/hal_arm_lpc2xxx.cdl: add suffix option to denote + different versions of LPC2XXX + 2007-08-23 Hans Rosenfeld * include/hal_var_ints.h: use interrupt priority 16 for @@ -8,7 +32,7 @@ 2007-08-17 Hans Rosenfeld +2007-07-10 Uwe Kindler * cdl/hal_arm_lpc2xxx.cdl: Added option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY for diff --git a/packages/hal/arm/lpc2xxx/var/current/cdl/hal_arm_lpc2xxx.cdl b/packages/hal/arm/lpc2xxx/var/current/cdl/hal_arm_lpc2xxx.cdl --- a/packages/hal/arm/lpc2xxx/var/current/cdl/hal_arm_lpc2xxx.cdl +++ b/packages/hal/arm/lpc2xxx/var/current/cdl/hal_arm_lpc2xxx.cdl @@ -110,6 +110,33 @@ cdl_package CYGPKG_HAL_ARM_LPC2XXX { lpc214x has USB) which affect which features should be available in the HAL." } + + cdl_option CYGHWR_HAL_ARM_LPC2XXX_VARIANT_VERSION { + display "LPC2XXX variant version" + flavor data + calculated { + is_substr(CYGHWR_HAL_ARM_LPC2XXX, "LPC21") ? 1 : + is_substr(CYGHWR_HAL_ARM_LPC2XXX, "LPC22") ? 2 : + is_substr(CYGHWR_HAL_ARM_LPC2XXX, "LPC24") ? 4 : 0 + } + description " + This specifies the variant version that the processor + belongs to. Some common characteristics may be + different in newer LPC2xxx versions. I.e. the LPC24xx variants + are significant different from former LPC2xxx variants." + } + + cdl_option CYGHWR_HAL_ARM_LPC2XXX_SUFFIX { + display "Suffix of LPC2XXX device" + flavor data + legal_values { "no_suffix" "00" "01" } + default_value { "no_suffix" } + description " + This option sets the version number of LPC2XXX microcontroller. + To denote different version of LPC2XXX the following suffixes + are used: no suffix, /00, /01. All /01 version contain + enhanced features." + } } # Important! Be very careful changing this value. That will always @@ -130,20 +157,42 @@ cdl_package CYGPKG_HAL_ARM_LPC2XXX { of the ARM vector table." } - cdl_option CYGNUM_HAL_ARM_LPC2XXX_VPBDIV { + cdl_component CYGNUM_HAL_ARM_LPC2XXX_VPBDIV { display "VPB clock divisor" flavor data legal_values { 4 2 1 } default_value { 4 } description " + The VPB Divider determines the relationship between the + processor clock (cclk) and the clock used by peripheral + devices (pclk). The VPB Divider serves two purposes. + The first is to provides peripherals with desired pclk + via VPB bus so that they can operate at the speed chosen for the ARM + processor. In order to achieve this, the VPB bus may be slowed down + to one half or one fourth of the processor clock rate. + Because the VPB bus must work properly at power up (and its timing + cannot be altered if it does not work since the VPB divider control + registers reside on the VPB bus), the default condition at reset is + for the VPB bus to run at one quarter speed. The second purpose of + the VPB Divider is to allow power savings when an application + does not require any peripherals to run at the full processor rate. This option sets the divisor for the VPB clock relative to the processor clock. 4 means that the VPB clock runs at one fourth the processor clock, 2 means that it runs at one half of the processor clock and 1 means that it is the same as the processor clock." + + cdl_option CYGNUM_HAL_ARM_LPC2XXX_PCLK { + display "Peripheral clock" + flavor data + calculated {CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED / CYGNUM_HAL_ARM_LPC2XXX_VPBDIV} + description " + The peripheral clock is the clock derived from the processor clock + speed divided by the VPB clock divisor." + } } - cdl_option CYGNUM_HAL_ARM_LPC2XXX_XCLKDIV { + cdl_component CYGNUM_HAL_ARM_LPC2XXX_XCLKDIV { display "XCLK clock divisor" flavor data legal_values { 4 2 1 } @@ -155,6 +204,15 @@ cdl_package CYGPKG_HAL_ARM_LPC2XXX { at one fourth the processor clock, 2 means that it runs at one half of the processor clock and 1 means that it is the same as the processor clock." + + cdl_option CYGNUM_HAL_ARM_LPC2XXX_XCLK { + display "Clock on XCLK pin" + flavor data + calculated {CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED / CYGNUM_HAL_ARM_LPC2XXX_VPBDIV} + description " + This option controls the clock that can be driven onto the + A23/XCLK pin" + } } cdl_component CYGNUM_HAL_RTC_CONSTANTS { diff --git a/packages/hal/arm/lpc2xxx/var/current/include/lpc2xxx_misc.h b/packages/hal/arm/lpc2xxx/var/current/include/lpc2xxx_misc.h --- a/packages/hal/arm/lpc2xxx/var/current/include/lpc2xxx_misc.h +++ b/packages/hal/arm/lpc2xxx/var/current/include/lpc2xxx_misc.h @@ -51,18 +51,20 @@ //============================================================================= //----------------------------------------------------------------------------- -// Functions to obtain the current processor clock settings -//----------------------------------------------------------------------------- -externC cyg_uint32 hal_lpc_get_cclk(void); -externC cyg_uint32 hal_lpc_get_pclk(void); -externC cyg_uint32 hal_lpc_get_xclk(void); - -//----------------------------------------------------------------------------- // Macros to derive the baudrate divider values for the internal UARTs //----------------------------------------------------------------------------- -#define CYG_HAL_ARM_LPC2XXX_PCLK() hal_lpc_get_pclk() #define CYG_HAL_ARM_LPC2XXX_BAUD_GENERATOR(baud) \ - (CYG_HAL_ARM_LPC2XXX_PCLK()/((baud)*16)) + (CYGNUM_HAL_ARM_LPC2XXX_PCLK/((baud)*16)) + +//----------------------------------------------------------------------------- +// LPX2xxx varaint specific initialisatio of CAN channels +// This function configures the pin functions for CAN use +//----------------------------------------------------------------------------- +#ifdef CYGPKG_DEVS_CAN_LPC2XXX +externC void hal_lpc_can_init(cyg_uint8 can_chan_no); +#define HAL_LPC2XXX_INIT_CAN(_can_chan_no_) hal_lpc_can_init(_can_chan_no_) +#define CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK CYGNUM_HAL_ARM_LPC2XXX_PCLK +#endif // CYGPKG_DEVS_CAN_LPC2XXX //----------------------------------------------------------------------------- // LPX2xxx watchdog support diff --git a/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c b/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c --- a/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c +++ b/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c @@ -70,28 +70,6 @@ #include // For diagnostic printing -// ------------------------------------------------------------------------- -// Processor clock configuration values and accessor functions -static cyg_uint32 lpc_cclk; // CPU clock frequency -static cyg_uint32 lpc_pclk; // peripheral devices clock speed - // (equal to, half, or quarter of CPU clock) -static cyg_uint32 lpc_xclk; // XCLK speed (equal to, half, or quarter of - // CPU clock) - -cyg_uint32 hal_lpc_get_cclk(void) -{ - return (lpc_cclk); -} - -cyg_uint32 hal_lpc_get_pclk(void) -{ - return (lpc_pclk); -} - -cyg_uint32 hal_lpc_get_xclk(void) -{ - return (lpc_xclk); -} // ------------------------------------------------------------------------- // eCos clock support @@ -102,7 +80,7 @@ void hal_clock_initialize(cyg_uint32 per { CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE; - period = period/(lpc_cclk/lpc_pclk); + period = period / (CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED / CYGNUM_HAL_ARM_LPC2XXX_PCLK); // Disable and reset counter HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 2); @@ -159,7 +137,8 @@ void hal_delay_us(cyg_int32 usecs) // Calculate how many timer ticks the required number of // microseconds equate to. We do this calculation in 64 bit // arithmetic to avoid overflow. - ticks = (((cyg_uint64)usecs) * ((cyg_uint64)lpc_pclk))/1000000LL; + ticks = CYGNUM_HAL_ARM_LPC2XXX_PCLK; + ticks = (((cyg_uint64)usecs) * (ticks))/1000000LL; // Disable and reset counter HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 2); @@ -217,22 +196,16 @@ void lpc_set_vpbdiv(int vpbdiv, int xclk HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_VPBDIV, ((xclkdiv & 0x3) << 4) | (vpbdiv & 0x3)); - lpc_xclk = lpc_cclk / xclkdiv; #else HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_VPBDIV, vpbdiv & 0x3); - lpc_xclk = 0; // Obvious bad value #endif - - lpc_pclk = lpc_cclk / vpbdiv; } // Perform variant setup. This optionally calls into the platform // HAL if it has defined HAL_PLF_HARDWARE_INIT. void hal_hardware_init(void) { - lpc_cclk = CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED; - #ifdef CYGHWR_HAL_ARM_LPC2XXX_FAMILY_LPC22XX lpc_set_vpbdiv(CYGNUM_HAL_ARM_LPC2XXX_VPBDIV, CYGNUM_HAL_ARM_LPC2XXX_XCLKDIV); @@ -506,5 +479,35 @@ void hal_lpc_watchdog_reset(void) continue; } +#ifdef CYGPKG_DEVS_CAN_LPC2XXX +//=========================================================================== +// Do varianat specific CAN initialisation +//=========================================================================== +void hal_lpc_can_init(cyg_uint8 can_chan_no) +{ + typedef struct + { + cyg_uint32 pin_mask; + cyg_uint16 reg; + } canpincfg; + + static const canpincfg canpincfg_tbl[] = + { + {0x00040000L, CYGARC_HAL_LPC2XXX_REG_PINSEL1}, + {0x00014000L, CYGARC_HAL_LPC2XXX_REG_PINSEL1}, + {0x00001800L, CYGARC_HAL_LPC2XXX_REG_PINSEL1}, + {0x0F000000L, CYGARC_HAL_LPC2XXX_REG_PINSEL0}, + }; + + CYG_ASSERT(can_chan_no < 4, "CAN channel number out of bounds"); + canpincfg *pincfg = (canpincfg *)&canpincfg_tbl[can_chan_no]; + cyg_uint32 regval; + + HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_PIN_BASE + pincfg->reg, regval); + regval |= pincfg->pin_mask; + HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_PIN_BASE + pincfg->reg, regval); +} +#endif // CYGPKG_DEVS_CAN_LPC2XXX + //-------------------------------------------------------------------------- // EOF lpc_misc.c