Mercurial > ecos-v3_0-branch
changeset 72:da3908c9cd10 ecos-sw-2000-02-17
Merge from eCos master repository on 2000-02-17-18:56:14-GMT
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -2,12 +2,6 @@ 2000-02-10 Jonathan Larmour <jlarmour@ * targets: Fix up some accidental reversions -2000-02-10 Nick Garnett <nickg@cygnus.co.uk> - - * targets: - * packages: - Added appropriate entries for i386 PC target. - 2000-02-07 Jesper Skov <jskov@redhat.com> * targets:
--- a/packages/hal/arm/arch/current/ChangeLog +++ b/packages/hal/arm/arch/current/ChangeLog @@ -1,3 +1,7 @@ +2000-02-16 Jesper Skov <jskov@redhat.com> + + * src/arm_stub.c: CYG_HAL_ARM -> CYGPKG_HAL_ARM + 2000-02-10 Jesper Skov <jskov@redhat.com> * src/vectors.S (reset_platform):
--- a/packages/hal/arm/arch/current/src/arm_stub.c +++ b/packages/hal/arm/arch/current/src/arm_stub.c @@ -51,7 +51,7 @@ #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS -#ifdef CYG_HAL_ARM_SIM +#ifdef CYGPKG_HAL_ARM_SIM #error "GDB Stub support not implemented for ARM SIM" #endif
--- a/packages/hal/arm/edb7xxx/current/ChangeLog +++ b/packages/hal/arm/edb7xxx/current/ChangeLog @@ -1,3 +1,8 @@ +2000-02-16 Jesper Skov <jskov@redhat.com> + + * include/hal_platform_setup.h: + CYG_HAL_ARM -> CYGPKG_HAL_ARM + 2000-02-10 Gary Thomas <gthomas@cygnus.co.uk> * tests/dram_test.c: Include proper testing infrastructure to
--- a/packages/hal/arm/edb7xxx/current/include/hal_platform_setup.h +++ b/packages/hal/arm/edb7xxx/current/include/hal_platform_setup.h @@ -113,7 +113,7 @@ // Define startup code [macros] #if defined(CYGSEM_HAL_INSTALL_MMU_TABLES) && !defined(CYG_HAL_STARTUP_RAM) -#ifdef CYG_HAL_ARM_CL7111 // CL7111, 710 processor +#ifdef CYGPKG_HAL_ARM_CL7111 // CL7111, 710 processor #define MMU_INITIALIZE \ ldr r2,=MMU_Control_Init ;\ mcr MMU_CP,0,r2,MMU_Control,c0 /* MMU off */ ;\
--- a/packages/hal/common/current/ChangeLog +++ b/packages/hal/common/current/ChangeLog @@ -1,3 +1,7 @@ +2000-02-16 Jesper Skov <jskov@redhat.com> + + * include/hal_stub.h: fixed endian definitions. + 2000-02-10 Jesper Skov <jskov@redhat.com> * include/pkgconf/hal.h: Added CYGSEM_HAL_ROM_MONITOR
--- a/packages/hal/common/current/include/hal_stub.h +++ b/packages/hal/common/current/include/hal_stub.h @@ -75,9 +75,13 @@ extern "C" { #define __set_mem_fault_trap(x) ({__mem_fault = 0; x(); __mem_fault;}) -#if (CYG_BYTEORDER==CYG_LSBFIRST) && \ - (!defined(__LITTLE_ENDIAN__) || !defined(_LITTLE_ENDIAN)) -# define __LITTLE_ENDIAN__ +#if (CYG_BYTEORDER==CYG_LSBFIRST) +# if !defined(__LITTLE_ENDIAN__) +# define __LITTLE_ENDIAN__ +# endif +# if !defined(_LITTLE_ENDIAN) +# define _LITTLE_ENDIAN +# endif #endif //----------------------------------------------------------------------------
--- a/packages/hal/i386/arch/current/ChangeLog +++ b/packages/hal/i386/arch/current/ChangeLog @@ -1,3 +1,27 @@ +2000-02-16 Jesper Skov <jskov@redhat.com> + + * src/i386_stub.c: CYG_HAL_I386 -> CYGPKG_HAL_I386 + +2000-02-10 Nick Garnett <nickg@cygnus.co.uk> + + * include/hal_arch.h: Merged PC platform support changes + contributed by Patrick O'Grady (pjo)(patrick@softprocess.com). + + * include/hal_intr.h: Moved Linux specific support out to its own + var_intr.h. + + * src/context.S: Added FP switch code from pjo, suitably + protected. + + * src/PKGconf.mak: Added i386_stub.c to COMPILE list. + + * src/i386_stub.c: + * include/arch.inc: Files added. + + * src/hal_misc.c: Added hal_zero_bss(). + + * src/vectors.S: Added PC support code. + 2000-01-21 Jesper Skov <jskov@cygnus.co.uk> * include/hal_intr.h (HAL_INTERRUPT_MASK, HAL_INTERRUPT_UNMASK):
new file mode 100644 --- /dev/null +++ b/packages/hal/i386/arch/current/include/arch.inc @@ -0,0 +1,207 @@ +#ifndef CYGONCE_HAL_ARCH_INC +#define CYGONCE_HAL_ARCH_INC +##============================================================================= +## +## arch.inc +## +## i386 assembler header file +## +##============================================================================= +######COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +######COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg, pjo +## Date: 1999-10-15 +## Purpose: Architecture definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the i386 CPU family. +## Usage: +## #include <cyg/hal/arch.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/i386.inc> + +#include <cyg/hal/variant.inc> + +##----------------------------------------------------------------------------- +## CPU specific macros. These provide a common assembler interface to +## operations that may have CPU specific implementations on different +## variants of the architecture. + +#ifndef CYGPKG_HAL_I386_CPU_INIT_DEFINED + # Initialize CPU + .macro hal_cpu_init + .endm +#endif /* !CYGPKG_HAL_I386_CPU_INIT_DEFINED */ + +##----------------------------------------------------------------------------- + +#ifndef CYGPKG_HAL_I386_INTC_DEFINED + +#ifndef CYGPKG_HAL_I386_INTC_INIT_DEFINED + # initialize all interrupts to disabled + .macro hal_intc_init + .endm +#endif + + .macro hal_intc_decode vnum + .endm + +#endif + + +#------------------------------------------------------------------------------ +# FPU macros. + +#ifndef CYGPKG_HAL_I386_FPU_DEFINED + +#ifdef CYGHWR_HAL_I386_FPU + + .macro hal_fpu_init + .endm + + .macro hal_fpu_save regs + .endm + + .macro hal_fpu_save_caller regs + .endm + + .macro hal_fpu_save_callee regs + .endm + + .macro hal_fpu_load_caller regs + .endm + + .macro hal_fpu_load_callee regs + .endm + + .macro hal_fpu_load regs + .endm + +#else /* !CYGHWR_HAL_I386_FPU */ + + .macro hal_fpu_init + .endm + + .macro hal_fpu_save regs + .endm + + .macro hal_fpu_save_caller regs + .endm + + .macro hal_fpu_save_callee regs + .endm + + .macro hal_fpu_load_caller regs + .endm + + .macro hal_fpu_load_callee regs + .endm + + .macro hal_fpu_load regs + .endm + +#endif + +#endif + +#------------------------------------------------------------------------------ +# MMU macros. + +#ifndef CYGPKG_HAL_I386_MMU_DEFINED + + .macro hal_mmu_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# MEMC macros. + +#ifndef CYGPKG_HAL_I386_MEMC_DEFINED + + .macro hal_memc_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Cache macros. + +#ifndef CYGPKG_HAL_I386_CACHE_DEFINED + + .macro hal_cache_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Diagnostics macros. + +#ifndef CYGPKG_HAL_I386_DIAG_DEFINED + + .macro hal_diag_init + .endm + + .macro hal_diag_excpt_start + .endm + + .macro hal_diag_intr_start + .endm + + .macro hal_diag_restore + .endm +#endif + +#------------------------------------------------------------------------------ +# Timer initialization. + +#ifndef CYGPKG_HAL_I386_TIMER_DEFINED + + .macro hal_timer_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_I386_MON_DEFINED + + .macro hal_mon_init + .endm + +#endif + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_ARCH_INC +# end of arch.inc
--- a/packages/hal/i386/arch/current/include/hal_arch.h +++ b/packages/hal/i386/arch/current/include/hal_arch.h @@ -35,7 +35,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): proven -// Contributors:proven +// Contributors:proven, pjo, nickg // Date: 1998-10-05 // Purpose: Define architecture abstractions // Usage: #include <cyg/hal/hal_arch.h> @@ -47,6 +47,8 @@ #include <pkgconf/hal.h> #include <cyg/infra/cyg_type.h> +#include <cyg/hal/i386_stub.h> + //----------------------------------------------------------------------------- // Processor saved states. This structure is also defined in i386.inc for // assembly code. Do not change this without changing that (or vice versa). @@ -98,8 +100,12 @@ externC cyg_uint32 hal_msbit_index(cyg_u /* Cyg_HardwareThread::thread_entry expects one argument at stack */ \ /* offset 4 (_thread_). The (0xDEADBEEF) entry is the return addr */ \ /* for thread_entry (which is never used). */ \ + *(--_sp_) = (CYG_WORD)(0); \ + *(--_sp_) = (CYG_WORD)(0); \ + *(--_sp_) = (CYG_WORD)(0); \ + *(--_sp_) = (CYG_WORD)(0); \ *(--_sp_) = (CYG_WORD)(_thread_); \ - *(--_sp_) = (CYG_WORD)(0xDEADBEEF); \ + *(--_sp_) = (CYG_WORD)(0); \ *(--_sp_) = (CYG_WORD)(_entry_); \ \ _regs_ = (HAL_SavedRegisters *) \ @@ -143,11 +149,16 @@ externC void hal_thread_load_context( CY // HAL_BREAKINST is the value of the breakpoint instruction and // HAL_BREAKINST_SIZE is its size in bytes. -// #define HAL_BREAKPOINT(_label_) +#define HAL_BREAKPOINT(_label_) \ +CYG_MACRO_START \ + asm volatile (" .globl " #_label_ ";" \ + #_label_":" \ + "int $3" \ + ); \ +CYG_MACRO_END -// #define HAL_BREAKINST - -// #define HAL_BREAKINST_SIZE +#define HAL_BREAKINST 0xCC +#define HAL_BREAKINST_SIZE 1 //----------------------------------------------------------------------------- // Thread register state manipulation for GDB support. @@ -159,10 +170,16 @@ externC void hal_thread_load_context( CY // Copy a set of registers from a HAL_SavedRegisters structure into a // GDB ordered array. -#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) + +externC void hal_get_gdb_registers(target_register_t *, HAL_SavedRegisters *); +externC void hal_set_gdb_registers(HAL_SavedRegisters *, target_register_t *); + +#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ + hal_get_gdb_registers((target_register_t *)(_aregval_), (_regs_)) // Copy a GDB ordered array into a HAL_SavedRegisters structure. -#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) +#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ + hal_set_gdb_registers((_regs_), (target_register_t *)(_aregval_)) //----------------------------------------------------------------------------- // HAL setjmp @@ -212,7 +229,7 @@ externC void hal_idle_thread_action(cyg_ // Interrupt + call to ISR, interrupt_end() and the DSR #define CYGNUM_HAL_STACK_INTERRUPT_SIZE \ - ((6*4 /* sizeof(HAL_SavedRegisters) */) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE) + ((6*4*2 /* 2*sizeof(HAL_SavedRegisters) */) + 4 * CYGNUM_HAL_STACK_FRAME_SIZE) // We have lots of registers so no particular amount is added in for // typical local variable usage. @@ -222,7 +239,7 @@ externC void hal_idle_thread_action(cyg_ // than this. Allow enough for three interrupt sources - clock, serial and // one other -#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK +#if 0 // defined(CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK) // An interrupt stack which is large enough for all possible interrupt // conditions (and only used for that purpose) exists. "User" stacks @@ -235,14 +252,17 @@ externC void hal_idle_thread_action(cyg_ // No separate interrupt stack exists. Make sure all threads contain // a stack sufficiently large + # define CYGNUM_HAL_STACK_SIZE_MINIMUM \ - (((2+3)*CYGNUM_HAL_STACK_INTERRUPT_SIZE) + \ + (((2+3+10)*CYGNUM_HAL_STACK_INTERRUPT_SIZE) + \ (2*CYGNUM_HAL_STACK_FRAME_SIZE)) + #endif // Now make a reasonable choice for a typical thread size. Pluck figures // from thin air and say 15 call frames with an average of 16 words of // automatic variables per call frame + #define CYGNUM_HAL_STACK_SIZE_TYPICAL \ (CYGNUM_HAL_STACK_SIZE_MINIMUM + \ 15 * (CYGNUM_HAL_STACK_FRAME_SIZE+(16*4)))
--- a/packages/hal/i386/arch/current/include/hal_intr.h +++ b/packages/hal/i386/arch/current/include/hal_intr.h @@ -35,7 +35,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): proven -// Contributors: proven, jskov +// Contributors: proven, jskov, pjo, nickg // Date: 1999-02-20 // Purpose: Define Interrupt support // Description: The macros defined here provide the HAL APIs for handling @@ -54,84 +54,29 @@ #include <cyg/infra/cyg_type.h> -#ifdef CYGPKG_HAL_I386_LINUX -#include <pkgconf/hal_i386_linux.h> // CYGSEM_HAL_I386_LINUX_REAL_TIME -#endif +#include <cyg/hal/var_intr.h> //-------------------------------------------------------------------------- // Interrupt vectors. +#ifndef CYGNUM_HAL_ISR_MAX #define CYGNUM_HAL_VECTOR_NMI 0 +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VECTOR_NMI +#define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 ) +#endif /* CYGNUM_HAL_ISR_MAX, pjo 15 oct 1999 */ -#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VECTOR_NMI - +#ifndef CYGNUM_HAL_VSR_COUNT #define CYGNUM_HAL_VSR_MIN 0 #define CYGNUM_HAL_VSR_MAX 0 #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 ) +#endif /* CYGNUM_HAL_VSR_COUNT, pjo 15 oct 1999 */ +#ifndef CYGNUM_HAL_EXCEPTION_COUNT #define CYGNUM_HAL_EXCEPTION_MIN 0 #define CYGNUM_HAL_EXCEPTION_MAX 0 #define CYGNUM_HAL_EXCEPTION_COUNT ( CYGNUM_HAL_EXCEPTION_MAX + 1 ) - -#define CYGNUM_HAL_ISR_MIN 0 -#define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 ) - - -#ifdef CYGPKG_HAL_I386_LINUX -// Additional vectors on Linux. These match the Linux signals. -#define CYGNUM_HAL_VECTOR_SIGHUP 1 -#define CYGNUM_HAL_VECTOR_SIGINT 2 -#define CYGNUM_HAL_VECTOR_SIGQUIT 3 -#define CYGNUM_HAL_VECTOR_SIGILL 4 -#define CYGNUM_HAL_VECTOR_SIGTRAP 5 -#define CYGNUM_HAL_VECTOR_SIGIOT 6 -#define CYGNUM_HAL_VECTOR_SIGBUS 7 -#define CYGNUM_HAL_VECTOR_SIGFPE 8 -#define CYGNUM_HAL_VECTOR_SIGKILL 9 -#define CYGNUM_HAL_VECTOR_SIGUSR1 10 -#define CYGNUM_HAL_VECTOR_SIGSEGV 11 -#define CYGNUM_HAL_VECTOR_SIGUSR2 12 -#define CYGNUM_HAL_VECTOR_SIGPIPE 13 -#define CYGNUM_HAL_VECTOR_SIGALRM 14 -#define CYGNUM_HAL_VECTOR_SIGTERM 15 -#define CYGNUM_HAL_VECTOR_SIGCHLD 17 -#define CYGNUM_HAL_VECTOR_SIGCONT 18 -#define CYGNUM_HAL_VECTOR_SIGSTOP 19 -#define CYGNUM_HAL_VECTOR_SIGTSTP 20 -#define CYGNUM_HAL_VECTOR_SIGTTIN 21 -#define CYGNUM_HAL_VECTOR_SIGTTOU 22 -#define CYGNUM_HAL_VECTOR_SIGURG 23 -#define CYGNUM_HAL_VECTOR_SIGXCPU 24 -#define CYGNUM_HAL_VECTOR_SIGXFSZ 25 -#define CYGNUM_HAL_VECTOR_SIGVTALRM 26 -#define CYGNUM_HAL_VECTOR_SIGPROF 27 -#define CYGNUM_HAL_VECTOR_SIGWINCH 28 -#define CYGNUM_HAL_VECTOR_SIGIO 29 -#define CYGNUM_HAL_VECTOR_SIGPWR 30 - -#undef CYGNUM_HAL_ISR_MAX -#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VECTOR_SIGPWR - -// Generic exception vector names -#define CYGNUM_HAL_EXCEPTION_INTERRUPT CYGNUM_HAL_VECTOR_SIGINT -#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION CYGNUM_HAL_VECTOR_SIGILL -#define CYGNUM_HAL_EXCEPTION_TRAP CYGNUM_HAL_VECTOR_SIGTRAP -#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_SIGBUS -#define CYGNUM_HAL_EXCEPTION_FPU CYGNUM_HAL_VECTOR_SIGFPE -#define CYGNUM_HAL_EXCEPTION_STACK_OVERFLOW CYGNUM_HAL_VECTOR_SIGSEGV - -#undef CYGNUM_HAL_EXCEPTION_MAX -#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_STACK_OVERFLOW - -// The vector used by the Real time clock -#ifdef CYGSEM_HAL_I386_LINUX_REAL_TIME -#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_VECTOR_SIGALRM -#else -#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_VECTOR_SIGVTALRM -#endif - -#endif // ifdef CYGPKG_HAL_I386_LINUX - +#endif /* CYGNUM_HAL_EXCEPTION_COUNT, pjo 15 oct 1999 */ //-------------------------------------------------------------------------- // Static data used by HAL @@ -144,90 +89,14 @@ externC volatile CYG_ADDRESS cyg_hal_in // VSR table externC volatile CYG_ADDRESS cyg_hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; - -#ifdef CYGPKG_HAL_I386_LINUX -// Interrupt controler emulation variables. -externC volatile int cyg_hal_interrupts_disabled; -externC volatile int cyg_hal_interrupts_deferred; -externC volatile int cyg_hal_interrupts_unhandled[CYGNUM_HAL_ISR_COUNT]; -#endif - //-------------------------------------------------------------------------- // Interrupt state storage typedef cyg_uint32 CYG_INTERRUPT_STATE; -//-------------------------------------------------------------------------- -// Interrupt control macros - -#ifdef CYGPKG_HAL_I386_LINUX - -externC void cyg_hal_default_interrupt_vsr(int vector); -externC void cyg_hal_default_exception_vsr(int vector); -externC int cyg_hal_sys_sigprocmask(int, const long*, long*); - -// FIXME: These should use block/unblock of the signals instead of -// cyg_hal_interrupts_disabled. - -#define HAL_ENABLE_INTERRUPTS() \ - CYG_MACRO_START \ - cyg_ucount8 _i_; \ - cyg_hal_interrupts_disabled = 0; \ - if (cyg_hal_interrupts_deferred) { \ - cyg_hal_interrupts_deferred = 0; \ - for (_i_ = CYGNUM_HAL_ISR_MIN; _i_ <= CYGNUM_HAL_ISR_MAX; _i_++) { \ - if (cyg_hal_interrupts_unhandled[_i_]) { \ - cyg_hal_default_interrupt_vsr(_i_); \ - } \ - } \ - } \ - CYG_MACRO_END - -#define HAL_DISABLE_INTERRUPTS(_old_) \ - CYG_MACRO_START \ - (_old_) = cyg_hal_interrupts_disabled++; \ - CYG_MACRO_END - -#define HAL_RESTORE_INTERRUPTS(_old_) \ - CYG_MACRO_START \ - cyg_ucount8 _i_; \ - cyg_hal_interrupts_disabled = (_old_); \ - if (0 == cyg_hal_interrupts_disabled) { \ - if (cyg_hal_interrupts_deferred) { \ - cyg_hal_interrupts_deferred = 0; \ - for (_i_ = CYGNUM_HAL_ISR_MIN; _i_ <= CYGNUM_HAL_ISR_MAX; \ - _i_++){ \ - if (cyg_hal_interrupts_unhandled[_i_]) { \ - cyg_hal_default_interrupt_vsr(_i_); \ - } \ - } \ - } \ - } \ - CYG_MACRO_END - -#define HAL_QUERY_INTERRUPTS(_old_) \ - CYG_MACRO_START \ - (_old_) = !cyg_hal_interrupts_disabled; \ - CYG_MACRO_END - -#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ - CYG_MACRO_START \ - cyg_hal_interrupts_unhandled[_vector_] = 0; \ - CYG_MACRO_END - -#endif // ifdef CYGPKG_HAL_I386_LINUX - - -//--------------------------------------------------------------------------- -// Translate a vector number into an ISR table index. - -#ifdef CYGPKG_HAL_I386_LINUX -// The native linux port doesn't support chained interrupts --proven 19981005 -#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_) -#endif - //--------------------------------------------------------------------------- // Interrupt and VSR attachment macros + externC cyg_uint32 cyg_hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ @@ -242,6 +111,9 @@ externC cyg_uint32 cyg_hal_default_isr(C (_state_) = 1; \ CYG_MACRO_END +// pjo, 18 oct 1999: Temporary. Soon the i386/pc hal will be able to +// use this definition of interrupt attach. +#ifndef HAL_INTERRUPT_ATTACH #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ CYG_MACRO_START \ cyg_uint32 _index_; \ @@ -255,6 +127,7 @@ externC cyg_uint32 cyg_hal_default_isr(C cyg_hal_interrupt_objects[_index_] = (CYG_ADDRESS)(_object_); \ } \ CYG_MACRO_END +#endif /* HAL_INTERRUPT_ATTACH */ #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ CYG_MACRO_START \ @@ -283,89 +156,5 @@ externC cyg_uint32 cyg_hal_default_isr(C CYG_MACRO_END //--------------------------------------------------------------------------- -// Interrupt controller access - -#ifdef CYGPKG_HAL_I386_LINUX - -#define LINUX_SIG_BLOCK 0 -#define LINUX_SIG_UNBLOCK 1 -#define HAL_INTERRUPT_MASK( _vector_ ) \ - CYG_MACRO_START \ - long _old_, _new_; \ - _new_ = 1 << (_vector_); \ - cyg_hal_sys_sigprocmask(LINUX_SIG_BLOCK, &_new_, &_old_); \ - CYG_MACRO_END - -#define HAL_INTERRUPT_UNMASK( _vector_ ) \ - CYG_MACRO_START \ - long _old_, _new_; \ - _new_ = 1 << (_vector_); \ - cyg_hal_sys_sigprocmask(LINUX_SIG_UNBLOCK, &_new_, &_old_); \ - CYG_MACRO_END - -// The native linux port doesn't have configurable interrupts. -#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) - -// The native linux port doesn't have interrupt levels. -#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) - -#endif // ifdef CYGPKG_HAL_I386_LINUX - - -//--------------------------------------------------------------------------- -// Clock control - -#ifdef CYGPKG_HAL_I386_LINUX - -struct hal_timeval { - long tv_sec; - long tv_usec; -}; -struct hal_itimerval { - struct hal_timeval it_interval; - struct hal_timeval it_value; -}; - -externC int cyg_hal_sys_setitimer(int, const struct hal_itimerval*, - struct hal_itimerval*); -externC int cyg_hal_sys_getitimer(int, struct hal_itimerval*); - -#ifdef CYGSEM_HAL_I386_LINUX_REAL_TIME -#define CYGNUM_HAL_TIMER_TYPE 0 // ITIMER_REAL -#else -#define CYGNUM_HAL_TIMER_TYPE 1 // ITIMER_VIRTUAL -#endif - -#define HAL_CLOCK_INITIALIZE( _period_ ) \ - CYG_MACRO_START \ - struct hal_itimerval new_itimerval, old; \ - \ - new_itimerval.it_interval.tv_sec = 0; \ - new_itimerval.it_interval.tv_usec = (_period_); \ - new_itimerval.it_value.tv_sec = 0; \ - new_itimerval.it_value.tv_usec = (_period_); \ - /* Use setitimer to set the realtime clock */ \ - cyg_hal_sys_setitimer(CYGNUM_HAL_TIMER_TYPE, &new_itimerval, &old); \ - CYG_MACRO_END - -// The sigalarm runs in one-shot mode. We have to re-enable it -#define HAL_CLOCK_RESET( _vector_, _period_ ) \ - HAL_INTERRUPT_UNMASK( _vector_ ) - -// This timer counts down, so subtract from set value. -#define HAL_CLOCK_READ( _pvalue_ ) \ - CYG_MACRO_START \ - struct hal_itimerval old_itimerval; \ - cyg_hal_sys_getitimer(CYGNUM_HAL_TIMER_TYPE, &old_itimerval); \ - *(_pvalue_) = old_itimerval.it_interval.tv_usec - \ - old_itimerval.it_value.tv_usec; \ - CYG_MACRO_END - -#define HAL_CLOCK_LATENCY( _pvalue_ ) \ - HAL_CLOCK_READ((_pvalue_)) - -#endif // ifdef CYGPKG_HAL_I386_LINUX - -//--------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_HAL_INTR_H // End of hal_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/i386/arch/current/include/i386_stub.h @@ -0,0 +1,91 @@ +#ifndef CYGONCE_HAL_I386_STUB_H +#define CYGONCE_HAL_I386_STUB_H +//========================================================================== +// +// i386_stub.h +// +// i386/PC GDB stub support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pjo +// Contributors: pjo, nickg +// Date: 1999-10-15 +// Purpose: i386/PC GDB stub support +// Description: Definitions for the GDB stubs. Most of this comes from +// the original libstub code. +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +//####DESCRIPTIONEND#### +// +//========================================================================== + + +#define NUMREGS (16) +#define REGSIZE(x) (((x) < CS)? 4 : 2) + + +enum regnames +{ EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, + PC /* also known as eip */, + PS /* also known as eflags */, + CS, SS, DS, ES, FS, GS +}; + +typedef enum regnames regnames_t ; +typedef unsigned long target_register_t ; + +#define PS_C 0x00000001 +#define PS_Z 0x00000040 +#define PS_V 0x00000080 +#define PS_T 0x00000100 + +#define SP (ESP) +#define EIP (PC) + + +/* Find out what our last trap was. */ +extern int __get_trap_number(void) ; + +/* Given a trap number, compute the signal code for it. */ +extern int __computeSignal(unsigned int trap_number) ; + +/* Enable single stepping after the next user resume instruction. */ +extern void __single_step(void) ; +extern void __clear_single_step(void) ; + +extern void __install_breakpoints(void) ; +extern void __clear_breakpoints(void) ; + + +//--------------------------------------------------------------------------- +#endif /* CYGONCE_HAL_I386_STUB_H */ +// End of i386_stub.h
--- a/packages/hal/i386/arch/current/src/PKGconf.mak +++ b/packages/hal/i386/arch/current/src/PKGconf.mak @@ -34,7 +34,7 @@ PACKAGE := hal_i386 include ../../../../../pkgconf/pkgconf.mak LIBRARY := libtarget.a -COMPILE := hal_misc.c context.S +COMPILE := hal_misc.c context.S i386_stub.c OTHER_OBJS := OTHER_TARGETS := vectors.stamp ldscript.stamp OTHER_DEPS := $(PACKAGE)_vectors.d ldscript.d
--- a/packages/hal/i386/arch/current/src/context.S +++ b/packages/hal/i386/arch/current/src/context.S @@ -32,7 +32,7 @@ #######DESCRIPTIONBEGIN#### ## ## Author(s): jskov -## Contributors:jskov +## Contributors:jskov, pjo, nickg ## Date: 1999-01-20 ## Purpose: i386 context switch code ## Description: This file contains implementations of the thread context @@ -72,7 +72,7 @@ FUNC_START(hal_thread_switch_context) # Make room on the stack for the context movl %esp,%ecx # keep original SP - sub $i386reg_context_size,%esp + sub $i386reg_context_size,%esp # Save next context ptr in this context. Necessary because # hal_thread_load_context expects to find the ptr on the stack, @@ -102,6 +102,13 @@ FUNC_START(hal_thread_switch_context) # %eax, %ecx, and %edx are ours to abuse. FUNC_START(hal_thread_load_context) + +#ifdef CYGHWR_HAL_I386_FPU + movl %cr0, %eax + orl $0x8, %eax + movl %eax, %cr0 +#endif + movl i386reg_next_context(%esp),%eax # get new context ptr movl (%eax),%eax
--- a/packages/hal/i386/arch/current/src/hal_misc.c +++ b/packages/hal/i386/arch/current/src/hal_misc.c @@ -32,7 +32,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): nickg -// Contributors: proven +// Contributors: proven, pjo // Date: 1999-02-20 // Purpose: HAL miscellaneous functions // Description: This file contains miscellaneous functions provided by the @@ -48,6 +48,25 @@ #include <cyg/hal/hal_arch.h> +void hal_zero_bss(void) +{ extern char _end ; + extern char __bss_start ; + + asm( + "movl %0, %%ecx;" /* Get the address of _end */ + "movl %1, %%edi;" /* Address of __bss_start */ + "subl %%edi, %%ecx;" /* Number of bytes in %ecx */ + "addl $3, %%ecx;" /* Round up to the next 32-bits */ + "shr $2, %%ecx;" /* Divide by 4: we'll fill 32-bit words. */ + "xorl %%eax, %%eax;" /* Store zeros. */ + "rep + stosl" /* Fill the region. */ + : /* No outputs. */ + : "g" (&_end), "g" (&__bss_start) + : "ecx", "edi", "eax" + ); +} + //--------------------------------------------------------------------------- #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
new file mode 100644 --- /dev/null +++ b/packages/hal/i386/arch/current/src/i386_stub.c @@ -0,0 +1,208 @@ +/* i386_stub.c - helper functions for stub, generic to all i386 processors + * + * Copyright (c) 1998,1999 Cygnus Solutions + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* +- pjo, 29 sep 1999 +- Copied from the ARM configuration and merged with an older GDB i386-stub.c. +*/ + +#include <stddef.h> + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#ifdef CYGPKG_HAL_I386_SIM +#error "GDB Stub support not implemented for i386 SIM" +#endif + +#include <cyg/hal/hal_stub.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> + +#ifndef FALSE +#define FALSE 0 +#define TRUE 1 +#endif + +#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT +#include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id +#endif + +/* Given a trap value TRAP, return the corresponding signal. */ + +int __computeSignal (unsigned int trap_number) +{ + switch (trap_number) + { + case CYGNUM_HAL_VECTOR_DIV0: + /* This isn't quite accurrate: this is integer division only. */ + return SIGFPE ; + + case CYGNUM_HAL_VECTOR_DEBUG: + return SIGTRAP ; + + case CYGNUM_HAL_VECTOR_NMI: + return SIGINT ; + + case CYGNUM_HAL_VECTOR_BREAKPOINT: + return SIGTRAP ; + + case CYGNUM_HAL_VECTOR_OVERFLOW: + case CYGNUM_HAL_VECTOR_BOUND: + return SIGSEGV ; + + case CYGNUM_HAL_VECTOR_OPCODE: + return SIGILL ; + + case CYGNUM_HAL_VECTOR_NO_DEVICE: + case CYGNUM_HAL_VECTOR_FPE: + return SIGFPE ; + + case CYGNUM_HAL_VECTOR_DOUBLE_FAULT: + return SIGTRAP ; + + case CYGNUM_HAL_VECTOR_INVALID_TSS: + case CYGNUM_HAL_VECTOR_SEGV: + case CYGNUM_HAL_VECTOR_STACK_FAULT: + case CYGNUM_HAL_VECTOR_PROTECTION: + case CYGNUM_HAL_VECTOR_PAGE: + case CYGNUM_HAL_VECTOR_ALIGNMENT: + return SIGSEGV ; + + default: + return SIGTRAP; + } +} + + +/* Return the trap number corresponding to the last-taken trap. */ + +int __get_trap_number (void) +{ + extern int hal_pc_trap_number ; + // The vector is not not part of the GDB register set so get it + // directly from the save context. + return hal_pc_trap_number ; +} + +/* Set the currently-saved pc register value to PC. */ + +void set_pc (target_register_t pc) +{ + put_register (PC, pc); +} + + +/*---------------------------------------------------------------------- + * Single-step support + */ + +/* Set things up so that the next user resume will execute one instruction. + This may be done by setting breakpoints or setting a single step flag + in the saved user registers, for example. */ + + +/* We just turn on the trap bit in the flags register for the particular + thread. When it resumes, we'll get another debugger trap. +*/ +void __single_step (void) +{ put_register(PS, get_register(PS) | PS_T) ; +} + +/* Clear the single-step state. */ + +void __clear_single_step (void) +{ put_register(PS, get_register(PS) & ~PS_T) ; +} + +void __install_breakpoints (void) +{ +// FIXME(); +} + +void __clear_breakpoints (void) +{ +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + extern cyg_uint32 hal_pc_break_pc ; + if (hal_pc_break_pc) + { + cyg_hal_gdb_remove_break(hal_pc_break_pc) ; +#if 0 + hal_pc_break_pc = 0 ; +// asm("movl %0, %%dr0" : /* No outputs */ : "m" (hal_pc_break_pc)) ; + asm(" + movl %%dr7, %%eax + andl $0xFFFFFFFC, %%eax + movl %%eax, %%dr7" + : /* No outputs. */ + : /* No inputs. */ + : "eax"); +#endif + } +#endif + +} + +/* If the breakpoint we hit is in the breakpoint() instruction, return a + non-zero value. */ + +int isBreakpointFunction ; + +int +__is_breakpoint_function () +{ + isBreakpointFunction = (get_register (PC) == (target_register_t)&CYG_LABEL_NAME(breakinst)); + return isBreakpointFunction ; +} + + +/* Skip the current instruction. Since this is only called by the + stub when the PC points to a breakpoint or trap instruction, + we can safely just skip 4. */ + +void __skipinst (void) +{ +// FIXME() ; +} + + +#if 0 +void hal_get_gdb_registers(target_register_t * d, HAL_SavedRegisters * s) +{ + d[ESP] = s->esp ; + d[ESP] = s->esp ; + d[EBP] = s->ebp ; + d[EBX] = s->ebx ; + d[ESI] = s->esi ; + d[EDI] = s->edi ; + d[PC] = s->eip ; +} + + +void hal_set_gdb_registers(HAL_SavedRegisters * d, target_register_t * s) +{ + d->esp = s[ESP] ; + d->next_context = 0 ; + d->ebp = s[EBP] ; + d->ebx = s[EBX] ; + d->esi = s[ESI] ; + d->edi = s[EDI] ; + d->eip = s[PC] ; +} +#endif + + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
--- a/packages/hal/i386/arch/current/src/vectors.S +++ b/packages/hal/i386/arch/current/src/vectors.S @@ -44,33 +44,279 @@ ## ##============================================================================= + +#include <pkgconf/system.h> #include <pkgconf/hal.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif /* CYGPKG_KERNEL */ + +#include <cyg/hal/arch.inc> + #============================================================================== .file "vectors.S" +#============================================================================== # The Linux synthetic target defines its own startup. + #ifdef CYGPKG_HAL_I386_LINUX - .extern _linux_entry - .text - .globl _start + + .extern _linux_entry + .text + .globl _start _start: - jmp _linux_entry + jmp _linux_entry #else ## ifdef CYGPKG_HAL_I386_LINUX #============================================================================== # Real startup code. We jump here from the various reset vectors to set up the # world. - .text - .globl _start + .text + .globl _start _start: -#error "Not defined." + hal_cpu_init + hal_diag_init + hal_mmu_init + hal_fpu_init + hal_memc_init + hal_intc_init + hal_cache_init + hal_timer_init + +# loading the stack pointer seems appropriate now. + movl $_start, %esp + +# Save the sizes of memory on the stack. These were initialized by hal_cpu_init. + movl pc_standard_memory_size, %eax + movl pc_extended_memory_size, %ebx + pushl %ebx + pushl %eax + pushl %esp # pointer to that, um, 'struct' that we just saved. + + hal_mon_init + + .extern hal_zero_bss + call hal_zero_bss + + .extern hal_variant_init + call hal_variant_init + + .extern hal_platform_init + call hal_platform_init + + .extern cyg_hal_invoke_constructors + call cyg_hal_invoke_constructors + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + .extern initialize_stub + call initialize_stub +#endif /* CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS */ + +# Unused IRQ vector 15 points to our 'struct'... + popl %eax + movl %eax, (15 * 8) + + .extern cyg_start + call cyg_start + +# Hmm. Not expecting to return from cyg_start. +1: hlt + jmp 1b + +#============================================================================== +# Add a bit of debugger support. +#if 0 + .align 4 + .globl _breakinst +_breakinst: + int $3 + ret +#endif + +#============================================================================== +# +# hal_pc_generic_interrupt +# +#- Pushes the interrupt vector onto the stack, then +# jumps to hal_pc_irq. +# + + .extern __interrupt_stack + + .align 4, 0xCC + .globl hal_pc_generic_interrupt + .globl hal_pc_generic_interrupt_start + .globl hal_pc_generic_interrupt_vector + .globl hal_pc_generic_interrupt_end +hal_pc_generic_interrupt_start: +hal_pc_generic_interrupt: + pushl $0xbad4c0de +hal_pc_generic_interrupt_vector = . - 4 + jmp *hal_pc_irq_p +hal_pc_generic_interrupt_end: + + .align 4, 0xCC +hal_pc_irq_p: + .long hal_pc_irq + +# +# hal_pc_irq +# +#- Actually saves the CPU state, executes ISRs, etc. +#- The stack has eflags, cs, eip, and vector; all 32 bits. +# + .align 4, 0xCC + .globl hal_pc_irq +hal_pc_irq: + pusha + +# Maybe instrument for an interrupt. Parameter==vector number. + hal_pc_irq_instrument 0x20(%esp) + +# Maybe instrument for idle detection. + hal_pc_unidle_instrument + +# Show how far nested we are. + .extern hal_pc_in_interrupt + incl hal_pc_in_interrupt + + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + .extern cyg_scheduler_sched_lock + incl cyg_scheduler_sched_lock +#endif /* CYGFUN_HAL_COMMON_KERNEL_SUPPORT */ + -#endif ## ifndef CYGPKG_HAL_I386_LINUX +# Call cyg_hal_interrupt_handlers[vector](vector, cyg_hal_interrupt_data[vector]) + movl 0x20(%esp), %ecx + movl $cyg_hal_interrupt_handlers, %ebx + movl (%ebx, %ecx, 4), %edx + movl $cyg_hal_interrupt_data, %ebx + movl (%ebx, %ecx, 4), %eax + pushl %esp # Save the pointer to registers. Secret parameter! + pushl %eax + pushl %ecx + call *%edx # eax has the return value, needed for interrupt_end() + popl %ebx + popl %ebx + popl %ebx + +# Fix our nesting figure. + decl hal_pc_in_interrupt + +# Following code messes up eax, but not esi. + movl %eax, %esi + +# Send an EOI, maybe. + hal_intc_ack 0x20(%esp) + +# Reenable interrupts, if necessary. + movl 0x2C(%esp), %eax +# Turn off the single step flag. GDB uses that to single step through +# the code; we'll use the tasks' version of this flag in the popf later. + andl $~(0x100), %eax + pushl %eax + popfl + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT +# Call interrupt_end(r, cyg_hal_interrupt_objects[vector], regs) +# - r is the return value from cyg_hal_interrupt_handlers; +# - regs just points to the stack; we have already saved our context there; + movl $cyg_hal_interrupt_objects, %ebx + movl 0x20(%esp), %ecx + movl (%ebx, %ecx, 4), %edx + # regs is left from the push of ebp above; + pushl %edx + pushl %eax + call interrupt_end + addl $8, %esp +#endif /* CYGFUN_HAL_COMMON_KERNEL_SUPPORT */ + +# Maybe uninstrument the irq handler. + hal_pc_irq_uninstrument 0x20(%esp) + + popa # restore all our registers. + addl $4, %esp # dump the vector number + iret # and return to the program. + +#============================================================================== +# hal_idle_thread_action(cyg_uint32 loop_count) + + .align 4 + .globl hal_idle_thread_action +hal_idle_thread_action: + hal_pc_idle_instrument + hlt + ret + +#============================================================================== +# Port IO functions + +# pc_outb(port, value) + .align 4 + .globl pc_outb +pc_outb: + movl 4(%esp), %edx + movl 8(%esp), %eax + outb %al, %dx + ret + + +# x = pc_inb(port) + .align 4 + .globl pc_inb +pc_inb: + movl 4(%esp), %edx + inb %dx, %al + cbtw + cwtl + ret + +# pc_outw(port, value) + .align 4 + .globl pc_outw +pc_outw: + movl 4(%esp), %edx + movl 8(%esp), %eax + outw %ax, %dx + ret + +# x = pc_inw(port) + .align 4 + .globl pc_inw +pc_inw: + movl 4(%esp), %edx + inw %dx, %ax + cwtl + ret + +# x = CPU_swap_u16(x) + .align 4 + .global CPU_swap_u16 +CPU_swap_u16: + xorl %eax, %eax + movb 4(%esp), %ah + movb 5(%esp), %al + ret + +# x = CPU_swap_u32(x) + .align 4 + .global CPU_swap_u32 +CPU_swap_u32: + xorl %eax, %eax + movb 4(%esp), %ah + movb 5(%esp), %al + sall $16, %eax + movb 6(%esp), %ah + movb 7(%esp), %al + ret + +#endif // ifndef CYGPKG_HAL_I386_LINUX #------------------------------------------------------------------------------ # end of vectors.S
--- a/packages/hal/i386/linux/current/ChangeLog +++ b/packages/hal/i386/linux/current/ChangeLog @@ -1,3 +1,21 @@ +2000-02-16 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c (hal_diag_write_char): Check that write call is + successful. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/variant.inc: Added missed copyright notice. + +2000-02-15 Nick Garnett <nickg@cygnus.co.uk> + + * include/variant.inc: + * include/var_intr.h: + * include/plf_intr.h: + These files added to make this HAL consistent with PC + version. They also contains some code moved out of the + architecture HAL. + 2000-01-21 Jesper Skov <jskov@cygnus.co.uk> CR 902062-CR * src/hal_diag.c:
new file mode 100644 --- /dev/null +++ b/packages/hal/i386/linux/current/include/plf_intr.h @@ -0,0 +1,271 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// i386/Linux Interrupt and clock support +// +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): proven +// Contributors: proven, jskov, pjo +// Date: 1999-10-15 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock. +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_i386.h> +#include <cyg/infra/cyg_type.h> +//#include <cyg/hal/plf_intr.h> + +#include <pkgconf/hal_i386_linux.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#include <cyg/kernel/ktypes.h> +#include <cyg/kernel/kapi.h> +#endif /* CYGPKG_KERNEL */ + + +//-------------------------------------------------------------------------- +// Interrupt vectors. + +// Additional vectors on Linux. These match the Linux signals. +#define CYGNUM_HAL_VECTOR_SIGHUP 1 +#define CYGNUM_HAL_VECTOR_SIGINT 2 +#define CYGNUM_HAL_VECTOR_SIGQUIT 3 +#define CYGNUM_HAL_VECTOR_SIGILL 4 +#define CYGNUM_HAL_VECTOR_SIGTRAP 5 +#define CYGNUM_HAL_VECTOR_SIGIOT 6 +#define CYGNUM_HAL_VECTOR_SIGBUS 7 +#define CYGNUM_HAL_VECTOR_SIGFPE 8 +#define CYGNUM_HAL_VECTOR_SIGKILL 9 +#define CYGNUM_HAL_VECTOR_SIGUSR1 10 +#define CYGNUM_HAL_VECTOR_SIGSEGV 11 +#define CYGNUM_HAL_VECTOR_SIGUSR2 12 +#define CYGNUM_HAL_VECTOR_SIGPIPE 13 +#define CYGNUM_HAL_VECTOR_SIGALRM 14 +#define CYGNUM_HAL_VECTOR_SIGTERM 15 +#define CYGNUM_HAL_VECTOR_SIGCHLD 17 +#define CYGNUM_HAL_VECTOR_SIGCONT 18 +#define CYGNUM_HAL_VECTOR_SIGSTOP 19 +#define CYGNUM_HAL_VECTOR_SIGTSTP 20 +#define CYGNUM_HAL_VECTOR_SIGTTIN 21 +#define CYGNUM_HAL_VECTOR_SIGTTOU 22 +#define CYGNUM_HAL_VECTOR_SIGURG 23 +#define CYGNUM_HAL_VECTOR_SIGXCPU 24 +#define CYGNUM_HAL_VECTOR_SIGXFSZ 25 +#define CYGNUM_HAL_VECTOR_SIGVTALRM 26 +#define CYGNUM_HAL_VECTOR_SIGPROF 27 +#define CYGNUM_HAL_VECTOR_SIGWINCH 28 +#define CYGNUM_HAL_VECTOR_SIGIO 29 +#define CYGNUM_HAL_VECTOR_SIGPWR 30 + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VECTOR_SIGPWR +#define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 ) + +// Generic exception vector names +#define CYGNUM_HAL_EXCEPTION_INTERRUPT CYGNUM_HAL_VECTOR_SIGINT +#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION CYGNUM_HAL_VECTOR_SIGILL +#define CYGNUM_HAL_EXCEPTION_TRAP CYGNUM_HAL_VECTOR_SIGTRAP +#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_SIGBUS +#define CYGNUM_HAL_EXCEPTION_FPU CYGNUM_HAL_VECTOR_SIGFPE +#define CYGNUM_HAL_EXCEPTION_STACK_OVERFLOW CYGNUM_HAL_VECTOR_SIGSEGV + +#define CYGNUM_HAL_EXCEPTION_MIN 0 +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_STACK_OVERFLOW +#define CYGNUM_HAL_EXCEPTION_COUNT ( CYGNUM_HAL_EXCEPTION_MAX + 1 ) + +// The vector used by the Real time clock +#ifdef CYGSEM_HAL_I386_LINUX_REAL_TIME +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_VECTOR_SIGALRM +#else +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_VECTOR_SIGVTALRM +#endif + +//-------------------------------------------------------------------------- +// Static data used by HAL + +// Interrupt controler emulation variables. +externC volatile int cyg_hal_interrupts_disabled; +externC volatile int cyg_hal_interrupts_deferred; +externC volatile int cyg_hal_interrupts_unhandled[CYGNUM_HAL_ISR_COUNT]; + +//-------------------------------------------------------------------------- +// Interrupt control macros + +externC void cyg_hal_default_interrupt_vsr(int vector); +externC void cyg_hal_default_exception_vsr(int vector); +externC int cyg_hal_sys_sigprocmask(int, const long*, long*); + +// FIXME: These should use block/unblock of the signals instead of +// cyg_hal_interrupts_disabled. + +#define HAL_ENABLE_INTERRUPTS() \ + CYG_MACRO_START \ + cyg_ucount8 _i_; \ + cyg_hal_interrupts_disabled = 0; \ + if (cyg_hal_interrupts_deferred) { \ + cyg_hal_interrupts_deferred = 0; \ + for (_i_ = CYGNUM_HAL_ISR_MIN; _i_ <= CYGNUM_HAL_ISR_MAX; _i_++) { \ + if (cyg_hal_interrupts_unhandled[_i_]) { \ + cyg_hal_default_interrupt_vsr(_i_); \ + } \ + } \ + } \ + CYG_MACRO_END + +#define HAL_DISABLE_INTERRUPTS(_old_) \ + CYG_MACRO_START \ + (_old_) = cyg_hal_interrupts_disabled++; \ + CYG_MACRO_END + +#define HAL_RESTORE_INTERRUPTS(_old_) \ + CYG_MACRO_START \ + cyg_ucount8 _i_; \ + cyg_hal_interrupts_disabled = (_old_); \ + if (0 == cyg_hal_interrupts_disabled) { \ + if (cyg_hal_interrupts_deferred) { \ + cyg_hal_interrupts_deferred = 0; \ + for (_i_ = CYGNUM_HAL_ISR_MIN; _i_ <= CYGNUM_HAL_ISR_MAX; \ + _i_++){ \ + if (cyg_hal_interrupts_unhandled[_i_]) { \ + cyg_hal_default_interrupt_vsr(_i_); \ + } \ + } \ + } \ + } \ + CYG_MACRO_END + +#define HAL_QUERY_INTERRUPTS(_old_) \ + CYG_MACRO_START \ + (_old_) = !cyg_hal_interrupts_disabled; \ + CYG_MACRO_END + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ + CYG_MACRO_START \ + cyg_hal_interrupts_unhandled[_vector_] = 0; \ + CYG_MACRO_END + +//--------------------------------------------------------------------------- +// Translate a vector number into an ISR table index. + +// The native linux port doesn't support chained interrupts --proven 19981005 +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_) + +//--------------------------------------------------------------------------- +// Interrupt controller access + +#define LINUX_SIG_BLOCK 0 +#define LINUX_SIG_UNBLOCK 1 + +#define HAL_INTERRUPT_MASK( _vector_ ) \ + CYG_MACRO_START \ + long _old_, _new_; \ + _new_ = 1 << (_vector_); \ + cyg_hal_sys_sigprocmask(LINUX_SIG_BLOCK, &_new_, &_old_); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ + CYG_MACRO_START \ + long _old_, _new_; \ + _new_ = 1 << (_vector_); \ + cyg_hal_sys_sigprocmask(LINUX_SIG_UNBLOCK, &_new_, &_old_); \ + CYG_MACRO_END + +// The native linux port doesn't have configurable interrupts. +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) + +// The native linux port doesn't have interrupt levels. +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) + +//--------------------------------------------------------------------------- +// Clock control + +struct hal_timeval { + long tv_sec; + long tv_usec; +}; +struct hal_itimerval { + struct hal_timeval it_interval; + struct hal_timeval it_value; +}; + +externC int cyg_hal_sys_setitimer(int, const struct hal_itimerval*, + struct hal_itimerval*); +externC int cyg_hal_sys_getitimer(int, struct hal_itimerval*); + +#ifdef CYGSEM_HAL_I386_LINUX_REAL_TIME +#define CYGNUM_HAL_TIMER_TYPE 0 // ITIMER_REAL +#else +#define CYGNUM_HAL_TIMER_TYPE 1 // ITIMER_VIRTUAL +#endif + +#define HAL_CLOCK_INITIALIZE( _period_ ) \ + CYG_MACRO_START \ + struct hal_itimerval new_itimerval, old; \ + \ + new_itimerval.it_interval.tv_sec = 0; \ + new_itimerval.it_interval.tv_usec = (_period_); \ + new_itimerval.it_value.tv_sec = 0; \ + new_itimerval.it_value.tv_usec = (_period_); \ + /* Use setitimer to set the realtime clock */ \ + cyg_hal_sys_setitimer(CYGNUM_HAL_TIMER_TYPE, &new_itimerval, &old); \ + CYG_MACRO_END + +// The sigalarm runs in one-shot mode. We have to re-enable it +#define HAL_CLOCK_RESET( _vector_, _period_ ) \ + HAL_INTERRUPT_UNMASK( _vector_ ) + +// This timer counts down, so subtract from set value. +#define HAL_CLOCK_READ( _pvalue_ ) \ + CYG_MACRO_START \ + struct hal_itimerval old_itimerval; \ + cyg_hal_sys_getitimer(CYGNUM_HAL_TIMER_TYPE, &old_itimerval); \ + *(_pvalue_) = old_itimerval.it_interval.tv_usec - \ + old_itimerval.it_value.tv_usec; \ + CYG_MACRO_END + +#define HAL_CLOCK_LATENCY( _pvalue_ ) \ + HAL_CLOCK_READ((_pvalue_)) + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/i386/linux/current/include/var_intr.h @@ -0,0 +1,64 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H + +//========================================================================== +// +// var_intr.h +// +// i386/Linux Interrupt and clock support +// +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): proven +// Contributors: proven, jskov, pjo +// Date: 1999-10-15 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock. +// +// Usage: +// #include <cyg/hal/var_intr.h> +// ... +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_i386.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/plf_intr.h> + +//--------------------------------------------------------------------------- + +// Nothing in here at present, + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_VAR_INTR_H +// End of var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/i386/linux/current/include/variant.inc @@ -0,0 +1,56 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## Linux synthetic target variant support +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov, pjo, nickg +## Date: 1999-01-07 +## Purpose: Linux synthetic target variant support +## Description: This file contains any i386 variant specific assembler macros +## needed to run eCos on a Linux synthetic target. It is here mainly +## to retain compatibility with other HALs. +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + + +#include <pkgconf/hal.h> +#include <cyg/hal/i386.inc> +//#include <cyg/hal/platform.inc> + +##============================================================================= +#endif // ifndef CYGONCE_HAL_VARIANT_INC +## end of variant.inc
--- a/packages/hal/i386/linux/current/src/hal_diag.c +++ b/packages/hal/i386/linux/current/src/hal_diag.c @@ -67,7 +67,16 @@ void hal_diag_write_char(char __c) __buffer[__index++] = __c; if ('\n' == __c || 128 == __index) { - cyg_hal_sys_write(1, &__buffer[0], __index); + cyg_int32 __written; + cyg_uint8* __p = __buffer; + + while (__index > 0) { + __written = cyg_hal_sys_write(1, __p, __index); + if (__written > 0) { + __index -= __written; + __p += __written; + } + } cyg_hal_sys_fdatasync(1); __index = 0; }
--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -16,8 +16,9 @@ 1999-12-21 Jonathan Larmour <jlarmour@ CYG_HAL_USE_ROM_MONITOR_CYGMON -> CYGSEM_HAL_USE_ROM_MONITOR_CygMon Rename CYG_HAL_ROM_MONITOR -> CYGSEM_HAL_ROM_MONITOR - * src/hal_misc.c (hal_default_isr): Rename CYG_HAL_USE_ROM_MONITOR_CYGMON - -> CYGSEM_HAL_USE_ROM_MONITOR_CygMon + * src/hal_misc.c (hal_default_isr): Rename + CYG_HAL_USE_ROM_MONITOR_CYGMON -> + CYGSEM_HAL_USE_ROM_MONITOR_CygMon * include/arch.inc: Rename CYG_HAL_USE_ROM_MONITOR -> CYGSEM_HAL_USE_ROM_MONITOR
--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,5 +1,12 @@ 2000-02-11 Jesper Skov <jskov@redhat.com> + * include/hal_cache.h: + * include/hal_mem.h: + Moved memory mapping definition to new file. + + * include/hal_cache.h: Deleted 60x macros. + + * src/hal_misc.c: Moved MMU functions to variant files. * src/hal_intr.c (hal_IRQ_init): Moved code to MPC8xx variant directory.
--- a/packages/hal/powerpc/arch/current/include/hal_cache.h +++ b/packages/hal/powerpc/arch/current/include/hal_cache.h @@ -56,173 +56,6 @@ #include <cyg/hal/var_cache.h> - -//============================================================================= -// Memory mapping -typedef struct { - CYG_ADDRESS virtual_addr; - CYG_ADDRESS physical_addr; - cyg_int32 size; - cyg_uint8 flags; -} cyg_memdesc_t; - -// each platform HAL must provide one of these to describe how memory -// should be mapped/cached, ideally weak aliased so that apps can override: -externC cyg_memdesc_t cyg_hal_mem_map[]; - -#define CYGARC_MEMDESC_CI 1 // cache inhibit -#define CYGARC_MEMDESC_GUARDED 2 // guarded - -// these macros should ease that task, and ease any future extension of the -// structure (physical == virtual addresses): -#define CYGARC_MEMDESC_CACHE( _va_, _sz_ ) \ - { (_va_), (_va_), (_sz_), 0 } - -#define CYGARC_MEMDESC_NOCACHE( _va_, _sz_ ) \ - { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_CI } - -#define CYGARC_MEMDESC_CACHEGUARD( _va_, _sz_ ) \ - { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED } - -#define CYGARC_MEMDESC_NOCACHEGUARD( _va_, _sz_ ) \ - { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED|CYGARC_MEMDESC_CI } - -#define CYGARC_MEMDESC_TABLE_END {0, 0, 0, 0} -#define CYGARC_MEMDESC_TABLE cyg_memdesc_t cyg_hal_mem_map[] -#define CYGARC_MEMDESC_EMPTY_TABLE { CYGARC_MEMDESC_TABLE_END } - -//============================================================================= -// PowerPC simulator - -#ifdef CYGPKG_HAL_POWERPC_SIM - -//----------------------------------------------------------------------------- -// Cache dimensions - -// Data cache -#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes -#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line -#define HAL_DCACHE_WAYS 2 // Associativity of the cache - -// Instruction cache -#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes -#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line -#define HAL_ICACHE_WAYS 2 // Associativity of the cache - -#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) -#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) - -//----------------------------------------------------------------------------- -// Global control of data cache - -// Enable the data cache -#define HAL_DCACHE_ENABLE() - -// Disable the data cache -#define HAL_DCACHE_DISABLE() - -// Invalidate the entire cache -#define HAL_DCACHE_INVALIDATE_ALL() - -// Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() - -// Query the state of the data cache -#define HAL_DCACHE_IS_ENABLED(_state_) \ - CYG_MACRO_START \ - (_state_) = 0; \ - CYG_MACRO_END - -// Set the data cache refill burst size -//#define HAL_DCACHE_BURST_SIZE(_size_) - -// Set the data cache write mode -//#define HAL_DCACHE_WRITE_MODE( _mode_ ) - -//#define HAL_DCACHE_WRITETHRU_MODE 0 -//#define HAL_DCACHE_WRITEBACK_MODE 1 - -// Load the contents of the given address range into the data cache -// and then lock the cache so that it stays there. -//#define HAL_DCACHE_LOCK(_base_, _size_) - -// Undo a previous lock operation -//#define HAL_DCACHE_UNLOCK(_base_, _size_) - -// Unlock entire cache -//#define HAL_DCACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Data cache line control - -// Allocate cache lines for the given address range without reading its -// contents from memory. -//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) - -// Write dirty cache lines to memory and invalidate the cache entries -// for the given address range. -//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) - -// Invalidate cache lines in the given range without writing to memory. -//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) - -// Write dirty cache lines to memory for the given address range. -//#define HAL_DCACHE_STORE( _base_ , _size_ ) - -// Preread the given range into the cache with the intention of reading -// from it later. -//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) - -// Preread the given range into the cache with the intention of writing -// to it later. -//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) - -// Allocate and zero the cache lines associated with the given range. -//#define HAL_DCACHE_ZERO( _base_ , _size_ ) - -//----------------------------------------------------------------------------- -// Global control of Instruction cache - -// Enable the instruction cache -#define HAL_ICACHE_ENABLE() - -// Disable the instruction cache -#define HAL_ICACHE_DISABLE() - -// Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() - -// Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() - -// Query the state of the instruction cache -#define HAL_ICACHE_IS_ENABLED(_state_) \ - CYG_MACRO_START \ - (_state_) = 0; \ - CYG_MACRO_END - -// Set the instruction cache refill burst size -//#define HAL_ICACHE_BURST_SIZE(_size_) - -// Load the contents of the given address range into the instruction cache -// and then lock the cache so that it stays there. -//#define HAL_ICACHE_LOCK(_base_, _size_) - -// Undo a previous lock operation -//#define HAL_ICACHE_UNLOCK(_base_, _size_) - -// Unlock entire cache -//#define HAL_ICACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Instruction cache line control - -// Invalidate cache lines in the given range without writing to memory. -//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) - - -#endif - //----------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_CACHE_H // End of hal_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/arch/current/include/hal_mem.h @@ -0,0 +1,99 @@ +#ifndef CYGONCE_HAL_MEM_H +#define CYGONCE_HAL_MEM_H + +//============================================================================= +// +// hal_mem.h +// +// HAL memory control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg, jskov, hmt +// Date: 2000-02-11 +// Purpose: Memory control API +// Description: The macros defined here provide the HAL APIs for handling +// simple memory management operations. +// Usage: +// #include <cyg/hal/hal_mem.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +//============================================================================= +// Memory mapping +typedef struct { + CYG_ADDRESS virtual_addr; + CYG_ADDRESS physical_addr; + cyg_int32 size; + cyg_uint8 flags; +} cyg_memdesc_t; + +// each variant HAL must provide these functions for mapping/clearing +// (simple BAT/TLB) memory mappings. +externC int +cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, + cyg_int32 size, cyg_uint8 flags); +externC void +cyg_hal_clear_MMU (void); + +// each platform HAL must provide one of these to describe how memory +// should be mapped/cached, ideally weak aliased so that apps can override: +externC cyg_memdesc_t cyg_hal_mem_map[]; + +#define CYGARC_MEMDESC_CI 1 // cache inhibit +#define CYGARC_MEMDESC_GUARDED 2 // guarded + +// these macros should ease that task, and ease any future extension of the +// structure (physical == virtual addresses): +#define CYGARC_MEMDESC_CACHE( _va_, _sz_ ) \ + { (_va_), (_va_), (_sz_), 0 } + +#define CYGARC_MEMDESC_NOCACHE( _va_, _sz_ ) \ + { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_CI } + +#define CYGARC_MEMDESC_CACHEGUARD( _va_, _sz_ ) \ + { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED } + +#define CYGARC_MEMDESC_NOCACHEGUARD( _va_, _sz_ ) \ + { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED|CYGARC_MEMDESC_CI } + +#define CYGARC_MEMDESC_TABLE_END {0, 0, 0, 0} +#define CYGARC_MEMDESC_TABLE cyg_memdesc_t cyg_hal_mem_map[] +#define CYGARC_MEMDESC_EMPTY_TABLE { CYGARC_MEMDESC_TABLE_END } + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_MEM_H +// End of hal_mem.h
--- a/packages/hal/powerpc/arch/current/src/hal_misc.c +++ b/packages/hal/powerpc/arch/current/src/hal_misc.c @@ -59,6 +59,7 @@ defined(CYGPKG_HAL_EXCEPTIONS) # include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions #endif +#include <cyg/hal/hal_mem.h> // HAL memory handling //--------------------------------------------------------------------------- // Functions used during initialization. @@ -249,218 +250,24 @@ hal_idle_thread_action( cyg_uint32 count //--------------------------------------------------------------------------- // Use MMU resources to map memory regions. -// Takes and returns an int used to ID the MMU resource to use. This ID -// is increased as resources are used and should be used for subsequent -// invocations. -static int -hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, - cyg_int32 size, cyg_uint8 flags) -{ -#ifdef CYGPKG_HAL_POWERPC_MPC603 - { - // Use BATs to map the memory. - cyg_uint32 ubat, lbat; - - ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP; - lbat = (phys & LBAT_BRPNMASK); - if (flags & CYGARC_MEMDESC_CI) - lbat |= LBAT_I; - if (flags & CYGARC_MEMDESC_GUARDED) - lbat |= LBAT_G; - - // There are 4 BATs, size is programmable. - while (id < 4 && size > 0) { - cyg_uint32 blk_size = 128*1024; - cyg_uint32 bl = 0; - while (blk_size < 256*1024*1024 && blk_size < size) { - blk_size *= 2; - bl = (bl << 1) | 1; - } - ubat = (ubat & ~UBAT_BLMASK) | (bl << 2); - - switch (id) { - case 0: - CYGARC_MTSPR (IBAT0U, ubat); - CYGARC_MTSPR (IBAT0L, lbat); - CYGARC_MTSPR (DBAT0U, ubat); - CYGARC_MTSPR (DBAT0L, lbat); - break; - case 1: - CYGARC_MTSPR (IBAT1U, ubat); - CYGARC_MTSPR (IBAT1L, lbat); - CYGARC_MTSPR (DBAT1U, ubat); - CYGARC_MTSPR (DBAT1L, lbat); - break; - case 2: - CYGARC_MTSPR (IBAT2U, ubat); - CYGARC_MTSPR (IBAT2L, lbat); - CYGARC_MTSPR (DBAT2U, ubat); - CYGARC_MTSPR (DBAT2L, lbat); - break; - case 3: - CYGARC_MTSPR (IBAT3U, ubat); - CYGARC_MTSPR (IBAT3L, lbat); - CYGARC_MTSPR (DBAT3U, ubat); - CYGARC_MTSPR (DBAT3L, lbat); - break; - } - - size -= blk_size; - id++; - } - } -#endif - - -#ifdef CYGPKG_HAL_POWERPC_MPC8xx - { - // The MPC8xx CPUs do not have BATs. Fortunately we don't - // currently use the MMU, so we can simulate BATs by using the - // TLBs. - - cyg_uint32 epn, rpn, ctr, twc; - int max_tlbs; - -#if defined(CYGPKG_HAL_POWERPC_MPC860) - // There are 32 TLBs. - max_tlbs = 32; -#endif -#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) - // There are 8 TLBs. - max_tlbs = 8; -#endif - - epn = (virt & MI_EPN_EPNMASK) | MI_EPN_EV; - rpn = ((phys & MI_RPN_RPNMASK) - | MI_RPN_PPRWRW | MI_RPN_LPS | MI_RPN_SH | MI_RPN_V); - if (flags & CYGARC_MEMDESC_CI) - rpn |= MI_RPN_CI; - - twc = MI_TWC_PS8MB | MI_TWC_V; - if (flags & CYGARC_MEMDESC_GUARDED) - twc |= MI_TWC_G; - - // Ignore attempts to use more than max_tlbs. - while (id < max_tlbs && size > 0) { - ctr = id << MI_CTR_INDX_SHIFT; - - // Instruction TLB. - CYGARC_MTSPR (MI_TWC, twc); - CYGARC_MTSPR (MI_CTR, ctr); - CYGARC_MTSPR (MI_EPN, epn); - CYGARC_MTSPR (MI_RPN, rpn); - - // Data TLB. - { - cyg_uint32 drpn; - - // Need to mark data page as changed or an exception - // will be generated on first write to the page. - drpn = rpn | MD_RPN_CHANGED; - - CYGARC_MTSPR (MD_TWC, twc); - CYGARC_MTSPR (MD_CTR, ctr); - CYGARC_MTSPR (MD_EPN, epn); - CYGARC_MTSPR (MD_RPN, drpn); - } - - // Move to next 8MB block. - size -= 8*1024*1024; - epn += 8*1024*1024; - rpn += 8*1024*1024; - id++; - } - } -#endif - - return id; -} - - -// Initialize MMU to a sane (NOP) state. -static void -hal_clear_MMU (void) -{ -#ifdef CYGPKG_HAL_POWERPC_MPC603 - { - cyg_uint32 ubat, lbat; - - // Initialize BATs with 0 -- VS&VP are unset, making all matches fail - ubat = 0; - lbat = 0; - - CYGARC_MTSPR (IBAT0U, ubat); - CYGARC_MTSPR (IBAT0L, lbat); - CYGARC_MTSPR (DBAT0U, ubat); - CYGARC_MTSPR (DBAT0L, lbat); - CYGARC_MTSPR (IBAT1U, ubat); - CYGARC_MTSPR (IBAT1L, lbat); - CYGARC_MTSPR (DBAT1U, ubat); - CYGARC_MTSPR (DBAT1L, lbat); - CYGARC_MTSPR (IBAT2U, ubat); - CYGARC_MTSPR (IBAT2L, lbat); - CYGARC_MTSPR (DBAT2U, ubat); - CYGARC_MTSPR (DBAT2L, lbat); - CYGARC_MTSPR (IBAT3U, ubat); - CYGARC_MTSPR (IBAT3L, lbat); - CYGARC_MTSPR (DBAT3U, ubat); - CYGARC_MTSPR (DBAT3L, lbat); - } -#endif - -#ifdef CYGPKG_HAL_POWERPC_MPC8xx - { - // Initialize TLBs with 0, Valid bits unset. - - cyg_uint32 ctr; - int id; - int max_tlbs; - -#if defined(CYGPKG_HAL_POWERPC_MPC860) - // There are 32 TLBs. - max_tlbs = 32; -#endif -#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) - // There are 8 TLBs. - max_tlbs = 8; -#endif - - CYGARC_MTSPR (M_CASID, 0); - - for (id = 0; id < max_tlbs; id++) { - ctr = id << MI_CTR_INDX_SHIFT; - - // Instruction TLBs. - CYGARC_MTSPR (MI_TWC, 0); - CYGARC_MTSPR (MI_CTR, ctr); - CYGARC_MTSPR (MI_EPN, 0); - CYGARC_MTSPR (MI_RPN, 0); - // Data TLBs. - CYGARC_MTSPR (MD_TWC, 0); - CYGARC_MTSPR (MD_CTR, ctr); - CYGARC_MTSPR (MD_EPN, 0); - CYGARC_MTSPR (MD_RPN, 0); - } - } -#endif -} - -// NB this demands that the platform HAL has provided an +// This relies that the platform HAL providing an // externC cyg_memdesc_t cyg_hal_mem_map[]; -// as detailed in hal_cache.h: -externC void hal_MMU_init (void) +// as detailed in hal_cache.h, and the variant HAL providing the +// MMU mapping/clear functions. +externC void +hal_MMU_init (void) { int id = 0; int i = 0; - hal_clear_MMU (); + cyg_hal_clear_MMU (); while (cyg_hal_mem_map[i].size) { - id = hal_map_memory (id, - cyg_hal_mem_map[i].virtual_addr, - cyg_hal_mem_map[i].physical_addr, - cyg_hal_mem_map[i].size, - cyg_hal_mem_map[i].flags); + id = cyg_hal_map_memory (id, + cyg_hal_mem_map[i].virtual_addr, + cyg_hal_mem_map[i].physical_addr, + cyg_hal_mem_map[i].size, + cyg_hal_mem_map[i].flags); i++; } }
--- a/packages/hal/powerpc/arch/current/src/vectors.S +++ b/packages/hal/powerpc/arch/current/src/vectors.S @@ -477,7 +477,7 @@ cyg_hal_default_exception_vsr: slwi \dreg,\dreg,2 # convert to word offset. .endm -#endif // CYGPKG_HAL_POWERPC_MPC8xx +#endif // CYGPKG_HAL_POWERPC_INTC_DEFINED #--------------------------------------------------------------------------- # Common interrupt handling code.
--- a/packages/hal/powerpc/cogent/current/ChangeLog +++ b/packages/hal/powerpc/cogent/current/ChangeLog @@ -1,3 +1,7 @@ +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/hal_aux.c: Cleaned up includes. + 2000-02-10 Jesper Skov <jskov@redhat.com> * include/plf_stub.h:
--- a/packages/hal/powerpc/cogent/current/src/hal_aux.c +++ b/packages/hal/powerpc/cogent/current/src/hal_aux.c @@ -42,15 +42,7 @@ //============================================================================= #include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> // base types -#include <cyg/infra/cyg_trac.h> // tracing macros -#include <cyg/infra/cyg_ass.h> // assertion macros - -#include <cyg/hal/hal_io.h> // IO macros -#include <cyg/hal/hal_diag.h> -#include <cyg/hal/hal_intr.h> // Interrupt macros -#include <cyg/hal/hal_cache.h> // Cache macros +#include <cyg/hal/hal_mem.h> // HAL memory definitions // The memory map is weakly defined, allowing the application to redefine // it if necessary. The regions defined below are the minimum requirements.
--- a/packages/hal/powerpc/fads/current/ChangeLog +++ b/packages/hal/powerpc/fads/current/ChangeLog @@ -1,3 +1,11 @@ +2000-02-17 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/pkgconf/hal_powerpc_fads.h: Fix PPC8xx -> MPC8xx typo + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/hal_aux.c: Cleaned up includes. + 2000-02-10 Jesper Skov <jskov@redhat.com> * include/plf_stub.h:
--- a/packages/hal/powerpc/fads/current/include/pkgconf/hal_powerpc_fads.h +++ b/packages/hal/powerpc/fads/current/include/pkgconf/hal_powerpc_fads.h @@ -71,7 +71,7 @@ display "Motorola FADS PowerPC evaluation board" type radio parent CYGPKG_HAL_POWERPC - requires CYGPKG_HAL_POWERPC_PPC8xx + requires CYGPKG_HAL_POWERPC_MPC8xx requires !CYGSEM_HAL_USE_ROM_MONITOR platform fads description "
--- a/packages/hal/powerpc/fads/current/src/hal_aux.c +++ b/packages/hal/powerpc/fads/current/src/hal_aux.c @@ -42,15 +42,7 @@ //============================================================================= #include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> // base types -#include <cyg/infra/cyg_trac.h> // tracing macros -#include <cyg/infra/cyg_ass.h> // assertion macros - -#include <cyg/hal/hal_io.h> // IO macros -#include <cyg/hal/hal_diag.h> -#include <cyg/hal/hal_intr.h> // Interrupt macros -#include <cyg/hal/hal_cache.h> // Cache macros +#include <cyg/hal/hal_mem.h> // HAL memory definitions // The memory map is weakly defined, allowing the application to redefine // it if necessary. The regions defined below are the minimum requirements.
--- a/packages/hal/powerpc/mbx/current/ChangeLog +++ b/packages/hal/powerpc/mbx/current/ChangeLog @@ -1,3 +1,11 @@ +2000-02-17 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/pkgconf/hal_powerpc_mbx.h: Fix MPC860 -> MPC8xx typo + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/hal_aux.c: Cleaned up includes. + 2000-02-10 Jesper Skov <jskov@redhat.com> * include/plf_stub.h:
--- a/packages/hal/powerpc/mbx/current/include/pkgconf/hal_powerpc_mbx.h +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/hal_powerpc_mbx.h @@ -52,7 +52,7 @@ type radio parent CYGPKG_HAL_POWERPC requires CYGPKG_HAL_QUICC - requires CYGPKG_HAL_POWERPC_MPC860 + requires CYGPKG_HAL_POWERPC_MPC8xx platform mbx description " The MBX HAL package provides the support needed to run
--- a/packages/hal/powerpc/mbx/current/src/hal_aux.c +++ b/packages/hal/powerpc/mbx/current/src/hal_aux.c @@ -42,15 +42,7 @@ //============================================================================= #include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> // base types -#include <cyg/infra/cyg_trac.h> // tracing macros -#include <cyg/infra/cyg_ass.h> // assertion macros - -#include <cyg/hal/hal_io.h> // IO macros -#include <cyg/hal/hal_diag.h> -#include <cyg/hal/hal_intr.h> // Interrupt macros -#include <cyg/hal/hal_cache.h> // Cache macros +#include <cyg/hal/hal_mem.h> // HAL memory definitions // The memory map is weakly defined, allowing the application to redefine // it if necessary. The regions defined below are the minimum requirements.
--- a/packages/hal/powerpc/mpc8xx/current/ChangeLog +++ b/packages/hal/powerpc/mpc8xx/current/ChangeLog @@ -1,5 +1,12 @@ +2000-02-14 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/hal_powerpc_mpc8xx.h: Added simple config for + 1st level arbiter. + 2000-02-11 Jesper Skov <jskov@redhat.com> + * src/var_misc.c: Moved MMU functions here. + * src/var_intr.c (Cyg_InterruptHANDLED): Mask out CALL_DSR flag before return.
--- a/packages/hal/powerpc/mpc8xx/current/include/pkgconf/hal_powerpc_mpc8xx.h +++ b/packages/hal/powerpc/mpc8xx/current/include/pkgconf/hal_powerpc_mpc8xx.h @@ -64,13 +64,36 @@ cdl_option CYGPKG_HAL_POWERPC_MPC860 { display "MPC860 microprocessor" - parent CYGPKG_HAL_POWERPC_MPC860 + parent CYGPKG_HAL_POWERPC_MPC8xx type radio description " The MPC860 microprocessor. This is an embedded part that in addition to the PowerPC processor core has built in peripherals such as memory controllers, DMA controllers, serial ports and timers/counters." + + + cdl_component CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE { + display "Enable CPM interrupts" + paernt CYGPKG_HAL_POWERPC_MPC860 + type boolean + description " + This option causes the CPM interrupt arbiter to be attached + at startup, and CPM interrupts are enabled. Enabling CPM + level interrupt arbitration and handling must still be + done by the application code. See intr0.c test for an + example." + + cdl_component CYGSEM_HAL_POWERPC_MPC860_CPM_LVL { + display "CPM interrupt level on the SIU" + type count + legal_values 0 to 7 + parent CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE + description " + This option selects which SIU level the CPM interrupts + should be routed to." + } + } } }}CFG_DATA */ @@ -85,6 +108,10 @@ #define CYGPKG_HAL_POWERPC_MSBFIRST // Big-endian CPU #define CYGSEM_HAL_USE_ROM_MONITOR +// CPM options +#define CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE +#define CYGSEM_HAL_POWERPC_MPC860_CPM_LVL 7 + //---------------------------------------------------------------------- #endif // CYGONCE_PKGCONF_HAL_POWERPC_MPC8XX_H // EOF hal_powerpc_mpc8xx.h
--- a/packages/hal/powerpc/mpc8xx/current/src/var_misc.c +++ b/packages/hal/powerpc/mpc8xx/current/src/var_misc.c @@ -42,9 +42,122 @@ // //========================================================================== +#include <pkgconf/hal.h> + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <cyg/hal/ppc_regs.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_mem.h> + +//-------------------------------------------------------------------------- void hal_variant_init(void) { } +//--------------------------------------------------------------------------- +// Use MMU resources to map memory regions. +// Takes and returns an int used to ID the MMU resource to use. This ID +// is increased as resources are used and should be used for subsequent +// invocations. +// +// The MPC8xx CPUs do not have BATs. Fortunately we don't currently +// use the MMU, so we can simulate BATs by using the TLBs. +int +cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, + cyg_int32 size, cyg_uint8 flags) +{ + cyg_uint32 epn, rpn, ctr, twc; + int max_tlbs; + +#if defined(CYGPKG_HAL_POWERPC_MPC860) + // There are 32 TLBs. + max_tlbs = 32; +#elif defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) + // There are 8 TLBs. + max_tlbs = 8; +#endif + + epn = (virt & MI_EPN_EPNMASK) | MI_EPN_EV; + rpn = ((phys & MI_RPN_RPNMASK) + | MI_RPN_PPRWRW | MI_RPN_LPS | MI_RPN_SH | MI_RPN_V); + if (flags & CYGARC_MEMDESC_CI) + rpn |= MI_RPN_CI; + + twc = MI_TWC_PS8MB | MI_TWC_V; + if (flags & CYGARC_MEMDESC_GUARDED) + twc |= MI_TWC_G; + + // Ignore attempts to use more than max_tlbs. + while (id < max_tlbs && size > 0) { + ctr = id << MI_CTR_INDX_SHIFT; + + // Instruction TLB. + CYGARC_MTSPR (MI_TWC, twc); + CYGARC_MTSPR (MI_CTR, ctr); + CYGARC_MTSPR (MI_EPN, epn); + CYGARC_MTSPR (MI_RPN, rpn); + + // Data TLB. + { + cyg_uint32 drpn; + + // Need to mark data page as changed or an exception + // will be generated on first write to the page. + drpn = rpn | MD_RPN_CHANGED; + + CYGARC_MTSPR (MD_TWC, twc); + CYGARC_MTSPR (MD_CTR, ctr); + CYGARC_MTSPR (MD_EPN, epn); + CYGARC_MTSPR (MD_RPN, drpn); + } + + // Move to next 8MB block. + size -= 8*1024*1024; + epn += 8*1024*1024; + rpn += 8*1024*1024; + id++; + } + + return id; +} + + +// Initialize MMU to a sane (NOP) state. +// +// Initialize TLBs with 0, Valid bits unset. +void +cyg_hal_clear_MMU (void) +{ + cyg_uint32 ctr; + int id; + int max_tlbs; + +#if defined(CYGPKG_HAL_POWERPC_MPC860) + // There are 32 TLBs. + max_tlbs = 32; +#elif defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) + // There are 8 TLBs. + max_tlbs = 8; +#endif + + CYGARC_MTSPR (M_CASID, 0); + + for (id = 0; id < max_tlbs; id++) { + ctr = id << MI_CTR_INDX_SHIFT; + + // Instruction TLBs. + CYGARC_MTSPR (MI_TWC, 0); + CYGARC_MTSPR (MI_CTR, ctr); + CYGARC_MTSPR (MI_EPN, 0); + CYGARC_MTSPR (MI_RPN, 0); + // Data TLBs. + CYGARC_MTSPR (MD_TWC, 0); + CYGARC_MTSPR (MD_CTR, ctr); + CYGARC_MTSPR (MD_EPN, 0); + CYGARC_MTSPR (MD_RPN, 0); + } +} + //-------------------------------------------------------------------------- // End of var_misc.c
--- a/packages/hal/powerpc/ppc60x/current/ChangeLog +++ b/packages/hal/powerpc/ppc60x/current/ChangeLog @@ -1,5 +1,9 @@ 2000-02-11 Jesper Skov <jskov@redhat.com> + * src/var_intr.c: include cyg_type header. + + * src/var_misc.c (hal_clear_MMU): Moved MMU functions here. + * src/PKGconf.mak (COMPILE): Added var_intr.c
--- a/packages/hal/powerpc/ppc60x/current/src/var_intr.c +++ b/packages/hal/powerpc/ppc60x/current/src/var_intr.c @@ -43,7 +43,7 @@ //========================================================================== #include <pkgconf/hal.h> -#include <cyg/hal/ppc_regs.h> +#include <cyg/infra/cyg_type.h> externC void hal_variant_IRQ_init(void) @@ -53,4 +53,3 @@ hal_variant_IRQ_init(void) // ------------------------------------------------------------------------- // EOF var_intr.c -
--- a/packages/hal/powerpc/ppc60x/current/src/var_misc.c +++ b/packages/hal/powerpc/ppc60x/current/src/var_misc.c @@ -42,9 +42,110 @@ // //========================================================================== +#include <pkgconf/hal.h> + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <cyg/hal/ppc_regs.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_mem.h> + +//-------------------------------------------------------------------------- void hal_variant_init(void) { } +//--------------------------------------------------------------------------- +// Use MMU resources to map memory regions. +// Takes and returns an int used to ID the MMU resource to use. This ID +// is increased as resources are used and should be used for subsequent +// invocations. +int +cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, + cyg_int32 size, cyg_uint8 flags) +{ + // Use BATs to map the memory. + cyg_uint32 ubat, lbat; + + ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP; + lbat = (phys & LBAT_BRPNMASK); + if (flags & CYGARC_MEMDESC_CI) + lbat |= LBAT_I; + if (flags & CYGARC_MEMDESC_GUARDED) + lbat |= LBAT_G; + + // There are 4 BATs, size is programmable. + while (id < 4 && size > 0) { + cyg_uint32 blk_size = 128*1024; + cyg_uint32 bl = 0; + while (blk_size < 256*1024*1024 && blk_size < size) { + blk_size *= 2; + bl = (bl << 1) | 1; + } + ubat = (ubat & ~UBAT_BLMASK) | (bl << 2); + + switch (id) { + case 0: + CYGARC_MTSPR (IBAT0U, ubat); + CYGARC_MTSPR (IBAT0L, lbat); + CYGARC_MTSPR (DBAT0U, ubat); + CYGARC_MTSPR (DBAT0L, lbat); + break; + case 1: + CYGARC_MTSPR (IBAT1U, ubat); + CYGARC_MTSPR (IBAT1L, lbat); + CYGARC_MTSPR (DBAT1U, ubat); + CYGARC_MTSPR (DBAT1L, lbat); + break; + case 2: + CYGARC_MTSPR (IBAT2U, ubat); + CYGARC_MTSPR (IBAT2L, lbat); + CYGARC_MTSPR (DBAT2U, ubat); + CYGARC_MTSPR (DBAT2L, lbat); + break; + case 3: + CYGARC_MTSPR (IBAT3U, ubat); + CYGARC_MTSPR (IBAT3L, lbat); + CYGARC_MTSPR (DBAT3U, ubat); + CYGARC_MTSPR (DBAT3L, lbat); + break; + } + + size -= blk_size; + id++; + } + + return id; +} + + +// Initialize MMU to a sane (NOP) state. +void +cyg_hal_clear_MMU (void) +{ + cyg_uint32 ubat, lbat; + + // Initialize BATs with 0 -- VS&VP are unset, making all matches fail + ubat = 0; + lbat = 0; + + CYGARC_MTSPR (IBAT0U, ubat); + CYGARC_MTSPR (IBAT0L, lbat); + CYGARC_MTSPR (DBAT0U, ubat); + CYGARC_MTSPR (DBAT0L, lbat); + CYGARC_MTSPR (IBAT1U, ubat); + CYGARC_MTSPR (IBAT1L, lbat); + CYGARC_MTSPR (DBAT1U, ubat); + CYGARC_MTSPR (DBAT1L, lbat); + CYGARC_MTSPR (IBAT2U, ubat); + CYGARC_MTSPR (IBAT2L, lbat); + CYGARC_MTSPR (DBAT2U, ubat); + CYGARC_MTSPR (DBAT2L, lbat); + CYGARC_MTSPR (IBAT3U, ubat); + CYGARC_MTSPR (IBAT3L, lbat); + CYGARC_MTSPR (DBAT3U, ubat); + CYGARC_MTSPR (DBAT3L, lbat); +} + //-------------------------------------------------------------------------- // End of var_misc.c
--- a/packages/hal/powerpc/sim/current/ChangeLog +++ b/packages/hal/powerpc/sim/current/ChangeLog @@ -1,3 +1,7 @@ +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/hal_aux.c: Cleaned up includes. + 2000-02-07 Jesper Skov <jskov@redhat.com> * include/pkgconf/hal_powerpc_sim.h:
--- a/packages/hal/powerpc/sim/current/src/hal_aux.c +++ b/packages/hal/powerpc/sim/current/src/hal_aux.c @@ -42,15 +42,7 @@ //============================================================================= #include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> // base types -#include <cyg/infra/cyg_trac.h> // tracing macros -#include <cyg/infra/cyg_ass.h> // assertion macros - -#include <cyg/hal/hal_io.h> // IO macros -#include <cyg/hal/hal_diag.h> -#include <cyg/hal/hal_intr.h> // Interrupt macros -#include <cyg/hal/hal_cache.h> // Cache macros +#include <cyg/hal/hal_mem.h> // HAL memory definitions // The memory map is weakly defined, allowing the application to redefine // it if necessary. The regions defined below are the minimum requirements.
--- a/packages/hal/sparclite/arch/current/ChangeLog +++ b/packages/hal/sparclite/arch/current/ChangeLog @@ -1,3 +1,9 @@ +2000-02-16 Jesper Skov <jskov@redhat.com> + + * src/vectors.S: + * src/hal_boot.c: + CYG_HAL_SPARCLITE_ > CYGPKG_HAL_SPARCELITE_ + 1999-10-15 Hugo Tyson <hmt@cygnus.co.uk> * src/vectors.S (not_window_overflow): Actually the dispatcher
--- a/packages/hal/sparclite/arch/current/src/hal_boot.c +++ b/packages/hal/sparclite/arch/current/src/hal_boot.c @@ -116,7 +116,7 @@ void __gccmain(void) {} /*------------------------------------------------------------------------*/ /* CYG_HAL_START - pre-main-entrypoint */ -#ifdef CYG_HAL_SPARCLITE_SLEB +#ifdef CYGPKG_HAL_SPARCLITE_SLEB #define SLEB_LED (*(volatile char *)(0x02000003)) #define LED( _x_ ) SLEB_LED = (char)(0xff & ~(_x_)) #else
--- a/packages/hal/sparclite/arch/current/src/vectors.S +++ b/packages/hal/sparclite/arch/current/src/vectors.S @@ -63,7 +63,7 @@ # undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT #endif -#if defined( CYG_HAL_SPARCLITE_SIM ) || \ +#if defined( CYGPKG_HAL_SPARCLITE_SIM ) || \ defined( CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK ) #define BOOTUPSTACK_IS_INTERRUPTSTACK #endif
--- a/packages/io/common/current/ChangeLog +++ b/packages/io/common/current/ChangeLog @@ -1,3 +1,11 @@ +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/io_file.c: Use eCos error list <cyg/error/codes.h>. + +2000-02-15 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/io_file.c: Use standard errno.h, not sys/errno.h + 2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> * include/file.h:
--- a/packages/io/common/current/src/io_file.c +++ b/packages/io/common/current/src/io_file.c @@ -47,7 +47,7 @@ #include <pkgconf/io.h> #include <cyg/io/file.h> -#include <sys/errno.h> +#include <cyg/error/codes.h> struct file fds[CYGPKG_IO_NFILE]; @@ -95,4 +95,3 @@ getfp(int fd, struct file **fp) *fp = f; return 0; } -
--- a/packages/io/serial/current/ChangeLog +++ b/packages/io/serial/current/ChangeLog @@ -1,3 +1,15 @@ +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + 2000-02-11 Jesper Skov <jskov@redhat.com> * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY):
--- a/packages/io/serial/current/tests/ser_test_protocol.inl +++ b/packages/io/serial/current/tests/ser_test_protocol.inl @@ -160,6 +160,15 @@ # endif # endif #endif +#if defined(CYGPKG_HAL_I386_PC) \ + && defined(CYGPKG_IO_SERIAL_I386_PC) \ + && defined(CYGPKG_IO_SERIAL_I386_PC_SERIAL0) +# define TEST_CRASH_ID "i386pc" +# define TEST_SER_DEV CYGDAT_IO_SERIAL_I386_PC_SERIAL0_NAME +# if defined(CYGPKG_IO_SERIAL_TTY_TTY0) +# define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY0_DEV +# endif +#endif // We can't rely on haldiag for ser_filter detection - it may not define // a working character reading function.
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -1,3 +1,14 @@ +2000-02-17 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/pkgconf/kernel.h: Make + CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INHERITANCE_SIMPLE a cdl_component + since it has children now + +2000-02-17 Jesper Skov <jskov@redhat.com> + CR101202, CR902078 + * include/mvarimpl.inl: Avoid unlinking the list from the head + during coalescing. + 2000-02-11 Jesper Skov <jskov@redhat.com> * tests/dhrystone.c (PASSES): Reduced for MPC8xx targets.
--- a/packages/kernel/current/include/mvarimpl.inl +++ b/packages/kernel/current/include/mvarimpl.inl @@ -163,7 +163,7 @@ Cyg_Mempool_Variable_Implementation::all return alloced + sizeof(struct memdq); } -// As no coalescing is done, free is simply a matter of using the +// When no coalescing is done, free is simply a matter of using the // freed memory as an element of the free list linking it in at the // start. @@ -199,7 +199,6 @@ Cyg_Mempool_Variable_Implementation::fre if (idq->next > dq) break; } - dq->size = size; if (idq != hdq) { dq->prev = idq; dq->next = idq->next; @@ -211,13 +210,13 @@ Cyg_Mempool_Variable_Implementation::fre idq->prev = dq; dq->prev->next = dq; } - // Now do coalescing - if ((char *)dq + dq->size == (char *)dq->next) { + // Now do coalescing, but leave the head of the list alone. + if (dq->next != hdq && (char *)dq + dq->size == (char *)dq->next) { dq->size += dq->next->size; dq->next = dq->next->next; dq->next->prev = dq; } - if ((char *)dq->prev + dq->prev->size == (char *)dq) { + if (dq->prev != hdq && (char *)dq->prev + dq->prev->size == (char *)dq) { dq->prev->size += dq->size; dq->prev->next = dq->next; dq->next->prev = dq->prev;
--- a/packages/kernel/current/include/pkgconf/kernel.h +++ b/packages/kernel/current/include/pkgconf/kernel.h @@ -710,7 +710,7 @@ # NOTE: the requires statement is only valid for the current kernel. # Priority inheritance is possible in other schedulers as well # but is not yet implemented. - cdl_option CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INHERITANCE_SIMPLE { + cdl_component CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INHERITANCE_SIMPLE { display "Simple mutex priority inheritance" requires CYGSEM_KERNEL_SCHED_MLQUEUE parent CYGPKG_KERNEL_SYNCH