Mercurial > ecos-v3_0-branch
changeset 2755:f935377c1228
* include/var_intr.h: Various fixes to allow external interrupts
to work.
* include/var_io.h: Add AFIO, DMA, SPI and USB definitions.
* src/stm32_misc.c (hal_stm32_gpio_set): Refetch bit number for
setting pullup/down.
line wrap: on
line diff
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi @@ -14,6 +14,7 @@ MEMORY SECTIONS { SECTIONS_BEGIN + SECTION_sram (sram, 0x20000400, LMA_EQ_VMA) SECTION_rom_vectors (ram, 0x68000000, LMA_EQ_VMA) SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi @@ -14,6 +14,7 @@ MEMORY SECTIONS { SECTIONS_BEGIN + SECTION_sram (sram, 0x20000400, LMA_EQ_VMA) SECTION_rom_vectors (ram, 0x68008000, LMA_EQ_VMA) SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi @@ -24,6 +24,7 @@ SECTIONS SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000400, LMA_EQ_VMA) SECTION_data (ram, 0x68000000, FOLLOWING (.got)) SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi @@ -26,6 +26,7 @@ SECTIONS SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA) SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA) SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); SECTIONS_END }
--- a/packages/hal/cortexm/stm32/var/current/ChangeLog +++ b/packages/hal/cortexm/stm32/var/current/ChangeLog @@ -1,3 +1,13 @@ +2009-02-04 Nick Garnett <nickg@ecoscentric.com> + + * include/var_intr.h: Various fixes to allow external interrupts + to work. + + * include/var_io.h: Add AFIO, DMA, SPI and USB definitions. + + * src/stm32_misc.c (hal_stm32_gpio_set): Refetch bit number for + setting pullup/down. + 2008-11-24 Nick Garnett <nickg@ecoscentric.com> * include/var_intr.h (CYGNUM_HAL_INTERRUPT_DMA1_CHX): Rename DMA0
--- a/packages/hal/cortexm/stm32/var/current/include/var_intr.h +++ b/packages/hal/cortexm/stm32/var/current/include/var_intr.h @@ -141,12 +141,9 @@ #define CYGNUM_HAL_INTERRUPT_EXTI13 ( 9+CYGNUM_HAL_INTERRUPT_NVIC_MAX) #define CYGNUM_HAL_INTERRUPT_EXTI14 (10+CYGNUM_HAL_INTERRUPT_NVIC_MAX) #define CYGNUM_HAL_INTERRUPT_EXTI15 (11+CYGNUM_HAL_INTERRUPT_NVIC_MAX) -#define CYGNUM_HAL_INTERRUPT_EXTI16 (12+CYGNUM_HAL_INTERRUPT_NVIC_MAX) -#define CYGNUM_HAL_INTERRUPT_EXTI17 (13+CYGNUM_HAL_INTERRUPT_NVIC_MAX) -#define CYGNUM_HAL_INTERRUPT_EXTI18 (14+CYGNUM_HAL_INTERRUPT_NVIC_MAX) #define CYGNUM_HAL_ISR_MIN 0 -#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_EXTI18 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_EXTI15 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) #define CYGNUM_HAL_VSR_MIN 0 @@ -165,28 +162,36 @@ switch( __vector ) \ { \ case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI0; \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ break; \ \ case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ break; \ \ case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_PVD: \ + __v = 16; \ break; \ \ - case CYGNUM_HAL_INTERRUPT_EXTI16...CYGNUM_HAL_INTERRUPT_EXTI18: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + case CYGNUM_HAL_INTERRUPT_RTC_ALARM: \ + __v = 17; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_USB_WAKEUP: \ + __v = 18; \ break; \ } \ \ - if( __v > 0 ) \ + if( __v >= 0 ) \ { \ cyg_uint32 __imr; \ HAL_READ_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ __imr &= ~CYGHWR_HAL_STM32_EXTI_BIT(__v); \ - HAL_READ_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ } \ } @@ -197,38 +202,82 @@ switch( __vector ) \ { \ case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI0; \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ break; \ \ case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(CYGNUM_HAL_INTERRUPT_EXTI9_5-CYGNUM_HAL_INTERRUPT_EXTERNAL), \ CYGARC_REG_NVIC_IBIT(CYGNUM_HAL_INTERRUPT_EXTI9_5-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); \ break; \ \ case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(CYGNUM_HAL_INTERRUPT_EXTI15_10-CYGNUM_HAL_INTERRUPT_EXTERNAL), \ CYGARC_REG_NVIC_IBIT(CYGNUM_HAL_INTERRUPT_EXTI15_10-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); \ break; \ \ - case CYGNUM_HAL_INTERRUPT_EXTI16...CYGNUM_HAL_INTERRUPT_EXTI18: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + case CYGNUM_HAL_INTERRUPT_PVD: \ + __v = 16; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_RTC_ALARM: \ + __v = 17; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_USB_WAKEUP: \ + __v = 18; \ break; \ } \ \ - if( __v > 0 ) \ + if( __v >= 0 ) \ { \ cyg_uint32 __imr; \ HAL_READ_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ __imr |= CYGHWR_HAL_STM32_EXTI_BIT(__v); \ - HAL_READ_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ } \ } #define HAL_VAR_INTERRUPT_SET_LEVEL( __vector, __level ) CYG_EMPTY_STATEMENT -#define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector ) CYG_EMPTY_STATEMENT +#define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector ) \ +{ \ + cyg_int32 __v = -1; \ + \ + switch( __vector ) \ + { \ + case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_PVD: \ + __v = 16; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_RTC_ALARM: \ + __v = 17; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_USB_WAKEUP: \ + __v = 18; \ + break; \ + } \ + \ + if( __v >= 0 ) \ + { \ + cyg_uint32 __bit = CYGHWR_HAL_STM32_EXTI_BIT(__v); \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_PR, __bit ); \ + } \ +} #define HAL_VAR_INTERRUPT_CONFIGURE( __vector, __level, __up ) \ { \ @@ -237,33 +286,41 @@ switch( __vector ) \ { \ case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI0; \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ break; \ \ case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ break; \ \ case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_PVD: \ + __v = 16; \ break; \ \ - case CYGNUM_HAL_INTERRUPT_EXTI16...CYGNUM_HAL_INTERRUPT_EXTI18: \ - __v -= CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + case CYGNUM_HAL_INTERRUPT_RTC_ALARM: \ + __v = 17; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_USB_WAKEUP: \ + __v = 18; \ break; \ } \ \ - if( !(__level) ) \ + if(( __v >= 0 ) && !(__level) ) \ { \ cyg_uint32 __base = CYGHWR_HAL_STM32_EXTI; \ cyg_uint32 __rtsr, __ftsr; \ cyg_uint32 __bit = CYGHWR_HAL_STM32_EXTI_BIT(__v); \ HAL_READ_UINT32( __base+CYGHWR_HAL_STM32_EXTI_RTSR, __rtsr ); \ - HAL_READ_UINT32( __base+CYGHWR_HAL_STM32_EXTI_RTSR, __ftsr ); \ + HAL_READ_UINT32( __base+CYGHWR_HAL_STM32_EXTI_FTSR, __ftsr ); \ if( __up ) __rtsr |= __bit, __ftsr &= ~__bit; \ else __ftsr |= __bit, __rtsr &= ~__bit; \ HAL_WRITE_UINT32( __base+CYGHWR_HAL_STM32_EXTI_RTSR, __rtsr ); \ - HAL_WRITE_UINT32( __base+CYGHWR_HAL_STM32_EXTI_RTSR, __ftsr ); \ + HAL_WRITE_UINT32( __base+CYGHWR_HAL_STM32_EXTI_FTSR, __ftsr ); \ } \ }
--- a/packages/hal/cortexm/stm32/var/current/include/var_io.h +++ b/packages/hal/cortexm/stm32/var/current/include/var_io.h @@ -110,8 +110,8 @@ // Device signature and ID registers #define CYGHWR_HAL_STM32_DEV_SIG 0x1FFFF7E0 -#define CYGHWR_HAL_STM32_DEV_SIG_FSIZE(__s) (((__s)>>16)&0xFFFF) -#define CYGHWR_HAL_STM32_DEV_SIG_RSIZE(__s) ((__s)&0xFFFF) +#define CYGHWR_HAL_STM32_DEV_SIG_RSIZE(__s) (((__s)>>16)&0xFFFF) +#define CYGHWR_HAL_STM32_DEV_SIG_FSIZE(__s) ((__s)&0xFFFF) #define CYGHWR_HAL_STM32_MCU_ID 0xe0042000 #define CYGHWR_HAL_STM32_MCU_ID_DEV(__x) ((__x)&0xFFF) @@ -228,7 +228,8 @@ #define CYGHWR_HAL_STM32_RCC_APB1ENR_UART4 BIT_(19) #define CYGHWR_HAL_STM32_RCC_APB1ENR_UART5 BIT_(20) #define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C1 BIT_(21) -#define CYGHWR_HAL_STM32_RCC_APB1ENR_USB BIT_(22) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C2 BIT_(22) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_USB BIT_(23) #define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN BIT_(25) #define CYGHWR_HAL_STM32_RCC_APB1ENR_BKP BIT_(27) #define CYGHWR_HAL_STM32_RCC_APB1ENR_PWR BIT_(28) @@ -369,6 +370,127 @@ #define CYGHWR_HAL_STM32_GPIO_IN(__pin, __val ) hal_stm32_gpio_in( __pin, __val ) //============================================================================= +// Alternate I/O configuration registers. + +#define CYGHWR_HAL_STM32_AFIO_EVCR 0x00 +#define CYGHWR_HAL_STM32_AFIO_MAPR 0x04 +#define CYGHWR_HAL_STM32_AFIO_EXTICR1 0x08 +#define CYGHWR_HAL_STM32_AFIO_EXTICR2 0x0C +#define CYGHWR_HAL_STM32_AFIO_EXTICR3 0x10 +#define CYGHWR_HAL_STM32_AFIO_EXTICR4 0x14 + +// The following macro allows the four ETXICR registers to be indexed +// as CYGHWR_HAL_STM32_AFIO_EXTICR(1) to CYGHWR_HAL_STM32_AFIO_EXTICR(4) +#define CYGHWR_HAL_STM32_AFIO_EXTICR(__x) (4*((__x)-1)+0x08) + +#define CYGHWR_HAL_STM32_AFIO_EVCR_PIN(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTA VALUE_(4,0) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTB VALUE_(4,1) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTC VALUE_(4,2) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTD VALUE_(4,3) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTE VALUE_(4,4) +#define CYGHWR_HAL_STM32_AFIO_EVCR_EVOE BIT_(7) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_SPI1_RMP BIT_(0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_I2C1_RMP BIT_(1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT1_RMP BIT_(2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT2_RMP BIT_(3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_NO_RMP VALUE_(4,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_P1_RMP VALUE_(4,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_FL_RMP VALUE_(4,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_NO_RMP VALUE_(6,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_P1_RMP VALUE_(6,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_FL_RMP VALUE_(6,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_NO_RMP VALUE_(8,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P1_RMP VALUE_(8,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P2_RMP VALUE_(8,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_FL_RMP VALUE_(8,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_NO_RMP VALUE_(10,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_P2_RMP VALUE_(10,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_FL_RMP VALUE_(10,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM4_RMP BIT_(12) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_NO_RMP VALUE_(13,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL1_RMP VALUE_(13,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL2_RMP VALUE_(13,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_PD01_RMP BIT_(15) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM5CH4_RMP BIT_(16) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EINJ_RMP BIT_(17) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EREG_RMP BIT_(18) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EINJ_RMP BIT_(19) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EREG_RMP BIT_(20) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_FULL VALUE_(24,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_NORST VALUE_(24,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPEN VALUE_(24,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS VALUE_(24,4) + +// The following macros are used to generate the bitfields for setting up +// external interrupts. For example, CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(12) +// will generate the bitfield which when ORed into the EXTICR4 register will +// set up C12 as the external interrupt pin for the EXTI12 interrupt. +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTA(__x) VALUE_(4*((__x)&3),0) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTB(__x) VALUE_(4*((__x)&3),1) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(__x) VALUE_(4*((__x)&3),2) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTD(__x) VALUE_(4*((__x)&3),3) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTE(__x) VALUE_(4*((__x)&3),4) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTF(__x) VALUE_(4*((__x)&3),5) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTG(__x) VALUE_(4*((__x)&3),6) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_MASK(__x) VALUE_(4*((__x)&3),0xF) + +//============================================================================= +// DMA controller register definitions. + +#define CYGHWR_HAL_STM32_DMA_ISR 0x00 +#define CYGHWR_HAL_STM32_DMA_IFCR 0x04 + +// The following macros allow access to the per-channel DMA registers, indexed +// by channel number. Valid channel numbers are 1 to 7 for DMA1 and 1 to 5 +// for DMA2. +#define CYGHWR_HAL_STM32_DMA_CCR(__x) (0x14*(__x)-0x0C) +#define CYGHWR_HAL_STM32_DMA_CNDTR(__x) (0x14*(__x)-0x08) +#define CYGHWR_HAL_STM32_DMA_CPAR(__x) (0x14*(__x)-0x04) +#define CYGHWR_HAL_STM32_DMA_CMAR(__x) (0x14*(__x)) + +#define CYGHWR_HAL_STM32_DMA_ISR_GIF(__x) BIT_(4*(__x)-4) +#define CYGHWR_HAL_STM32_DMA_ISR_TCIF(__x) BIT_(4*(__x)-3) +#define CYGHWR_HAL_STM32_DMA_ISR_HTIF(__x) BIT_(4*(__x)-2) +#define CYGHWR_HAL_STM32_DMA_ISR_TEIF(__x) BIT_(4*(__x)-1) +#define CYGHWR_HAL_STM32_DMA_ISR_MASK(__x) VALUE_(4*(__x)-4,0xF) + +#define CYGHWR_HAL_STM32_DMA_IFCR_CGIF(__x) BIT_(4*(__x)-4) +#define CYGHWR_HAL_STM32_DMA_IFCR_CTCIF(__x) BIT_(4*(__x)-3) +#define CYGHWR_HAL_STM32_DMA_IFCR_CHTIF(__x) BIT_(4*(__x)-2) +#define CYGHWR_HAL_STM32_DMA_IFCR_CTEIF(__x) BIT_(4*(__x)-1) +#define CYGHWR_HAL_STM32_DMA_IFCR_MASK(__x) VALUE_(4*(__x)-4,0xF) + +#define CYGHWR_HAL_STM32_DMA_CCR_EN BIT_(0) +#define CYGHWR_HAL_STM32_DMA_CCR_TCIE BIT_(1) +#define CYGHWR_HAL_STM32_DMA_CCR_HTIE BIT_(2) +#define CYGHWR_HAL_STM32_DMA_CCR_TEIE BIT_(3) +#define CYGHWR_HAL_STM32_DMA_CCR_DIR BIT_(4) +#define CYGHWR_HAL_STM32_DMA_CCR_CIRC BIT_(5) +#define CYGHWR_HAL_STM32_DMA_CCR_PINC BIT_(6) +#define CYGHWR_HAL_STM32_DMA_CCR_MINC BIT_(7) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE8 VALUE_(8,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE16 VALUE_(8,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE32 VALUE_(8,2) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE8 VALUE_(10,0) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE16 VALUE_(10,1) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE32 VALUE_(10,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PLLOW VALUE_(12,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PLMEDIUM VALUE_(12,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PLHIGH VALUE_(12,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PLMAX VALUE_(12,3) +#define CYGHWR_HAL_STM32_DMA_CCR_MEM2MEM BIT_(14) + +//============================================================================= // UARTs #define CYGHWR_HAL_STM32_UART_SR 0x00 @@ -484,6 +606,157 @@ #endif //============================================================================= +// SPI interface register definitions. + +#define CYGHWR_HAL_STM32_SPI_CR1 0x00 +#define CYGHWR_HAL_STM32_SPI_CR2 0x04 +#define CYGHWR_HAL_STM32_SPI_SR 0x08 +#define CYGHWR_HAL_STM32_SPI_DR 0x0C +#define CYGHWR_HAL_STM32_SPI_CRCPR 0x10 +#define CYGHWR_HAL_STM32_SPI_RXCRCR 0x14 +#define CYGHWR_HAL_STM32_SPI_TXCRCR 0x18 +#define CYGHWR_HAL_STM32_SPI_I2SCFGR 0x1C +#define CYGHWR_HAL_STM32_SPI_I2SPR 0x20 + +#define CYGHWR_HAL_STM32_SPI_CR1_CPHA BIT_(0) +#define CYGHWR_HAL_STM32_SPI_CR1_CPOL BIT_(1) +#define CYGHWR_HAL_STM32_SPI_CR1_MSTR BIT_(2) +#define CYGHWR_HAL_STM32_SPI_CR1_BR(__x) VALUE_(3,(__x)) +#define CYGHWR_HAL_STM32_SPI_CR1_SPE BIT_(6) +#define CYGHWR_HAL_STM32_SPI_CR1_LSBFIRST BIT_(7) +#define CYGHWR_HAL_STM32_SPI_CR1_SSI BIT_(8) +#define CYGHWR_HAL_STM32_SPI_CR1_SSM BIT_(9) +#define CYGHWR_HAL_STM32_SPI_CR1_RXONLY BIT_(10) +#define CYGHWR_HAL_STM32_SPI_CR1_DFF BIT_(11) +#define CYGHWR_HAL_STM32_SPI_CR1_CRCNEXT BIT_(12) +#define CYGHWR_HAL_STM32_SPI_CR1_CRCEN BIT_(13) +#define CYGHWR_HAL_STM32_SPI_CR1_BIDIOE BIT_(14) +#define CYGHWR_HAL_STM32_SPI_CR1_BIDIMODE BIT_(15) + +#define CYGHWR_HAL_STM32_SPI_CR2_RXDMAEN BIT_(0) +#define CYGHWR_HAL_STM32_SPI_CR2_TXDMAEN BIT_(1) +#define CYGHWR_HAL_STM32_SPI_CR2_SSOE BIT_(2) +#define CYGHWR_HAL_STM32_SPI_CR2_ERRIE BIT_(5) +#define CYGHWR_HAL_STM32_SPI_CR2_RXNEIE BIT_(6) +#define CYGHWR_HAL_STM32_SPI_CR2_TXEIE BIT_(7) + +#define CYGHWR_HAL_STM32_SPI_SR_RXNE BIT_(0) +#define CYGHWR_HAL_STM32_SPI_SR_TXE BIT_(1) +#define CYGHWR_HAL_STM32_SPI_SR_CHSIDE BIT_(2) +#define CYGHWR_HAL_STM32_SPI_SR_UDR BIT_(3) +#define CYGHWR_HAL_STM32_SPI_SR_CRCERR BIT_(4) +#define CYGHWR_HAL_STM32_SPI_SR_MODF BIT_(5) +#define CYGHWR_HAL_STM32_SPI_SR_OVR BIT_(6) +#define CYGHWR_HAL_STM32_SPI_SR_BSY BIT_(7) + +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_CHLEN BIT_(0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN16 VALUE_(1,0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN24 VALUE_(1,1) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN32 VALUE_(1,2) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_CKPOL BIT_(3) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDPHL VALUE_(4,0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDMSB VALUE_(4,1) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDLSB VALUE_(4,2) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDPCM VALUE_(4,3) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_PCMSYNC BIT_(7) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGST VALUE_(8,0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGSR VALUE_(8,1) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGMT VALUE_(8,2) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGMR VALUE_(8,3) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SE BIT_(10) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2MOD BIT_(11) + +#define CYGHWR_HAL_STM32_SPI_I2SPR_I2SDIV(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_SPI_I2SPR_ODD BIT_(8) +#define CYGHWR_HAL_STM32_SPI_I2SPR_MCKOE BIT_(9) + +//============================================================================= +// USB interface register definitions. + +#define CYGHWR_HAL_STM32_USB_EP0R 0x00 +#define CYGHWR_HAL_STM32_USB_EP1R 0x04 +#define CYGHWR_HAL_STM32_USB_EP2R 0x08 +#define CYGHWR_HAL_STM32_USB_EP3R 0x0C +#define CYGHWR_HAL_STM32_USB_EP4R 0x10 +#define CYGHWR_HAL_STM32_USB_EP5R 0x14 +#define CYGHWR_HAL_STM32_USB_EP6R 0x18 +#define CYGHWR_HAL_STM32_USB_EP7R 0x1C + +#define CYGHWR_HAL_STM32_USB_CNTR 0x40 +#define CYGHWR_HAL_STM32_USB_ISTR 0x44 +#define CYGHWR_HAL_STM32_USB_FNR 0x48 +#define CYGHWR_HAL_STM32_USB_DADDR 0x4C +#define CYGHWR_HAL_STM32_USB_BTABLE 0x50 + +// The following macro allows the USB endpoint registers to be indexed as +// CYGHWR_HAL_STM32_USB_EPXR(0) to CYGHWR_HAL_STM32_USB_EPXR(7). +#define CYGHWR_HAL_STM32_USB_EPXR(__x) ((__x)*4) + +#define CYGHWR_HAL_STM32_USB_EPXR_EA(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_DIS VALUE_(4,0) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_STALL VALUE_(4,1) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_NAK VALUE_(4,2) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_VALID VALUE_(4,3) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_MASK VALUE_(4,3) +#define CYGHWR_HAL_STM32_USB_EPXR_DTOGTX BIT_(6) +#define CYGHWR_HAL_STM32_USB_EPXR_SWBUFRX BIT_(6) +#define CYGHWR_HAL_STM32_USB_EPXR_CTRTX BIT_(7) +#define CYGHWR_HAL_STM32_USB_EPXR_EPKIND BIT_(8) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_BULK VALUE_(9,0) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_CTRL VALUE_(9,1) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_ISO VALUE_(9,2) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_INTR VALUE_(9,3) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_MASK VALUE_(9,3) +#define CYGHWR_HAL_STM32_USB_EPXR_SETUP BIT_(11) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_DIS VALUE_(12,0) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_STALL VALUE_(12,1) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_NAK VALUE_(12,2) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_VALID VALUE_(12,3) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_MASK VALUE_(12,3) +#define CYGHWR_HAL_STM32_USB_EPXR_DTOGRX BIT_(14) +#define CYGHWR_HAL_STM32_USB_EPXR_SWBUFTX BIT_(14) +#define CYGHWR_HAL_STM32_USB_EPXR_CTRRX BIT_(15) + +#define CYGHWR_HAL_STM32_USB_CNTR_FRES BIT_(0) +#define CYGHWR_HAL_STM32_USB_CNTR_PDWN BIT_(1) +#define CYGHWR_HAL_STM32_USB_CNTR_LPMODE BIT_(2) +#define CYGHWR_HAL_STM32_USB_CNTR_FSUSP BIT_(3) +#define CYGHWR_HAL_STM32_USB_CNTR_RESUME BIT_(4) +#define CYGHWR_HAL_STM32_USB_CNTR_ESOFM BIT_(8) +#define CYGHWR_HAL_STM32_USB_CNTR_SOFM BIT_(9) +#define CYGHWR_HAL_STM32_USB_CNTR_RESETM BIT_(10) +#define CYGHWR_HAL_STM32_USB_CNTR_SUSPM BIT_(11) +#define CYGHWR_HAL_STM32_USB_CNTR_WKUPM BIT_(12) +#define CYGHWR_HAL_STM32_USB_CNTR_ERRM BIT_(13) +#define CYGHWR_HAL_STM32_USB_CNTR_PMAOVRM BIT_(14) +#define CYGHWR_HAL_STM32_USB_CNTR_CTRM BIT_(15) + +#define CYGHWR_HAL_STM32_USB_ISTR_EPID(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_USB_ISTR_EPID_MASK MASK_(0,4) +#define CYGHWR_HAL_STM32_USB_ISTR_DIR BIT_(4) +#define CYGHWR_HAL_STM32_USB_ISTR_ESOF BIT_(8) +#define CYGHWR_HAL_STM32_USB_ISTR_SOF BIT_(9) +#define CYGHWR_HAL_STM32_USB_ISTR_RESET BIT_(10) +#define CYGHWR_HAL_STM32_USB_ISTR_SUSP BIT_(11) +#define CYGHWR_HAL_STM32_USB_ISTR_WKUP BIT_(12) +#define CYGHWR_HAL_STM32_USB_ISTR_ERR BIT_(13) +#define CYGHWR_HAL_STM32_USB_ISTR_PMAOVR BIT_(14) +#define CYGHWR_HAL_STM32_USB_ISTR_CTR BIT_(15) + +#define CYGHWR_HAL_STM32_USB_FNR_FN_MASK MASK_(0,11) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF0 VALUE_(11,0) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF1 VALUE_(11,1) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF2 VALUE_(11,2) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOFN VALUE_(11,3) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_MASK MASK_(11,2) +#define CYGHWR_HAL_STM32_USB_FNR_LCK BIT_(13) +#define CYGHWR_HAL_STM32_USB_FNR_RXDM BIT_(14) +#define CYGHWR_HAL_STM32_USB_FNR_RXDP BIT_(15) + +#define CYGHWR_HAL_STM32_USB_DADDR_ADD(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_USB_DADDR_EF BIT_(7) + +//============================================================================= // Timers // // This currently only defines the basic registers and functionality
--- a/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c +++ b/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c @@ -282,6 +282,7 @@ cyg_uint32 hal_exti_isr( cyg_uint32 vect { cyg_uint32 odr; port = CYGHWR_HAL_STM32_GPIO_PORT( pin ); + bit = CYGHWR_HAL_STM32_GPIO_BIT(pin); HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_ODR, odr ); if( pin & CYGHWR_HAL_STM32_GPIO_PULLUP ) odr |= (1<<bit);