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1 /*================================================================= |
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2 // |
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3 // kcache2.c |
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4 // |
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5 // Cache feature/timing tests |
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6 // |
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7 //========================================================================== |
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8 //####COPYRIGHTBEGIN#### |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Cygnus eCos Public License |
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12 // Version 1.0 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://sourceware.cygnus.com/ecos |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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22 // September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Cygnus. Portions created |
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25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
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26 // ------------------------------------------- |
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27 // |
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28 //####COPYRIGHTEND#### |
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29 //========================================================================== |
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30 //#####DESCRIPTIONBEGIN#### |
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31 // |
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32 // Author(s): jskov, based on kcache1.c by dsm |
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33 // Contributors: jskov |
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34 // Date: 1998-12-10 |
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35 // Description: Tests some of the more exotic cache macros. |
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36 //####DESCRIPTIONEND#### |
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37 */ |
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38 |
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39 #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL |
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40 |
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41 #include <cyg/kernel/kapi.h> |
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42 |
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43 #include <cyg/infra/testcase.h> |
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44 |
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45 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK |
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46 #ifdef CYGFUN_KERNEL_API_C |
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47 |
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48 #include <cyg/infra/diag.h> |
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49 #include <cyg/hal/hal_cache.h> |
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50 |
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51 // ------------------------------------------------------------------------- |
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52 |
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53 #define NTHREADS 1 |
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54 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL |
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55 |
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56 // The following are defaults for loop variables. Note they will be overriden |
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57 // on simulator targets, where detected - there is no point testing a cache |
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58 // which doesn't exist :-). |
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59 |
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60 #define TEST_DZERO_LOOPS 5000 // default number of loops for test_dzero() |
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61 #define TIME_ILOCK_LOOPS 10000 // default number of loops for time_ilock() |
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62 #define TIME_DLOCK_LOOPS 10000 // default number of loops for time_dlock() |
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63 |
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64 |
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65 static cyg_handle_t thread[NTHREADS]; |
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66 |
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67 static cyg_thread thread_obj[NTHREADS]; |
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68 static char stack[NTHREADS][STACKSIZE]; |
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69 |
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70 #define MAXSIZE 1<<18 |
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71 |
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72 volatile char m[MAXSIZE]; |
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73 |
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74 // ------------------------------------------------------------------------- |
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75 // Test of data cache zero. |
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76 // o Timing comparison with instructions doing the same amount of work. |
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77 // o Check that area cleared with the DCACHE_ZERO macro contains zeros. |
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78 #ifdef HAL_DCACHE_ZERO |
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79 static void test_dzero(void) |
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80 { |
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81 register cyg_uint32 k, i; |
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82 cyg_tick_count_t count0, count1; |
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83 cyg_ucount32 t; |
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84 volatile cyg_uint32* aligned_p; |
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85 volatile cyg_uint32* p; |
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86 register CYG_INTERRUPT_STATE oldints; |
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87 cyg_ucount32 test_dzero_loops = TEST_DZERO_LOOPS; |
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88 |
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89 CYG_TEST_INFO("Data cache zero"); |
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90 |
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91 if (cyg_test_is_simulator) |
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92 test_dzero_loops=10; |
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93 |
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94 aligned_p = (volatile cyg_uint32*) |
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95 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) |
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96 & ~(HAL_DCACHE_LINE_SIZE-1)); |
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97 |
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98 // Time with conventional instructions. |
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99 HAL_DISABLE_INTERRUPTS(oldints); |
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100 HAL_DCACHE_SYNC(); |
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101 HAL_DCACHE_DISABLE(); |
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102 HAL_DCACHE_SYNC(); |
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103 HAL_DCACHE_INVALIDATE_ALL(); |
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104 HAL_DCACHE_ENABLE(); |
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105 HAL_RESTORE_INTERRUPTS(oldints); |
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106 count0 = cyg_current_time(); |
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107 for (k = 0; k < test_dzero_loops; k++) { |
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108 p = aligned_p; |
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109 for (i = 0; i < HAL_DCACHE_SETS; i++) { |
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110 #if (16 == HAL_DCACHE_LINE_SIZE) |
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111 *p++ = 0; |
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112 *p++ = 0; |
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113 *p++ = 0; |
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114 *p++ = 0; |
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115 #else |
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116 #error "Not defined for this cache line size." |
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117 #endif |
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118 } |
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119 |
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120 HAL_DISABLE_INTERRUPTS(oldints); |
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121 HAL_DCACHE_SYNC(); |
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122 HAL_DCACHE_DISABLE(); |
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123 HAL_DCACHE_SYNC(); |
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124 HAL_DCACHE_INVALIDATE_ALL(); |
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125 HAL_DCACHE_ENABLE(); |
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126 HAL_RESTORE_INTERRUPTS(oldints); |
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127 } |
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128 count1 = cyg_current_time(); |
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129 t = count1 - count0; |
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130 diag_printf("time with instructions: %d\n", t); |
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131 |
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132 // Initialize the area with non-zero so we can check whether |
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133 // the macro cleared the area properly. |
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134 p = aligned_p; |
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135 for (i = 0; |
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136 i < HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE/sizeof(cyg_uint32); |
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137 i++) { |
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138 *p++ = 0xdeadbeef; |
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139 } |
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140 |
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141 // Time with DCACHE_ZERO. |
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142 HAL_DISABLE_INTERRUPTS(oldints); |
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143 HAL_DCACHE_SYNC(); |
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144 HAL_DCACHE_DISABLE(); |
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145 HAL_DCACHE_SYNC(); |
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146 HAL_DCACHE_INVALIDATE_ALL(); |
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147 HAL_DCACHE_ENABLE(); |
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148 HAL_RESTORE_INTERRUPTS(oldints); |
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149 count0 = cyg_current_time(); |
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150 for (k = 0; k < test_dzero_loops; k++) { |
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151 HAL_DCACHE_ZERO(aligned_p, HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE); |
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152 |
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153 HAL_DISABLE_INTERRUPTS(oldints); |
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154 HAL_DCACHE_SYNC(); |
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155 HAL_DCACHE_DISABLE(); |
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156 HAL_DCACHE_SYNC(); |
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157 HAL_DCACHE_INVALIDATE_ALL(); |
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158 HAL_DCACHE_ENABLE(); |
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159 HAL_RESTORE_INTERRUPTS(oldints); |
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160 } |
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161 count1 = cyg_current_time(); |
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162 t = count1 - count0; |
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163 diag_printf("time with HAL_DCACHE_ZERO: %d\n", t); |
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164 |
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165 // Verify that the area was actually cleared. |
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166 { |
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167 cyg_uint32 d; |
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168 |
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169 d = 0; |
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170 p = aligned_p; |
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171 for (i = 0; |
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172 i < HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE/sizeof(cyg_uint32); |
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173 i++) { |
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174 d |= *p++; |
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175 } |
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176 |
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177 CYG_TEST_CHECK(0 == d, "region not properly cleared"); |
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178 } |
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179 |
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180 } |
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181 #endif |
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182 |
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183 // ------------------------------------------------------------------------- |
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184 // Test of data cache write hint. |
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185 // Just check that the macro compiles. |
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186 #ifdef HAL_DCACHE_WRITE_HINT |
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187 static void test_dwrite_hint(void) |
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188 { |
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189 register cyg_uint32 k; |
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190 register CYG_INTERRUPT_STATE oldints; |
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191 |
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192 CYG_TEST_INFO("Data cache write hint"); |
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193 |
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194 HAL_DISABLE_INTERRUPTS(oldints); |
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195 HAL_DCACHE_SYNC(); |
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196 HAL_DCACHE_DISABLE(); |
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197 HAL_DCACHE_SYNC(); |
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198 HAL_DCACHE_INVALIDATE_ALL(); |
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199 HAL_DCACHE_ENABLE(); |
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200 HAL_RESTORE_INTERRUPTS(oldints); |
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201 |
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202 HAL_DCACHE_WRITE_HINT(&m[HAL_DCACHE_LINE_SIZE*2], 2*HAL_DCACHE_LINE_SIZE); |
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203 for (k = 0; k < 20; k++); |
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204 m[HAL_DCACHE_LINE_SIZE*2] = 42; |
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205 } |
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206 #endif |
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207 |
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208 // ------------------------------------------------------------------------- |
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209 // Test of data cache read hint. |
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210 // Just check that the macro compiles. |
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211 #ifdef HAL_DCACHE_READ_HINT |
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212 static void test_dread_hint(void) |
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213 { |
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214 register char c; |
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215 register cyg_uint32 k; |
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216 register CYG_INTERRUPT_STATE oldints; |
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217 |
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218 CYG_TEST_INFO("Data cache read hint"); |
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219 |
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220 HAL_DISABLE_INTERRUPTS(oldints); |
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221 HAL_DCACHE_SYNC(); |
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222 HAL_DCACHE_DISABLE(); |
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223 HAL_DCACHE_SYNC(); |
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224 HAL_DCACHE_INVALIDATE_ALL(); |
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225 HAL_DCACHE_ENABLE(); |
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226 HAL_RESTORE_INTERRUPTS(oldints); |
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227 |
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228 HAL_DCACHE_READ_HINT(&m[HAL_DCACHE_LINE_SIZE*2], 2*HAL_DCACHE_LINE_SIZE); |
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229 for (k = 0; k < 20; k++); |
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230 c = m[HAL_DCACHE_LINE_SIZE*2]; |
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231 } |
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232 #endif |
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233 |
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234 // ------------------------------------------------------------------------- |
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235 // Test of data cache line store. |
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236 // Just check that the macro compiles. |
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237 #ifdef HAL_DCACHE_STORE |
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238 static void test_dstore(void) |
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239 { |
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240 volatile cyg_uint8* aligned_p; |
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241 cyg_int32 i; |
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242 register CYG_INTERRUPT_STATE oldints; |
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243 |
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244 CYG_TEST_INFO("Data cache store region"); |
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245 |
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246 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++) |
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247 m[i] = 0; |
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248 |
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249 HAL_DISABLE_INTERRUPTS(oldints); |
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250 HAL_DCACHE_SYNC(); |
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251 HAL_DCACHE_DISABLE(); |
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252 HAL_DCACHE_SYNC(); |
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253 HAL_DCACHE_INVALIDATE_ALL(); |
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254 HAL_DCACHE_ENABLE(); |
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255 HAL_RESTORE_INTERRUPTS(oldints); |
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256 |
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257 aligned_p = (volatile cyg_uint8*) |
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258 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) |
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259 & ~(HAL_DCACHE_LINE_SIZE-1)); |
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260 |
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261 aligned_p[0] = 42; |
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262 |
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263 HAL_DCACHE_STORE(aligned_p, HAL_DCACHE_LINE_SIZE); |
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264 } |
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265 #endif |
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266 |
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267 // ------------------------------------------------------------------------- |
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268 // Test of data cache line flush. |
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269 // o Requires write-back cache. |
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270 // o Check that flushed data is written to memory. |
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271 // o Simple range check of macro. |
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272 #ifdef HAL_DCACHE_FLUSH |
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273 static void test_dflush(void) |
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274 { |
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275 volatile cyg_uint8* aligned_p; |
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276 cyg_int32 i; |
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277 register CYG_INTERRUPT_STATE oldints; |
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278 |
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279 CYG_TEST_INFO("Data cache flush region"); |
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280 |
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281 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++) |
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282 m[i] = 0; |
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283 |
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284 HAL_DISABLE_INTERRUPTS(oldints); |
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285 HAL_DCACHE_SYNC(); |
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286 HAL_DCACHE_DISABLE(); |
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287 HAL_DCACHE_SYNC(); |
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288 HAL_DCACHE_INVALIDATE_ALL(); |
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289 HAL_DCACHE_ENABLE(); |
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290 HAL_RESTORE_INTERRUPTS(oldints); |
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291 |
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292 aligned_p = (volatile cyg_uint8*) |
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293 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) |
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294 & ~(HAL_DCACHE_LINE_SIZE-1)); |
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295 |
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296 aligned_p[0] = 42; |
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297 aligned_p[HAL_DCACHE_LINE_SIZE] = 43; |
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298 |
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299 HAL_DCACHE_FLUSH(aligned_p, HAL_DCACHE_LINE_SIZE); |
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300 |
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301 HAL_DCACHE_DISABLE(); |
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302 |
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303 CYG_TEST_CHECK(42 == aligned_p[0], |
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304 "memory didn't contain flushed data"); |
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305 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE], |
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306 "flushed beyond region"); |
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307 |
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308 HAL_DCACHE_ENABLE(); |
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309 |
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310 } |
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311 #endif |
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312 |
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313 // ------------------------------------------------------------------------- |
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314 // Test of data cache line invalidate. |
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315 // o Requires write-back cache. |
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316 // o Check that invalidated data is not written to memory and is invalidated |
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317 // in the cache. |
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318 // o Simple range check of macro. |
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319 #ifdef HAL_DCACHE_INVALIDATE |
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320 static void test_dinvalidate(void) |
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321 { |
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322 volatile cyg_uint8* aligned_p; |
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323 cyg_int32 i; |
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324 register CYG_INTERRUPT_STATE oldints; |
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325 |
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326 CYG_TEST_INFO("Data cache invalidate region"); |
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327 |
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328 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++) |
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329 m[i] = 0; |
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330 |
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331 HAL_DISABLE_INTERRUPTS(oldints); |
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332 HAL_DCACHE_SYNC(); |
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333 HAL_DCACHE_DISABLE(); |
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334 HAL_DCACHE_SYNC(); |
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335 HAL_DCACHE_INVALIDATE_ALL(); |
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336 HAL_DCACHE_ENABLE(); |
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337 HAL_RESTORE_INTERRUPTS(oldints); |
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338 |
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339 aligned_p = (volatile cyg_uint8*) |
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340 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) |
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341 & ~(HAL_DCACHE_LINE_SIZE-1)); |
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342 |
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343 aligned_p[0] = 43; |
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344 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43; |
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345 |
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346 aligned_p[HAL_DCACHE_LINE_SIZE] = 42; |
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347 |
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348 HAL_DCACHE_INVALIDATE(aligned_p, HAL_DCACHE_LINE_SIZE); |
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349 |
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350 CYG_TEST_CHECK(0 == aligned_p[0] && |
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351 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1], |
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352 "cache/memory contained invalidated data"); |
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353 CYG_TEST_CHECK(42 == aligned_p[HAL_DCACHE_LINE_SIZE], |
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354 "invalidated beyond range"); |
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355 } |
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356 #endif |
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357 |
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358 // ------------------------------------------------------------------------- |
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359 // Test of instruction cache locking. |
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360 // o Time difference between repeatedly executing a bunch of instructions |
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361 // with and without locking. |
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362 #ifdef HAL_ICACHE_LOCK |
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363 static void iloop(unsigned long* start, unsigned long* end) |
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364 { |
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365 register char c; |
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366 register CYG_INTERRUPT_STATE oldints; |
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367 |
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368 label_start: |
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369 // Invalidating shouldn't affect locked lines. |
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370 HAL_DISABLE_INTERRUPTS(oldints); |
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371 HAL_ICACHE_DISABLE(); |
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372 HAL_ICACHE_INVALIDATE_ALL(); |
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373 HAL_ICACHE_ENABLE(); |
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374 HAL_RESTORE_INTERRUPTS(oldints); |
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375 |
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376 c = m[HAL_DCACHE_LINE_SIZE*0]; |
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377 c = m[HAL_DCACHE_LINE_SIZE*1]; |
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378 c = m[HAL_DCACHE_LINE_SIZE*2]; |
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379 c = m[HAL_DCACHE_LINE_SIZE*3]; |
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380 c = m[HAL_DCACHE_LINE_SIZE*4]; |
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381 c = m[HAL_DCACHE_LINE_SIZE*5]; |
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382 c = m[HAL_DCACHE_LINE_SIZE*6]; |
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383 c = m[HAL_DCACHE_LINE_SIZE*7]; |
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384 c = m[HAL_DCACHE_LINE_SIZE*8]; |
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385 c = m[HAL_DCACHE_LINE_SIZE*9]; |
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386 c = m[HAL_DCACHE_LINE_SIZE*10]; |
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387 c = m[HAL_DCACHE_LINE_SIZE*11]; |
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388 c = m[HAL_DCACHE_LINE_SIZE*12]; |
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389 c = m[HAL_DCACHE_LINE_SIZE*13]; |
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390 c = m[HAL_DCACHE_LINE_SIZE*14]; |
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391 c = m[HAL_DCACHE_LINE_SIZE*15]; |
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392 c = m[HAL_DCACHE_LINE_SIZE*16]; |
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393 c = m[HAL_DCACHE_LINE_SIZE*17]; |
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394 c = m[HAL_DCACHE_LINE_SIZE*18]; |
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395 c = m[HAL_DCACHE_LINE_SIZE*19]; |
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396 c = m[HAL_DCACHE_LINE_SIZE*20]; |
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397 c = m[HAL_DCACHE_LINE_SIZE*21]; |
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398 c = m[HAL_DCACHE_LINE_SIZE*22]; |
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399 c = m[HAL_DCACHE_LINE_SIZE*23]; |
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400 c = m[HAL_DCACHE_LINE_SIZE*24]; |
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401 c = m[HAL_DCACHE_LINE_SIZE*25]; |
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402 c = m[HAL_DCACHE_LINE_SIZE*26]; |
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403 c = m[HAL_DCACHE_LINE_SIZE*27]; |
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404 c = m[HAL_DCACHE_LINE_SIZE*28]; |
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405 c = m[HAL_DCACHE_LINE_SIZE*29]; |
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406 c = m[HAL_DCACHE_LINE_SIZE*30]; |
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407 c = m[HAL_DCACHE_LINE_SIZE*31]; |
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408 c = m[HAL_DCACHE_LINE_SIZE*32]; |
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409 c = m[HAL_DCACHE_LINE_SIZE*33]; |
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410 c = m[HAL_DCACHE_LINE_SIZE*34]; |
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411 c = m[HAL_DCACHE_LINE_SIZE*35]; |
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412 c = m[HAL_DCACHE_LINE_SIZE*36]; |
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413 c = m[HAL_DCACHE_LINE_SIZE*37]; |
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414 c = m[HAL_DCACHE_LINE_SIZE*38]; |
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415 c = m[HAL_DCACHE_LINE_SIZE*39]; |
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416 c = m[HAL_DCACHE_LINE_SIZE*40]; |
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417 c = m[HAL_DCACHE_LINE_SIZE*41]; |
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418 c = m[HAL_DCACHE_LINE_SIZE*42]; |
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419 c = m[HAL_DCACHE_LINE_SIZE*43]; |
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420 c = m[HAL_DCACHE_LINE_SIZE*44]; |
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421 c = m[HAL_DCACHE_LINE_SIZE*45]; |
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422 c = m[HAL_DCACHE_LINE_SIZE*46]; |
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423 c = m[HAL_DCACHE_LINE_SIZE*47]; |
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424 c = m[HAL_DCACHE_LINE_SIZE*48]; |
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425 c = m[HAL_DCACHE_LINE_SIZE*49]; |
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426 c = m[HAL_DCACHE_LINE_SIZE*50]; |
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427 c = m[HAL_DCACHE_LINE_SIZE*51]; |
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428 c = m[HAL_DCACHE_LINE_SIZE*52]; |
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429 c = m[HAL_DCACHE_LINE_SIZE*53]; |
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430 c = m[HAL_DCACHE_LINE_SIZE*54]; |
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431 c = m[HAL_DCACHE_LINE_SIZE*55]; |
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432 c = m[HAL_DCACHE_LINE_SIZE*56]; |
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433 c = m[HAL_DCACHE_LINE_SIZE*57]; |
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434 c = m[HAL_DCACHE_LINE_SIZE*58]; |
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435 c = m[HAL_DCACHE_LINE_SIZE*59]; |
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436 c = m[HAL_DCACHE_LINE_SIZE*60]; |
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437 c = m[HAL_DCACHE_LINE_SIZE*61]; |
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438 c = m[HAL_DCACHE_LINE_SIZE*62]; |
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439 c = m[HAL_DCACHE_LINE_SIZE*63]; |
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440 |
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441 label_end: |
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442 |
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443 *start = (unsigned long) &&label_start; |
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444 *end = (unsigned long) &&label_end; |
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445 } |
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446 |
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447 static void time_ilock(void) |
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448 { |
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449 register cyg_ucount32 k; |
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450 cyg_tick_count_t count0, count1; |
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451 cyg_ucount32 t; |
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452 unsigned long start, end; |
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453 register cyg_ucount32 time_ilock_loops = TIME_ILOCK_LOOPS; |
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454 |
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455 CYG_TEST_INFO("Instruction cache lock"); |
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456 |
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457 if (cyg_test_is_simulator) |
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458 time_ilock_loops = 10; |
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459 |
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460 count0 = cyg_current_time(); |
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461 for (k = 0; k < time_ilock_loops; k++) { |
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462 iloop(&start, &end); |
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463 } |
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464 count1 = cyg_current_time(); |
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465 t = count1 - count0; |
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466 diag_printf("time without lock: %d\n", t); |
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467 |
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468 HAL_ICACHE_LOCK(start, end-start); |
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469 |
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470 count0 = cyg_current_time(); |
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471 for (k = 0; k < time_ilock_loops; k++) { |
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472 iloop(&start, &end); |
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473 } |
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474 count1 = cyg_current_time(); |
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475 t = count1 - count0; |
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476 diag_printf("time with lock: %d\n", t); |
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477 |
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478 HAL_ICACHE_UNLOCK(start, end-start); |
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479 } |
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480 #endif // ifdef HAL_ICACHE_LOCK |
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481 |
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482 // ------------------------------------------------------------------------- |
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483 // Test of data cache locking. |
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484 // o Time difference between repeatedly accessing a memory region |
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485 // with and without locking. |
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486 #ifdef HAL_DCACHE_LOCK |
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487 static void dloop(void) |
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488 { |
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489 register cyg_uint32 j; |
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490 register char c; |
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491 register CYG_INTERRUPT_STATE oldints; |
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492 |
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493 HAL_DISABLE_INTERRUPTS(oldints); |
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494 HAL_DCACHE_SYNC(); |
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495 HAL_DCACHE_DISABLE(); |
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496 HAL_DCACHE_SYNC(); |
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497 HAL_DCACHE_INVALIDATE_ALL(); |
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498 HAL_DCACHE_ENABLE(); |
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499 HAL_RESTORE_INTERRUPTS(oldints); |
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500 for (j = 0; j < HAL_DCACHE_SETS; j++) { |
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501 c = m[HAL_DCACHE_LINE_SIZE*j]; |
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502 } |
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503 } |
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504 |
|
|
505 static void time_dlock(void) |
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506 { |
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507 register cyg_ucount32 k; |
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508 cyg_tick_count_t count0, count1; |
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509 cyg_ucount32 t; |
|
|
510 register cyg_ucount32 time_dlock_loops = TIME_DLOCK_LOOPS; |
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|
511 |
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512 CYG_TEST_INFO("Data cache lock"); |
|
|
513 |
|
|
514 if (cyg_test_is_simulator) |
|
|
515 time_dlock_loops = 10; |
|
|
516 |
|
|
517 count0 = cyg_current_time(); |
|
|
518 for (k = 0; k < time_dlock_loops; k++) { |
|
|
519 dloop(); |
|
|
520 } |
|
|
521 count1 = cyg_current_time(); |
|
|
522 t = count1 - count0; |
|
|
523 diag_printf("time without lock: %d\n", t); |
|
|
524 |
|
|
525 HAL_DCACHE_LOCK(&m[0], HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE); |
|
|
526 |
|
|
527 count0 = cyg_current_time(); |
|
|
528 for (k = 0; k < time_dlock_loops; k++) { |
|
|
529 dloop(); |
|
|
530 } |
|
|
531 count1 = cyg_current_time(); |
|
|
532 t = count1 - count0; |
|
|
533 diag_printf("time with lock: %d\n", t); |
|
|
534 |
|
|
535 HAL_DCACHE_UNLOCK(&m[0], HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE); |
|
|
536 } |
|
|
537 #endif // ifdef HAL_DCACHE_LOCK |
|
|
538 |
|
|
539 // ------------------------------------------------------------------------- |
|
|
540 static void entry0( cyg_addrword_t data ) |
|
|
541 { |
|
|
542 #ifdef HAL_DCACHE_LOCK |
|
|
543 time_dlock(); |
|
|
544 #endif |
|
|
545 #ifdef HAL_ICACHE_LOCK |
|
|
546 time_ilock(); |
|
|
547 #endif |
|
|
548 #ifdef HAL_DCACHE_STORE |
|
|
549 test_dstore(); |
|
|
550 #endif |
|
|
551 #ifdef HAL_DCACHE_READ_HINT |
|
|
552 test_dread_hint(); |
|
|
553 #endif |
|
|
554 #ifdef HAL_DCACHE_WRITE_HINT |
|
|
555 test_dwrite_hint(); |
|
|
556 #endif |
|
|
557 #ifdef HAL_DCACHE_ZERO |
|
|
558 test_dzero(); |
|
|
559 #endif |
|
|
560 |
|
|
561 // The below tests only work on a copy-back cache. |
|
|
562 if (0) { |
|
|
563 #ifdef HAL_DCACHE_FLUSH |
|
|
564 test_dflush(); |
|
|
565 #endif |
|
|
566 #ifdef HAL_DCACHE_INVALIDATE |
|
|
567 test_dinvalidate(); |
|
|
568 #endif |
|
|
569 } |
|
|
570 |
|
|
571 CYG_TEST_PASS_FINISH("End of test"); |
|
|
572 } |
|
|
573 |
|
|
574 // ------------------------------------------------------------------------- |
|
|
575 |
|
|
576 void kcache2_main( void ) |
|
|
577 { |
|
|
578 CYG_TEST_INIT(); |
|
|
579 |
|
|
580 cyg_thread_create(4, entry0 , (cyg_addrword_t)0, "kcache2", |
|
|
581 (void *)stack[0], STACKSIZE, &thread[0], &thread_obj[0]); |
|
|
582 cyg_thread_resume(thread[0]); |
|
|
583 |
|
|
584 cyg_scheduler_start(); |
|
|
585 } |
|
|
586 |
|
|
587 // ------------------------------------------------------------------------- |
|
|
588 |
|
|
589 externC void |
|
|
590 cyg_start( void ) |
|
|
591 { |
|
|
592 kcache2_main(); |
|
|
593 } |
|
|
594 |
|
|
595 // ------------------------------------------------------------------------- |
|
|
596 |
|
|
597 #else // def CYGFUN_KERNEL_API_C |
|
|
598 #define N_A_MSG "Kernel C API layer disabled" |
|
|
599 #endif // def CYGFUN_KERNEL_API_C |
|
|
600 #else // def CYGVAR_KERNEL_COUNTERS_CLOCK |
|
|
601 #define N_A_MSG "Kernel real-time clock disabled" |
|
|
602 #endif // def CYGVAR_KERNEL_COUNTERS_CLOCK |
|
|
603 |
|
|
604 #ifdef N_A_MSG |
|
|
605 externC void |
|
|
606 cyg_start( void ) |
|
|
607 { |
|
|
608 CYG_TEST_INIT(); |
|
|
609 CYG_TEST_NA( N_A_MSG ); |
|
|
610 } |
|
|
611 #endif // N_A_MSG |
|
|
612 |
|
|
613 // ------------------------------------------------------------------------- |
|
|
614 /* EOF kcache2.c */ |
