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annotate packages/hal/arm/iq80310/current/include/hal_platform_ints.h @ 159:511f4dc167f6

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Merge from eCos master repository on 2001-05-18-01:30:05-BST
author jlarmour
date Fri, 18 May 2001 06:32:28 +0000
parents f935b880e96c
children e0c0827131d1
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1 #ifndef CYGONCE_HAL_PLATFORM_INTS_H
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2 #define CYGONCE_HAL_PLATFORM_INTS_H
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3 //==========================================================================
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4 //
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5 // hal_platform_ints.h
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6 //
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7 // HAL Interrupt and clock support
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8 //
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9 //==========================================================================
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10 //####COPYRIGHTBEGIN####
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11 //
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12 // -------------------------------------------
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13 // The contents of this file are subject to the Red Hat eCos Public License
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14 // Version 1.1 (the "License"); you may not use this file except in
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15 // compliance with the License. You may obtain a copy of the License at
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16 // http://www.redhat.com/
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17 //
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18 // Software distributed under the License is distributed on an "AS IS"
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19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 // License for the specific language governing rights and limitations under
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21 // the License.
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22 //
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23 // The Original Code is eCos - Embedded Configurable Operating System,
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24 // released September 30, 1998.
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25 //
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26 // The Initial Developer of the Original Code is Red Hat.
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27 // Portions created by Red Hat are
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28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 // All Rights Reserved.
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30 // -------------------------------------------
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31 //
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32 //####COPYRIGHTEND####
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33 //==========================================================================
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34 //#####DESCRIPTIONBEGIN####
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35 //
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36 // Author(s): msalter
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37 // Contributors:
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38 // Date: 2000-10-10
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39 // Purpose: Define Interrupt support
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40 // Description: The interrupt details for the IQ80310 are defined here.
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41 // Usage:
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42 // #include <cyg/hal/hal_platform_ints.h>
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43 // ...
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44 //
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //==========================================================================
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49
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50 // *** 80200 CPU ***
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51 #define CYGNUM_HAL_INTERRUPT_reserved0 0
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52 #define CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL 1 // See Ch.12 - Performance Mon.
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53 #define CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL 2 // PMU counter 0/1 overflow
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54 #define CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL 3 // PMU clock overflow
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55 #define CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT 4 // See Ch.11 - Bus Control Unit
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56 #define CYGNUM_HAL_INTERRUPT_NIRQ 5 // external IRQ
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57 #define CYGNUM_HAL_INTERRUPT_NFIQ 6 // external FIQ
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58
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59 // *** XINT6 interrupts ***
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60 #define CYGNUM_HAL_INTERRUPT_DMA_0 7
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61 #define CYGNUM_HAL_INTERRUPT_DMA_1 8
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62 #define CYGNUM_HAL_INTERRUPT_DMA_2 9
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63 #define CYGNUM_HAL_INTERRUPT_GTSC 10 // Global Time Stamp Counter
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64 #define CYGNUM_HAL_INTERRUPT_PEC 11 // Performance Event Counter
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65 #define CYGNUM_HAL_INTERRUPT_AAIP 12 // application accelerator unit
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66
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67 // *** XINT7 interrupts ***
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68 // I2C interrupts
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69 #define CYGNUM_HAL_INTERRUPT_I2C_TX_EMPTY 13
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70 #define CYGNUM_HAL_INTERRUPT_I2C_RX_FULL 14
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71 #define CYGNUM_HAL_INTERRUPT_I2C_BUS_ERR 15
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72 #define CYGNUM_HAL_INTERRUPT_I2C_STOP 16
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73 #define CYGNUM_HAL_INTERRUPT_I2C_LOSS 17
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74 #define CYGNUM_HAL_INTERRUPT_I2C_ADDRESS 18
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75 // Messaging Unit interrupts
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76 #define CYGNUM_HAL_INTERRUPT_MESSAGE_0 19
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77 #define CYGNUM_HAL_INTERRUPT_MESSAGE_1 20
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78 #define CYGNUM_HAL_INTERRUPT_DOORBELL 21
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79 #define CYGNUM_HAL_INTERRUPT_NMI_DOORBELL 22 // FIQ
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80 #define CYGNUM_HAL_INTERRUPT_QUEUE_POST 23
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81 #define CYGNUM_HAL_INTERRUPT_OUTBOUND_QUEUE_FULL 24 // FIQ
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82 #define CYGNUM_HAL_INTERRUPT_INDEX_REGISTER 25
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83 // PCI Address Translation Unit
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84 #define CYGNUM_HAL_INTERRUPT_BIST 26
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85
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86 // *** External board interrupts (XINT3) ***
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87 #define CYGNUM_HAL_INTERRUPT_TIMER 27 // external timer
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88 #define CYGNUM_HAL_INTERRUPT_ETHERNET 28 // onboard enet
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89 #define CYGNUM_HAL_INTERRUPT_SERIAL_A 29 // 16x50 uart A
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90 #define CYGNUM_HAL_INTERRUPT_SERIAL_B 30 // 16x50 uart B
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91 #define CYGNUM_HAL_INTERRUPT_PCI_S_INTD 31 // secondary PCI INTD
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92 // The hardware doesn't (yet?) provide masking or status for these
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93 // even though they can trigger cpu interrupts. ISRs will need to
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94 // poll the device to see if the device actually triggered the
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95 // interrupt.
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96 #define CYGNUM_HAL_INTERRUPT_PCI_S_INTC 32 // secondary PCI INTC
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97 #define CYGNUM_HAL_INTERRUPT_PCI_S_INTB 33 // secondary PCI INTB
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98 #define CYGNUM_HAL_INTERRUPT_PCI_S_INTA 34 // secondary PCI INTA
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99
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100 // *** NMI Interrupts go to FIQ ***
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101 #define CYGNUM_HAL_INTERRUPT_MCU_ERR 35
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102 #define CYGNUM_HAL_INTERRUPT_PATU_ERR 36
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103 #define CYGNUM_HAL_INTERRUPT_SATU_ERR 37
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104 #define CYGNUM_HAL_INTERRUPT_PBDG_ERR 38
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105 #define CYGNUM_HAL_INTERRUPT_SBDG_ERR 39
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106 #define CYGNUM_HAL_INTERRUPT_DMA0_ERR 40
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107 #define CYGNUM_HAL_INTERRUPT_DMA1_ERR 41
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108 #define CYGNUM_HAL_INTERRUPT_DMA2_ERR 42
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109 #define CYGNUM_HAL_INTERRUPT_MU_ERR 43
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110 #define CYGNUM_HAL_INTERRUPT_reserved52 44
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111 #define CYGNUM_HAL_INTERRUPT_AAU_ERR 45
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112 #define CYGNUM_HAL_INTERRUPT_BIU_ERR 46
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113
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114 // *** ATU FIQ sources ***
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115 #define CYGNUM_HAL_INTERRUPT_P_SERR 47
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116 #define CYGNUM_HAL_INTERRUPT_S_SERR 48
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117
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118 #define CYGNUM_HAL_ISR_MIN 0
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119 #define CYGNUM_HAL_ISR_MAX 48
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120
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121 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
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122
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123 // The vector used by the Real time clock
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124 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER
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125 //#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL
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126
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127 extern void hal_delay_us(cyg_uint32 usecs);
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128 #define HAL_DELAY_US(n) hal_delay_us(n);
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129
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130 //----------------------------------------------------------------------------
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131 // Reset.
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132 #include <cyg/hal/hal_iq80310.h> // registers
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133 #include <cyg/hal/hal_io.h> // IO macros
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134
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135 // FIXME - Can we reset the board?
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136 #define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT
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137
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138 #define HAL_PLATFORM_RESET_ENTRY 0x00000000
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139
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140 #endif // CYGONCE_HAL_PLATFORM_INTS_H