ecos: packages/hal/powerpc/arch/current/src/vectors.S annotate

annotate packages/hal/powerpc/arch/current/src/vectors.S @ 46:797268ecc331 ecos-sw-1999-10-19

Merge from eCos master repository on 1999-10-19-18:55:31-BST

author	jlarmour
date	Tue, 19 Oct 1999 19:19:52 +0000
parents	e7ba79f6d3a8
children	c38311975d4f

rev	line source
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	1 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 ##
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3 ## vectors.S
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 ##
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 ## PowerPC exception vectors
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	6 ##
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	7 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	8 #####COPYRIGHTBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 #
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 # -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	11 # The contents of this file are subject to the Cygnus eCos Public License
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	12 # Version 1.0 (the "License"); you may not use this file except in
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	13 # compliance with the License. You may obtain a copy of the License at
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	14 # http://sourceware.cygnus.com/ecos
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	15 #
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	16 # Software distributed under the License is distributed on an "AS IS"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	18 # License for the specific language governing rights and limitations under
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	19 # the License.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	20 #
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	21 # The Original Code is eCos - Embedded Cygnus Operating System, released
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	22 # September 30, 1998.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	23 #
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	24 # The Initial Developer of the Original Code is Cygnus. Portions created
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	25 # by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	26 # -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	27 #
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	28 #####COPYRIGHTEND####
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	29 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	30 #######DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	31 ##
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	32 ## Author(s): nickg, jskov
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	33 ## Contributors: nickg, jskov
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	34 ## Date: 1999-02-20
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	35 ## Purpose: PowerPC exception vectors
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	36 ## Description: This file defines the code placed into the exception
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	37 ## vectors. It also contains the first level default VSRs
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	38 ## that save and restore state for both exceptions and
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	39 ## interrupts.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	40 ##
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	41 ######DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	42 ##
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	43 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	44
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	45 #include <pkgconf/hal.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	46
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	47 #ifdef CYGPKG_KERNEL
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	48 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	49 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	50
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	51 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	52 #include "cyg/hal/ppc_regs.h"
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	53 #include "cyg/hal/ppc.inc"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	54
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	55 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	56
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	57 .file "vectors.S"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	58
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	59 .extern hal_interrupt_handlers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	60 .extern hal_interrupt_data
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	61 .extern hal_interrupt_objects
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	62
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	63 .extern cyg_instrument
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	64
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	65 .extern hal_hardware_init
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	66
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	67 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	68 # MSR initialization value
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	69 # zero all bits except:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	70 # FP = floating point available
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	71 # ME = machine check enabled
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	72 # IP = vectors at 0xFFFxxxxx (ROM startup only)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	73 # IR = instruction address translation
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	74 # DR = data address translation
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	75 # RI = recoverable interrupt
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	76
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	77 #define CYG_MSR_COMMON (MSR_FP \| MSR_ME \| MSR_IR \| MSR_DR \| MSR_RI)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	78 #if defined(CYG_HAL_STARTUP_ROM) \|\| defined(CYG_HAL_STARTUP_STUBS)
16 4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	79 # ifdef CYG_HAL_POWERPC_COPY_VECTORS
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	80 # define CYG_MSR CYG_MSR_COMMON
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	81 # else
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	82 # define CYG_MSR (CYG_MSR_COMMON \| MSR_IP)
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	83 # endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	84 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	85 #ifdef CYG_HAL_STARTUP_RAM
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	86 #define CYG_MSR CYG_MSR_COMMON
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	87 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	88 #ifdef CYG_HAL_POWERPC_SIM
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	89 # When building for SIM, don~t enable MMU -- it~s not needed since caches
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	90 # are disabled, and there is a runtime simulation overhead.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	91 #undef CYG_MSR
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	92 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR \| MSR_DR))
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	93 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	94
34 29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST jlarmour parents: 32 diff changeset	95 #define CYG_MSR_NO_INTS (CYG_MSR & ~MSR_ME)
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST jlarmour parents: 32 diff changeset	96
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	97 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	98 # If the following option is enabled, we only save registers up to R12.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	99 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	100 # not need to save them when calling C functions.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	101
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	102 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	103
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	104 #define MAX_SAVE_REG 12
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	105
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	106 #else
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	107
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	108 #define MAX_SAVE_REG 31
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	109
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	110 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	111
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	112 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	113 # Start by defining the exceptions vectors that must be placed at
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	114 # locations 0xFFF00000 and 0x00000000. The following code will normally
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	115 # be located at 0xFFF00000 in the ROM. It may optionally be copied out
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	116 # to 0x00000000 if we want to use the RAM vectors. For this reason this code
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	117 # MUST BE POSITION INDEPENDENT. In RAM loaded configurations, this code may
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	118 # be placed at 0x00000000 during loading.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	119
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	120 .section ".vectors","ax"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	121
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	122 #---------------------------------------------------------------------------
36 e97d78785e2d Merge from eCos master repository on 1999-09-12-15:40:34-BST jlarmour parents: 34 diff changeset	123 # Unused first vector. Jump to special handler, trapping null-pointer calls.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	124
36 e97d78785e2d Merge from eCos master repository on 1999-09-12-15:40:34-BST jlarmour parents: 34 diff changeset	125 rom_vectors:
e97d78785e2d Merge from eCos master repository on 1999-09-12-15:40:34-BST jlarmour parents: 34 diff changeset	126 .extern hal_null_call
e97d78785e2d Merge from eCos master repository on 1999-09-12-15:40:34-BST jlarmour parents: 34 diff changeset	127 b hal_null_call
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	128
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	129 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	130 # Reset vector.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	131
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	132 .p2align 8
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	133 .globl reset_vector
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	134
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	135 reset_vector:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	136 lwi r3,_start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	137 mtlr r3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	138 blr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	139
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	140 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	141 # Macro for generating an exception vector service routine
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	142
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	143 .macro exception_vector name
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	144 .p2align 8
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	145 .globl __exception_\name
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	146 __exception_\name:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	147 mtspr SPRG1,r3 # stash some work registers away
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	148 mtspr SPRG2,r4
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	149 mtspr SPRG3,r5
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	150 mfcr r4 # stash CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	151 li r5,__exception_\name@L # load low half of vector address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	152 srwi r5,r5,6 # shift right by 6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	153 lwi r3,hal_vsr_table # table base
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	154 lwzx r3,r3,r5 # address of vsr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	155 mflr r5 # save link register
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	156 mtlr r3 # put vsr address into it
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	157 li r3,__exception_\name@L # reload low half of vector address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	158 blr # go to common code
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	159 .endm
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	160
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	161 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	162 # Define the exception vectors.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	163
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	164 # These are the architecture defined vectors that
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	165 # are always present.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	166
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	167 exception_vector machine_check
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	168 exception_vector data_storage
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	169 exception_vector instruction_storage
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	170 exception_vector external
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	171 exception_vector alignment
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	172 #if defined(CYG_HAL_STARTUP_ROM) \|\| defined(CYG_HAL_STARTUP_STUBS) \
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	173 \|\| defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	174 exception_vector program
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	175 #else
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	176 # Provide a crude hook to the GDB exception handler in ROM.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	177 # This allows the testing infrastructure to rely on breakpoints
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	178 # to terminate tests, even when the tests are compiled without
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	179 # the GDB stub.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	180 # It is _not_ a generic solution to the problem; in particular it
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	181 # is not possible to continue after a breakpoint is hit.
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	182 #
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	183 # Note that for platforms where StubROM vectors are copied into RAM
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	184 # at 0x00000000, simply skipping the copy of vector 0x700 is a
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	185 # better solution. See CYGPRI_STUBROM_HAS_RAM_VECTORS below.
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	186
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	187 .p2align 8
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	188 .globl __exception_program
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	189 __exception_program:
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	190 bl _init_CPU # disable caches.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	191 lwi r3,0xfff00700 # address of trap handler
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	192 mtlr r3 # in ROM.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	193 blr # jump to it.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	194
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	195 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	196 exception_vector floatingpoint_unavailable
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	197 exception_vector decrementer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	198 exception_vector reserved_00a00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	199 exception_vector reserved_00b00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	200 exception_vector system_call
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	201 exception_vector trace
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	202 exception_vector floatingpoint_assist
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	203 exception_vector reserved_00f00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	204
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	205 # There are some additional vectors defined
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	206 # on various implementations.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	207
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	208 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	209 # MPC8xx vectors
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	210
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	211 exception_vector software_emu
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	212 exception_vector instruction_tlb_miss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	213 exception_vector data_tlb_miss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	214 exception_vector instruction_tlb_error
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	215 exception_vector data_tlb_error
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	216 exception_vector reserved_01500
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	217 exception_vector reserved_01600
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	218 exception_vector reserved_01700
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	219 exception_vector reserved_01800
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	220 exception_vector reserved_01900
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	221 exception_vector reserved_01A00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	222 exception_vector reserved_01B00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	223 exception_vector data_breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	224 exception_vector instruction_breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	225 exception_vector peripheral_breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	226 exception_vector NMI_port
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	227
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	228 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	229 rom_vectors_end:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	230
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	231 #===========================================================================
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	232 # Real startup code. We jump here from the various reset vectors to set up
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	233 # the world.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	234
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	235 .text
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	236 .globl _start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	237
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	238 _start:
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	239 # Initialize CPU
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	240 bl _init_CPU
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	241
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	242 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	243 # Disable special MPC8xx "development support" which
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	244 # suppresses trace exceptions. The CPU seems to hang, not
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	245 # executing from offset 0x1e00(?) as expected.
16 4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	246
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	247 lwi r3,0x00000007
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	248 mtspr ICTRL,r3
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	249
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	250 li r3,0
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	251 mtspr DER, r3
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	252 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	253
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	254 # Set up global offset table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	255 lwi r2,_GLOBAL_OFFSET_TABLE_
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	256
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	257 # set up time base register to zero
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	258 xor r3,r3,r3
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	259 mtspr TBL_W,r3
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	260 xor r4,r4,r4
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	261 mtspr TBU_W,r4
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	262
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	263 # Call platform specific hardware initialization
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	264 # This may include memory controller initialization. It is not
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	265 # safe to access RAM until after this point.
16 4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	266 bl hal_hardware_init # this is platform dependent
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	267
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	268 # set up stack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	269 lwi sp,__interrupt_stack
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	270 mtspr SPRG0,sp # save in sprg0 for later use
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	271
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	272 #if defined(CYG_HAL_STARTUP_ROM) \|\| defined(CYG_HAL_STARTUP_STUBS)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	273
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	274 # Copy data from ROM to ram
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	275 lwi r3,__rom_data_start # r3 = rom start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	276 lwi r4,__ram_data_start # r4 = ram start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	277 lwi r5,__ram_data_end # r5 = ram end
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	278
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	279 cmplw r4,r5 # skip if no data
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	280 beq 2f
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	281
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	282 1:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	283 lwz r0,0(r3) # get word from ROM
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	284 stw r0,0(r4) # store in RAM
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	285 addi r3,r3,4 # increment by 1 word
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	286 addi r4,r4,4 # increment by 1 word
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	287 cmplw r4,r5 # compare
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	288 blt 1b # loop if not yet done
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	289 2:
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	290 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	291
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	292
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	293 #ifdef CYG_HAL_POWERPC_COPY_VECTORS // only for StubRom-supported startup
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	294
32 5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST jlarmour parents: 20 diff changeset	295 #ifdef CYG_HAL_POWERPC_MBX
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST jlarmour parents: 20 diff changeset	296 # define CYGPRI_STUBROM_HAS_RAM_VECTORS
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST jlarmour parents: 20 diff changeset	297 #endif
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	298
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	299 #ifdef CYGPRI_STUBROM_HAS_RAM_VECTORS
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	300 # ifdef CYG_HAL_STARTUP_RAM
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	301 # ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	302 # define CYGPRI_SKIP_BREAKPOINT_VECTOR
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	303 # endif // no stubs
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	304 # endif // RAM startup
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	305 #endif // Stubrom vectors are in RAM
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	306
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	307 # Copy RAM exception vectors from ROM (or load place) to RAM
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	308 lwi r3,rom_vectors # r3 = rom start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	309 lwi r4,0 # r4 = ram start
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	310 #ifdef CYGPRI_SKIP_BREAKPOINT_VECTOR
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	311 lwi r5,__exception_program # r5 = end of first leg of copy
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	312 #else
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	313 lwi r5,rom_vectors_end # r5 = rom end
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	314 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	315
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	316 cmplw r3,r5 # skip if no vectors
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	317 beq 2f
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	318
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	319 1:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	320 lwz r0,0(r3) # get word from ROM
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	321 stw r0,0(r4) # store in RAM
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	322 addi r3,r3,4 # increment by 1 word
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	323 addi r4,r4,4 # increment by 1 word
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	324 cmplw r3,r5 # compare
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	325 blt 1b # loop if not yet done
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	326 2:
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	327 #ifdef CYGPRI_SKIP_BREAKPOINT_VECTOR
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	328 cmplwi r4,__exception_program@L
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	329 bne 3f # is it the breakpoint vector?
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	330 addi r4,r4,0x100 # if so, leave it well alone
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	331 addi r3,r3,0x100
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	332 lwi r5,rom_vectors_end # r5 = rom end
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	333 b 1b # and do the rest of the copy
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	334 3:
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 16 diff changeset	335 #endif // Skip copying the breakpoint vector
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	336 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	337
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	338 # clear BSS
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	339 .extern __bss_start
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	340 .extern __bss_end
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	341 lwi r3,__bss_start # r3 = start
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	342 lwi r4,__bss_end # r4 = end
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	343 li r0,0 # r0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	344 cmplw r3,r4 # skip if no bss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	345 beq 2f
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	346
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	347 1: stw r0,0(r3) # store zero
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	348 addi r3,r3,4 # increment by 1 word
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	349 cmplw r3,r4 # compare
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	350 blt 1b # loop if not yet done
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	351 2:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	352
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	353 # clear SBSS
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	354 .extern __sbss_start
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	355 .extern __sbss_end
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	356 lwi r3,__sbss_start # r3 = start
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	357 lwi r4,__sbss_end # r4 = end
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	358 cmplw r3,r4 # skip if no sbss
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	359 beq 2f
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	360
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	361 1: stw r0,0(r3) # store zero
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	362 addi r3,r3,4 # increment by 1 word
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	363 cmplw r3,r4 # compare
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	364 blt 1b # loop if not yet done
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	365 2:
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	366
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	367 # It is now safe to call C functions which may rely on initialized
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	368 # data.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	369
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	370 # Set up stack for calls to C code.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	371 subi sp,sp,12 # make space on stack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	372 li r0,0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	373 stw r0,0(sp) # clear back chain
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	374 stw r0,8(sp) # zero return pc
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	375 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	376
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	377 # Initialize MMU.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	378 .extern hal_MMU_init
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	379 bl hal_MMU_init
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	380
38 e7ba79f6d3a8 Merge from eCos master repository on 1999-09-23-20:10:25-BST jlarmour parents: 36 diff changeset	381 # Enable MMU so we can safely enable caches.
34 29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST jlarmour parents: 32 diff changeset	382 lwi r3,CYG_MSR_NO_INTS # interrupts enabled later
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	383 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	384 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	385 sync
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	386
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	387 # Enable caches
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	388 .extern hal_enable_caches
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	389 bl hal_enable_caches
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	390
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	391 # call c++ constructors
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	392 .extern cyg_hal_invoke_constructors
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	393 bl cyg_hal_invoke_constructors
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	394
20 5f5102441818 Merge from eCos master repository on 1999-07-02-23:17:07-BST jlarmour parents: 18 diff changeset	395 # set up platform specific interrupt environment
5f5102441818 Merge from eCos master repository on 1999-07-02-23:17:07-BST jlarmour parents: 18 diff changeset	396 .extern hal_IRQ_init
5f5102441818 Merge from eCos master repository on 1999-07-02-23:17:07-BST jlarmour parents: 18 diff changeset	397 bl hal_IRQ_init
5f5102441818 Merge from eCos master repository on 1999-07-02-23:17:07-BST jlarmour parents: 18 diff changeset	398
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	399 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	400 .extern initialize_stub
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	401 bl initialize_stub
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	402 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	403
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	404 .extern cyg_start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	405 bl cyg_start # call cyg_start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	406 9:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	407 b 9b # if we return, loop
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	408
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	409 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	410 # This code handles the common part of all exception handlers.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	411 # It saves the machine state onto the stack and then calls
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	412 # a "C" routine to do the rest of the work. This work may result
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	413 # in thread switches, and changes to the saved state. When we return
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	414 # here the saved state is restored and execution is continued.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	415
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	416 .text
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	417
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	418 .extern __default_exception_vsr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	419 __default_exception_vsr:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	420
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	421 # We come here with all register containing their
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	422 # pre-exception values except:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	423 # R3 = ls 16 bits of vector address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	424 # R4 = saved CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	425 # R5 = saved LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	426 # LR = VSR address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	427 # SPRG1 = old R3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	428 # SPRG2 = old R4
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	429 # SPRG3 = old R5
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	430 # SRR0 = old PC
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	431 # SRR1 = old MSR and the exception cause (the POW state is lost!)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	432
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	433 subi r1,r1,ppc_exception_decrement
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	434 # leave space for registers and
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	435 # a safety margin
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	436
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	437 # First, save away some registers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	438 stw r3,ppcreg_vector(r1) # stash vector
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	439 stw r4,ppcreg_cr(r1) # stash CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	440 stw r5,ppcreg_lr(r1) # stash LR
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	441
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	442 # Enable MMU.
34 29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST jlarmour parents: 32 diff changeset	443 lwi r3,CYG_MSR_NO_INTS
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	444 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	445 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	446 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	447
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	448 mfspr r3,SPRG1 # save original R3
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	449 stw r3,ppcreg_regs+3*4(r1)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	450 mfspr r4,SPRG2 # save original R4
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	451 stw r4,ppcreg_regs+4*4(r1)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	452 mfspr r5,SPRG3 # save original R5
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	453 stw r5,ppcreg_regs+5*4(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	454
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	455 stw r0,ppcreg_regs(r1) # save R0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	456 stw r2,ppcreg_regs+2*4(r1) # save R2
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	457
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	458 mr r3,r1 # recreate original R1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	459 addi r3,r3,ppc_exception_decrement
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	460 stw r3,ppcreg_regs+1*4(r1) # and save it in state
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	461
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	462 # Save registers r6..r12/r31
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	463 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	464 .rept MAX_SAVE_REG+1-6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	465 stw _reg,(ppcreg_regs+_reg*4)(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	466 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	467 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	468
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	469 # Save registers used in vsr (r14+r15)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	470 stw r14,(ppcreg_regs+14*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	471 stw r15,(ppcreg_regs+15*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	472
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	473 # get remaining CPU registers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	474 mfxer r3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	475 mfctr r5
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	476 mfdar r6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	477 mfdsisr r7
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	478 mfpvr r8
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	479 mfsrr0 r9
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	480 mfsrr1 r10
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	481
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	482 # and store them
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	483 stw r3,ppcreg_xer(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	484 stw r5,ppcreg_ctr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	485 stw r6,ppcreg_dar(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	486 stw r7,ppcreg_dsisr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	487 stw r8,ppcreg_pvr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	488 stw r9,ppcreg_pc(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	489 stw r10,ppcreg_msr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	490
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	491 # The entire CPU state is now stashed on the stack,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	492 # call into C to do something with it.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	493
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	494 mr r3,sp # R3 = register dump
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	495
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	496 subi sp,sp,ppc_stack_frame_size # make a null frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	497
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	498 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	499 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	500 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	501
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	502 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	503 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	504
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	505 lwi r5,restore_state # get return link
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	506 mtlr r5 # to link register
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	507
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	508 .extern cyg_hal_exception_handler
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	509 b cyg_hal_exception_handler # call C code, r3 = registers
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	510
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	511 # When the call returns it will go to restore_state below.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	512
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	513
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	514 ##--------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	515 ## The following macros are defined depending on whether the Interrupt
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	516 ## system is using isr tables or chaining, and depending on the interrupt
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	517 ## controller in the system.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	518
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	519 ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	520
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	521 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	522
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	523 ## First level decoding of MPC8xx SIU interrupt controller.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	524
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	525 #define CYG_ISR_TABLE_SIZE 59
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	526
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	527 # decode the interrupt
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	528 .macro decode_interrupt dreg,state
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	529 lwz \dreg,ppcreg_vector(\state) # retrieve vector number,
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	530 rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	531 beq 0f # done if decrementer (vec 0)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	532 lwi \dreg,CYGARC_REG_IMM_SIVEC # if external, get SIU
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	533 lbz \dreg,0(\dreg) # vector.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	534 srwi \dreg,\dreg,2
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	535 addi \dreg,\dreg,1 # Skip decrementer vector
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	536 0: stw \dreg,ppcreg_vector(\state) # update vector in state frame.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	537 slwi \dreg,\dreg,2 # convert to byte offset.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	538 .endm
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	539
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	540 #else
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	541
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	542 ## This is the simple version. No interrupt controller, ppcreg_vector
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	543 ## is updated with the decoded interrupt vector. Isr tables/chaining
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	544 ## use same interrupt decoder.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	545 ## Bit 21 biffers between decrementer (0) and external (1).
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	546
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	547 #define CYG_ISR_TABLE_SIZE 2
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	548
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	549 # decode the interrupt
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	550 .macro decode_interrupt dreg,state
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	551 lwz \dreg,ppcreg_vector(\state) # retrieve vector number,
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	552 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	553 stw \dreg,ppcreg_vector(\state) # vector in state frame.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	554 slwi \dreg,\dreg,2 # convert to word offset.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	555 .endm
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	556
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	557 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	558
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	559 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	560 # Common interrupt handling code.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	561
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	562 .extern __default_interrupt_vsr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	563 __default_interrupt_vsr:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	564
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	565 # We come here with all register containing their
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	566 # pre-exception values except:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	567 # R3 = ls 16 bits of vector address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	568 # R4 = saved CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	569 # R5 = saved LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	570 # LR = VSR address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	571 # SPRG1 = old R3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	572 # SPRG2 = old R4
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	573 # SPRG3 = old R5
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	574 # SRR0 = old PC
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	575 # SRR1 = old MSR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	576
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	577
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	578 subi r1,r1,ppc_exception_decrement
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	579 # leave space for registers and
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	580 # a safety margin
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	581
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	582 stw r3,ppcreg_vector(r1) # stash vector
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	583 stw r4,ppcreg_cr(r1) # stash CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	584 stw r5,ppcreg_lr(r1) # stash LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	585
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	586 # Enable MMU.
34 29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST jlarmour parents: 32 diff changeset	587 lwi r3,CYG_MSR_NO_INTS
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	588 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	589 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	590 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	591
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	592 mfspr r3,SPRG1 # save original R3
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	593 stw r3,ppcreg_regs+3*4(r1)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	594 mfspr r4,SPRG2 # save original R4
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	595 stw r4,ppcreg_regs+4*4(r1)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	596 mfspr r5,SPRG3 # save original R5
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	597 stw r5,ppcreg_regs+5*4(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	598
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	599 stw r0,ppcreg_regs(r1) # save R0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	600 stw r2,ppcreg_regs+2*4(r1) # save R2
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	601
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	602 mr r3,r1 # recreate original R1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	603 addi r3,r3,ppc_exception_decrement
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	604 stw r3,ppcreg_regs+1*4(r1) # and save it in state
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	605
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	606 # Save registers r6..r12/r31
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	607 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	608 .rept MAX_SAVE_REG+1-6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	609 stw _reg,(ppcreg_regs+_reg*4)(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	610 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	611 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	612
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	613 # Save registers used in vsr (r14+r15)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	614 stw r14,(ppcreg_regs+14*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	615 stw r15,(ppcreg_regs+15*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	616
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	617 # get remaining CPU registers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	618 mfxer r3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	619 mfctr r5
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	620 mfsrr0 r6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	621 mfsrr1 r7
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	622
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	623 # and store them
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	624 stw r3,ppcreg_xer(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	625 stw r5,ppcreg_ctr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	626 stw r6,ppcreg_pc(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	627 stw r7,ppcreg_msr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	628
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	629 # The entire CPU state is now stashed on the stack,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	630 # increment the scheduler lock and call the ISR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	631 # for this vector.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	632
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	633 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	634 .extern cyg_scheduler_sched_lock
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	635 lwi r3,cyg_scheduler_sched_lock
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	636 lwz r4,0(r3)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	637 addi r4,r4,1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	638 stw r4,0(r3)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	639 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	640
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	641 mr r14,sp # r14 = register dump
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	642
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	643 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	644 lwi r3,__interrupt_stack # stack top
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	645 lwi r4,__interrupt_stack_base # stack base
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	646 sub. r5,sp,r4 # sp - base
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	647 blt 1f # if < 0 - not on istack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	648 sub. r5,r3,sp # top - sp
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	649 bgt 2f # if > 0 - already on istack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	650
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	651 1: mr sp,r3 # switch to istack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	652
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	653 2: stwu r14,-4(sp) # save old SP on stack
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	654
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	655 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	656
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	657 subi sp,sp,ppc_stack_frame_size # make a null frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	658
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	659 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	660 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	661 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	662
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	663 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	664 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	665
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	666 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	667
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	668 lwi r3,0x0301 # r3 = type = INTR,RAISE
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	669 lwz r4,ppcreg_vector(r14) # arg1 = vector address
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	670 srwi r4,r4,8 # arg1 = vector number
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	671 xor r5,r5,r5 # arg2 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	672 bl cyg_instrument # call instrument function
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	673
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	674 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	675
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	676 decode_interrupt r15,r14 # get table index
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	677
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	678 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	679 .extern cyg_hal_gdb_isr
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	680 lwz r3,ppcreg_pc(r14) # for serial receive irq.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	681 bl cyg_hal_gdb_isr # (arg1 is PC)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	682 cmpwi r3,0x0000 # Call ISR proper?
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	683 beq 2f # (r3 is 0 when skipping
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	684 # to avoid DSR call)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	685 1:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	686 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	687
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	688 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	689
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	690 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	691 # The CPM controller allows nested interrupts. However,
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	692 # it sits on the back of the SIU controller which has no
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	693 # HW support for this. In effect, SW masking of lower
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	694 # priority IRQs in the SIU would be required for this to work.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	695 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	696
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	697 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	698
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	699 lwz r3,ppcreg_vector(r14) # retrieve decoded vector #
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	700
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	701 lwi r6,hal_interrupt_handlers # get interrupt handler table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	702 lwzx r6,r6,r15 # load routine pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	703
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	704 lwi r4,hal_interrupt_data # get interrupt data table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	705 lwzx r4,r4,r15 # load data pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	706 # R4 = data argument
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	707
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	708 mtctr r6 # put isr address in ctr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	709
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	710 bctrl # branch to ctr reg and link
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	711
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	712 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	713 # If interrupt was caused by GDB, the ISR call above
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	714 # is skipped by jumping here.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	715 2:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	716 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	717
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	718 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	719
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	720 # If we are returning from the last nested interrupt, move back
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	721 # to the thread stack. interrupt_end() must be called on the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	722 # thread stack since it potentially causes a context switch.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	723 # Since we have arranged for the top of stack location to
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	724 # contain the sp we need to go back to here, just pop it off
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	725 # and put it in SP.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	726
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	727
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	728 lwz sp,ppc_stack_frame_size2(sp) # sp = sp
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	729
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	730 subi sp,sp,ppc_stack_frame_size # make a null frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	731
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	732 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	733 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	734 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	735
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	736 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	737 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	738 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	739
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	740 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	741
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	742 # We only need to call _interrupt_end() when there is a kernel
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	743 # present to do any tidying up.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	744
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	745 # on return r3 bit 1 will indicate whether a DSR is
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	746 # to be posted. Pass this together with a pointer to
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	747 # the interrupt object we have just used to the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	748 # interrupt tidy up routine.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	749
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	750 # Note that r14 and r15 are defined to be preserved across
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	751 # calls by the calling convention, so they still contain
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	752 # the register dump and the vector number respectively.
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	753
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	754 # Note: The instructions restoring the msr mask out the POW bit.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	755 # When eCos gets power management aware, this bit will have to be
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	756 # set to the correct state rather than just cleared.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	757
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	758 lwi r4,hal_interrupt_objects # get interrupt object table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	759 lwzx r4,r4,r15 # load object pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	760
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	761 lwz r6,ppcreg_msr(r14) # restore msr, including
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	762 lis r5,0xfffe # interrupt enable.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	763 andc r6,r6,r5 # mask out reserved bits
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	764 sync # (and POW!)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	765 mtmsr r6
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	766 sync
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	767
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	768 mr r5,r14 # arg3 = saved register dump
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	769
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	770 .extern interrupt_end
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	771 bl interrupt_end # call into C to finish off
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	772 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	773
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	774 restore_state:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	775 # All done, restore CPU state and continue
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	776
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	777 addi sp,sp,ppc_stack_frame_size*2 # retrieve CPU state pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	778
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	779 # get sprs we want to restore
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	780 lwz r3,ppcreg_cr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	781 lwz r4,ppcreg_pc(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	782 lwz r5,ppcreg_msr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	783 lwz r6,ppcreg_xer(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	784 lwz r7,ppcreg_lr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	785 lwz r8,ppcreg_ctr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	786
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	787
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	788 # stuff some of them into the CPU
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	789 mtxer r6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	790 mtlr r7
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	791 mtctr r8
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	792
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	793 # restore R0 and R2
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	794 lwz r0,ppcreg_regs(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	795 lwz r2,ppcreg_regs+2*4(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	796
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	797 # Restore registers used in vsr (r14+r15)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	798 lwz r14,(ppcreg_regs+14*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	799 lwz r15,(ppcreg_regs+15*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	800
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	801 # restore registers r6..r12/r31
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	802 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	803 .rept MAX_SAVE_REG+1-6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	804 lwz _reg,(ppcreg_regs+_reg*4)(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	805 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	806 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	807
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	808 # Here all the registers are loaded except
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	809 # r1 = ppcregs
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	810 # r3 = ccr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	811 # r4 = srr0 = pc
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	812 # r5 = srr1 = msr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	813
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	814 # We have to disable interrupts while srr0 and
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	815 # srr1 are loaded, since another interrupt will
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	816 # destroy them.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	817
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	818 mtcr r3 # set ccr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	819
34 29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST jlarmour parents: 32 diff changeset	820 lwi r3,CYG_MSR_NO_INTS # do rest with ints disabled
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	821 sync
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	822 mtmsr r3
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	823 sync
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	824
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	825 mtsrr0 r4 # load old pc
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	826 mtsrr1 r5 # load old msr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	827
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	828 lwz r3,ppcreg_regs+3*4(r1) # load r3 value
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	829 lwz r4,ppcreg_regs+4*4(r1) # load r4 value
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	830 lwz r5,ppcreg_regs+5*4(r1) # load r5 value
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	831 lwz r1,ppcreg_regs+1*4(r1) # restore r1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	832
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	833 sync # settle things down
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	834 isync
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	835 rfi # and return
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	836
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	837
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	838
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	839 ##-----------------------------------------------------------------------------
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	840 ## Execute pending DSRs on the interrupt stack with interrupts enabled.
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	841 ## Note: this can only be called from code running on a thread stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	842
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	843 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	844 .extern cyg_interrupt_call_pending_DSRs
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	845
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	846 FUNC_START(hal_interrupt_stack_call_pending_DSRs)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	847 # Disable interrupts
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	848 mfmsr r4
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	849 lis r3,0
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	850 ori r3,r3,0x8000
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	851 andc r5,r4,r3
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	852 mtmsr r5
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	853
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	854 # Change to interrupt stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	855 mr r3,sp
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	856 lwi sp,__interrupt_stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	857 stwu r3,-4(sp) # store old stackptr on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	858 mflr r3
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	859 stwu r3,-4(sp) # store lr on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	860 stwu r4,-4(sp) # store msr values on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	861 stwu r5,-4(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	862
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	863 # Set up stack for calls to C code.
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	864 subi sp,sp,12 # make space on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	865 li r0,0
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	866 stw r0,0(sp) # clear back chain
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	867 stw r0,8(sp) # zero return pc
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	868 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	869
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	870 # Restore interrupt state
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	871 mtmsr r4
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	872
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	873 # Call into kernel which will execute DSRs
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	874 bl cyg_interrupt_call_pending_DSRs
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	875
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	876 # Unwind stack and get msr values
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	877 lwzu r5,12+ppc_stack_frame_size(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	878 lwz r4,4(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	879 lwz r3,8(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	880 mtlr r3
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	881
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	882 # Disable interrupts
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	883 mtmsr r5
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	884
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	885 # Restore original stack pointer, original interrupt state and return
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	886 lwz sp,12(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	887 mtmsr r4
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	888
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	889 blr
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	890 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	891
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	892 #---------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	893 # Code for putting the CPU in a post-reset state; disabling MMU and caches.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	894 _init_CPU:
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	895 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	896 lwi r3,CYGARC_REG_DC_CMD_CD
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	897 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	898 mtspr CYGARC_REG_DC_CST,r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	899 lwi r3,CYGARC_REG_IC_CMD_CD
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	900 isync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	901 mtspr CYGARC_REG_IC_CST,r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	902 isync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	903 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	904
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	905 # Set up MSR (disable MMU for now)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	906 lwi r3,(CYG_MSR & ~(MSR_IR \| MSR_DR))
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	907 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	908 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	909 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	910 blr
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	911
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	912 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	913 # This table contains a VSR pointer for each defined exception.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	914 # All of these except 5 and 9 point to the __default_exception_vsr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	915 # above, 5 and 9 point to the __default_interrupt_vsr. Entries in
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	916 # this table may be changed using Cyg_Interrupt::set_vsr().
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	917
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	918 .data
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	919
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	920 .globl hal_vsr_table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	921 hal_vsr_table:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	922 # Architecture defined vectors
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	923 .long __default_exception_vsr # reserved
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	924 .long __default_exception_vsr # system reset
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	925 .long __default_exception_vsr # machine check
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	926 .long __default_exception_vsr # data storage
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	927 .long __default_exception_vsr # instruction storage
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	928
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	929 .long __default_interrupt_vsr # external interrupt
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	930
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	931 .long __default_exception_vsr # alignment
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	932 .long __default_exception_vsr # program
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	933 .long __default_exception_vsr # floating point unavailable
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	934
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	935 .long __default_interrupt_vsr # decrementer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	936
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	937 .long __default_exception_vsr # reserved 0x0a00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	938 .long __default_exception_vsr # reserved 0x0b00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	939 .long __default_exception_vsr # system call
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	940 .long __default_exception_vsr # trace
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	941 .long __default_exception_vsr # floating point assist
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	942 .long __default_exception_vsr # reserved 0x0f00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	943
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	944 #ifdef CYG_HAL_POWERPC_MPC8xx
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	945
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	946 # Implementation defined vectors
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	947 .long __default_exception_vsr # software emulation
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	948 .long __default_exception_vsr # instruction TLB miss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	949 .long __default_exception_vsr # data TLB miss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	950 .long __default_exception_vsr # instruction TLB error
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	951 .long __default_exception_vsr # data TLB error
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	952 .long __default_exception_vsr # reserved 0x1500
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	953 .long __default_exception_vsr # reserved 0x1600
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	954 .long __default_exception_vsr # reserved 0x1700
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	955 .long __default_exception_vsr # reserved 0x1800
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	956 .long __default_exception_vsr # reserved 0x1900
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	957 .long __default_exception_vsr # reserved 0x1a00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	958 .long __default_exception_vsr # reserved 0x1b00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	959 .long __default_exception_vsr # data breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	960 .long __default_exception_vsr # instruction breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	961 .long __default_exception_vsr # peripheral breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	962 .long __default_exception_vsr # non maskable development port
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	963 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	964
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	965 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	966 # Interrupt vector tables.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	967 # These tables contain the isr, data and object pointers used to deliver
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	968 # interrupts to user code.
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	969
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	970 #if (CYG_ISR_TABLE_SIZE > 2)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	971 .data
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	972 #else
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	973 .section ".sdata","aw"
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	974 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	975
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	976 .extern hal_default_decrementer_isr
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	977 .extern hal_default_isr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	978
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	979 .globl hal_interrupt_handlers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	980 hal_interrupt_handlers:
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	981 .long hal_default_decrementer_isr
01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	982 .rept CYG_ISR_TABLE_SIZE-1
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	983 .long hal_default_isr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	984 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	985
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	986 .globl hal_interrupt_data
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	987 hal_interrupt_data:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	988 .rept CYG_ISR_TABLE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	989 .long 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	990 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	991
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	992 .globl hal_interrupt_objects
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	993 hal_interrupt_objects:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	994 .rept CYG_ISR_TABLE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	995 .long 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	996 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	997
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	998 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	999 ## Temporary interrupt stack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1000
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1001 .section ".bss"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1002
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1003 .balign 16
8 ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	1004 .global cyg_interrupt_stack_base
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	1005 cyg_interrupt_stack_base:
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1006 __interrupt_stack_base:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1007 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1008 .byte 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1009 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1010 .balign 16
8 ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	1011 .global cyg_interrupt_stack
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	1012 cyg_interrupt_stack:
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1013 __interrupt_stack:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1014
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1015 .long 0,0,0,0,0,0,0,0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1016
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	1017 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1018 # end of vectors.S

Mercurial > ecos

annotate packages/hal/powerpc/arch/current/src/vectors.S @ 46:797268ecc331 ecos-sw-1999-10-19