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annotate packages/devs/eth/sh/etherc/current/src/sh_etherc.h @ 3292:7f8e529b4d82 default tip

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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 74dbf4c3f2e1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #ifndef CYGONCE_DEVS_ETH_SH_ETHERC_H
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2 #define CYGONCE_DEVS_ETH_SH_ETHERC_H
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3 //==========================================================================
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4 //
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5 // sh_etherc.h
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6 //
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7 // SH EtherC Ethernet CPU module controller
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8 //
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9 //==========================================================================
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10 // ####ECOSGPLCOPYRIGHTBEGIN####
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11 // -------------------------------------------
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12 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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14 //
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15 // eCos is free software; you can redistribute it and/or modify it under
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16 // the terms of the GNU General Public License as published by the Free
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17 // Software Foundation; either version 2 or (at your option) any later
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18 // version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT
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21 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License
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26 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use
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30 // macros or inline functions from this file, or you compile this file
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31 // and link it with other works to produce a work based on this file,
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32 // this file does not by itself cause the resulting work to be covered by
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33 // the GNU General Public License. However the source code for this file
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34 // must still be made available in accordance with section (3) of the GNU
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35 // General Public License v2.
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36 //
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37 // This exception does not invalidate any other reasons why a work based
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38 // on this file might be covered by the GNU General Public License.
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39 // -------------------------------------------
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40 // ####ECOSGPLCOPYRIGHTEND####
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41 //==========================================================================
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42 //#####DESCRIPTIONBEGIN####
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43 //
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44 // Author(s): jskov
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45 // Contributors: jskov
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46 // Date: 2002-01-30
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47 // Purpose: Hardware description of SH EtherC controller.
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48 // Description:
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49 //
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50 //####DESCRIPTIONEND####
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51 //
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52 //==========================================================================
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53
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54 #include <cyg/hal/hal_io.h>
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55
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56 //------------------------------------------------------------------------
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57 // Get macros from platform header
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58 #define __WANT_CONFIG
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59 #include CYGDAT_DEVS_ETH_SH_ETHERC_INL
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60 #undef __WANT_CONFIG
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61
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62 //------------------------------------------------------------------------
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63 // Set to perms of:
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64 // 0 disables all debug output
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65 // 1 for process debug output
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66 // 2 for added data IO output: get_reg, put_reg
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67 // 4 for packet allocation/free output
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68 // 8 for only startup status, so we can tell we're installed OK
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69 #define DEBUG 0x0
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70
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71 #if DEBUG & 1
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72 #define DEBUG_FUNCTION() do { db_printf("%s\n", __FUNCTION__); } while (0)
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73 #else
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74 #define DEBUG_FUNCTION() do {} while(0)
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75 #endif
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76
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77 // ------------------------------------------------------------------------
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78 // Debug print function
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79 #if defined(CYGPKG_REDBOOT) && DEBUG
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80
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81 static void db_printf( char *fmt, ... )
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82 {
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83 extern int start_console(void);
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84 extern void end_console(int);
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85 va_list a;
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86 int old_console;
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87 va_start( a, fmt );
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88 old_console = start_console();
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89 diag_vprintf( fmt, a );
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90 end_console(old_console);
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91 va_end( a );
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92 }
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93
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94 #else
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95
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96 #define db_printf diag_printf
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97
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98 #endif
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99
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100 // ------------------------------------------------------------------------
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101 // Macros for keeping track of statistics
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102 #if defined(ETH_DRV_GET_IF_STATS) || defined (ETH_DRV_GET_IF_STATS_UD)
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103 # define KEEP_STATISTICS
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104 #endif
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105
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106 #ifdef KEEP_STATISTICS
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107 # define INCR_STAT( _x_ ) (cpd->stats. _x_ ++)
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108 #else
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109 # define INCR_STAT( _x_ ) CYG_EMPTY_STATEMENT
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110 #endif
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111
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112 //------------------------------------------------------------------------
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113 // Cache translation
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114 #ifndef CYGARC_UNCACHED_ADDRESS
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115 # define CYGARC_UNCACHED_ADDRESS(x) (x)
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116 #endif
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117
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118 // ------------------------------------------------------------------------
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119 // Macros for accessing structure elements
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120
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121 #define _SU8( _base_, _offset_) \
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122 *((cyg_uint8 *)((CYG_ADDRWORD)_base_+(_offset_)))
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123 #define _SU16( _base_, _offset_) \
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124 *((cyg_uint16 *)((CYG_ADDRWORD)_base_+(_offset_)))
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125 #define _SU32( _base_, _offset_) \
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126 *((cyg_uint32 *)((CYG_ADDRWORD)_base_+(_offset_)))
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127
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128 #define _SI8( _base_, _offset_) \
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129 *((cyg_int8 *)((CYG_ADDRWORD)_base_+(_offset_)))
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130 #define _SI16( _base_, _offset_) \
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131 *((cyg_int16 *)((CYG_ADDRWORD)_base_+(_offset_)))
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132 #define _SI32( _base_, _offset_) \
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133 *((cyg_int32 *)((CYG_ADDRWORD)_base_+(_offset_)))
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134
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135 // ------------------------------------------------------------------------
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136 // Controller registers in offset form
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137 #define _REG_EDMR 0x00
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138 #define _REG_EDTRR 0x04
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139 #define _REG_EDRRR 0x08
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140 #define _REG_TDLAR 0x0c
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141 #define _REG_RDLAR 0x10
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142 #define _REG_EESR 0x14
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143 #define _REG_EESIPR 0x18
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144 #define _REG_TRSCER 0x1c
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145 #define _REG_RMFCR 0x20
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146 #define _REG_TFTR 0x24
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147 #define _REG_FDR 0x28
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148 #define _REG_RCR 0x2c
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149 #define _REG_EDOCR 0x30
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150 #define _REG_RBWAR 0x40
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151 #define _REG_RDFAR 0x44
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152 #define _REG_TBRAR 0x4c
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153 #define _REG_TDFAR 0x50
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154
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155 #define _REG_ECMR 0x60
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156 #define _REG_ECSR 0x64
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157 #define _REG_ECSIPR 0x68
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158 #define _REG_PIR 0x6c
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159 #define _REG_MAHR 0x70
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160 #define _REG_MALR 0x74
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161 #define _REG_RFLR 0x78
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162 #define _REG_PSR 0x7c
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163 #define _REG_TROCR 0x80
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164 #define _REG_CDCR 0x84
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165 #define _REG_LCCR 0x88
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166 #define _REG_CNDCR 0x8c
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167 #define _REG_IFLCR 0x90
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168 #define _REG_CECFR 0x94
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169 #define _REG_FRECR 0x98
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170 #define _REG_TSFRCR 0x9c
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171 #define _REG_TLFRCR 0xa0
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172 #define _REG_RFCR 0xa4
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173 #define _REG_MAFCR 0xa8
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174
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175 //----------------------------------------------------------------------------
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176 // Receive buffer Descriptor
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177 #define ETHERC_RD_STAT 0x00 // 32 bit
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178 #define ETHERC_RD_RBL 0x04 // 16 bit - receive buffer length
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179 #define ETHERC_RD_RDL 0x06 // 16 bit - receive data length (-CRC)
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180 #define ETHERC_RD_RBA 0x08 // 32 bit - receive buffer address
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181 #define ETHERC_RD_PAD 0x0c // 32 bit
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182 #define ETHERC_RD_SIZE 0x10
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183
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184 #define ETHERC_RD_STAT_RACT 0x80000000
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185 #define ETHERC_RD_STAT_RDLE 0x40000000
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186 #define ETHERC_RD_STAT_RFP_OTO 0x30000000 // one buffer to one frame
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187 #define ETHERC_RD_STAT_RFE 0x08000000
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188 #define ETHERC_RD_STAT_RFOF 0x00000200
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189 #define ETHERC_RD_STAT_RMAF 0x00000080
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190 #define ETHERC_RD_STAT_RRF 0x00000010
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191 #define ETHERC_RD_STAT_RTLF 0x00000008
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192 #define ETHERC_RD_STAT_RTSF 0x00000004
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193 #define ETHERC_RD_STAT_PRE 0x00000002
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194 #define ETHERC_RD_STAT_CERF 0x00000001
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195
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196 #define ETHERC_RD_STAT_CLEAR 0x70000000
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197
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198 // Transmit buffer Descriptor
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199 #define ETHERC_TD_STAT 0x00 // 32 bit
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200 #define ETHERC_TD_TDL 0x04 // 16 bit - transmit data length
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201 #define ETHERC_TD_PAD0 0x06 // 16 bit
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202 #define ETHERC_TD_TBA 0x08 // 32 bit - transmit buffer address
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203 #define ETHERC_TD_PAD1 0x0c // 32 bit
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204 #define ETHERC_TD_SIZE 0x10
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205
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206 #define ETHERC_TD_STAT_TACT 0x80000000
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207 #define ETHERC_TD_STAT_TDLE 0x40000000
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208 #define ETHERC_TD_STAT_TFP_OTO 0x30000000 // one buffer to one frame
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209 #define ETHERC_TD_STAT_TDFE 0x08000000
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210 #define ETHERC_TD_STAT_ITF 0x00000010
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211 #define ETHERC_TD_STAT_CND 0x00000008
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212 #define ETHERC_TD_STAT_DLC 0x00000004
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213 #define ETHERC_TD_STAT_CD 0x00000002
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214 #define ETHERC_TD_STAT_TRO 0x00000001
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215
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216
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217 // Initialization Buffer
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218 #define ETHERC_IB_MODE 0
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219 #define ETHERC_IB_PADR0 2
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220 #define ETHERC_IB_PADR1 4
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221 #define ETHERC_IB_PADR2 6
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222 #define ETHERC_IB_LADRF0 8
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223 #define ETHERC_IB_LADRF1 10
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224 #define ETHERC_IB_LADRF2 12
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225 #define ETHERC_IB_LADRF3 14
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226 #define ETHERC_IB_RDRA 16
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227 #define ETHERC_IB_TDRA 20
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228 #define ETHERC_IB_SIZE 24
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229
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230 #define ETHERC_IB_TDRA_CNT_shift 29
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231 #define ETHERC_IB_TDRA_PTR_mask 0x00ffffff
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232 #define ETHERC_IB_RDRA_CNT_shift 29
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233 #define ETHERC_IB_RDRA_PTR_mask 0x00ffffff
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234
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235 // ------------------------------------------------------------------------
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236
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237 #ifdef KEEP_STATISTICS
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238 struct sh_etherc_stats {
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239 unsigned int tx_good ;
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240 unsigned int tx_max_collisions ;
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241 unsigned int tx_late_collisions ;
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242 unsigned int tx_underrun ;
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243 unsigned int tx_carrier_loss ;
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244 unsigned int tx_deferred ;
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245 unsigned int tx_sqetesterrors ;
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246 unsigned int tx_single_collisions;
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247 unsigned int tx_mult_collisions ;
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248 unsigned int tx_total_collisions ;
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249 unsigned int rx_good ;
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250 unsigned int rx_crc_errors ;
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251 unsigned int rx_align_errors ;
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252 unsigned int rx_resource_errors ;
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253 unsigned int rx_overrun_errors ;
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254 unsigned int rx_collisions ;
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255 unsigned int rx_short_frames ;
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256 unsigned int rx_too_long_frames ;
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257 unsigned int rx_symbol_errors ;
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258 unsigned int interrupts ;
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259 unsigned int rx_count ;
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260 unsigned int rx_deliver ;
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261 unsigned int rx_resource ;
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262 unsigned int rx_restart ;
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263 unsigned int tx_count ;
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264 unsigned int tx_complete ;
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265 unsigned int tx_dropped ;
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266 };
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267 #endif
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268
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269 struct etherc_priv_data;
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270 typedef cyg_bool (*provide_esa_t)(struct etherc_priv_data* cpd);
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271
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272 typedef struct etherc_priv_data {
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273 int index;
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274 cyg_uint8 // (split up for atomic byte access)
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275 mac_addr_ok:1, // can we bring up?
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276 active:1, // has this if been brung up?
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277 hardwired_esa:1, // set if ESA is hardwired via CDL
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278 txbusy:1, // A packet has been sent
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279 spare1:3;
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280
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281 unsigned long txkey; // Used to ack when packet sent
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282 unsigned char* base; // Base address of controller EPROM region
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283 int interrupt; // Interrupt vector used by controller
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284 unsigned char esa[6]; // Controller ESA
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285 // Function to configure the ESA - may fetch ESA from EPROM or
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286 // RedBoot config option.
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287 void (*config_esa)(struct etherc_priv_data* cpd);
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288 void *ndp; // Network Device Pointer
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289 provide_esa_t provide_esa;
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290
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291 cyg_handle_t interrupt_handle;
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292 cyg_interrupt interrupt_object;
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293 int devid;
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294
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295 cyg_uint8* rx_buffers; // ptr to base of buffer mem
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296 cyg_uint8* rx_ring; // ptr to base of rx ring memory
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297 int rx_ring_cnt; // number of entries in ring
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298 int rx_ring_next; // index of next full ring entry
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299
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300 cyg_uint8* tx_buffers;
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301 cyg_uint8* tx_ring;
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302 int tx_ring_cnt;
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303 int tx_ring_free; // index of next free ring entry
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304 int tx_ring_alloc; // index of first controller owned ring
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305 int tx_ring_owned; // number of controller owned ring entries
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306
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307 int rxpacket;
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308 #ifdef KEEP_STATISTICS
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309 struct sh_etherc_stats stats;
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310 #endif
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311 #if DEBUG & 1
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312 cyg_uint32 txd;
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313 #endif
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314 } etherc_priv_data;
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315
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316 // ------------------------------------------------------------------------
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317
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318 static __inline__ cyg_uint32
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319 get_reg(struct etherc_priv_data *cpd, int regno)
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320 {
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321 cyg_int32 val;
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322
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323 HAL_READ_UINT32(cpd->base+regno, val);
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324
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325 #if DEBUG & 2
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326 db_printf("read reg %d val 0x%08x\n", regno, val);
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327 #endif
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328 return val;
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329 }
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330
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331 static __inline__ void
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332 put_reg(struct etherc_priv_data *cpd, int regno, cyg_uint32 val)
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333 {
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334 HAL_WRITE_UINT32(cpd->base+regno, val);
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335
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336 #if DEBUG & 2
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337 db_printf("write reg %d val 0x%08x\n", regno, val);
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338 #endif
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339 }
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340
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341 // ------------------------------------------------------------------------
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342 #endif // CYGONCE_DEVS_ETH_SH_ETHERC_H
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343 // EOF sh_etherc.h