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annotate packages/devs/serial/arm/aeb/current/src/aeb_serial.h @ 3292:7f8e529b4d82 default tip

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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 74dbf4c3f2e1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #ifndef CYGONCE_ARM_AEB_SERIAL_H
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2 #define CYGONCE_ARM_AEB_SERIAL_H
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3
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4 // ====================================================================
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5 //
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6 // aeb_serial.h
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7 //
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8 // Device I/O - Description of ARM AEB-1 serial hardware
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9 //
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10 // ====================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 // ====================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): gthomas
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46 // Contributors: gthomas
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47 // Date: 1999-02-04
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48 // Purpose: Internal interfaces for serial I/O drivers
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49 // Description:
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50 //
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51 //####DESCRIPTIONEND####
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52 //
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53 // ====================================================================
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54
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55 // Description of serial ports on ARM AEB-1
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56
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57 struct serial_port {
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58 unsigned char _byte[32];
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59 };
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60
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61 #define REG(n) _byte[n*4]
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62
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63 // Receive control registers
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64 #define REG_RHR REG(0) // Receive holding register
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65 #define REG_ISR REG(2) // Interrupt status register
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66 #define REG_LSR REG(5) // Line status register
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67 #define REG_MSR REG(6) // Modem status register
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68 #define REG_SCR REG(7) // Scratch register
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69
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70 // Transmit control registers
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71 #define REG_THR REG(0) // Transmit holding register
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72 #define REG_IER REG(1) // Interrupt enable register
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73 #define REG_FCR REG(2) // FIFO control register
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74 #define REG_LCR REG(3) // Line control register
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75 #define REG_MCR REG(4) // Modem control register
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76 #define REG_LDL REG(0) // LSB of baud rate
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77 #define REG_MDL REG(1) // MSB of baud rate
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78
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79 // Interrupt Enable Register
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80 #define IER_RCV 0x01
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81 #define IER_XMT 0x02
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82 #define IER_LS 0x04
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83 #define IER_MS 0x08
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84
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85 // Line Control Register
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86 #define LCR_WL5 0x00 // Word length
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87 #define LCR_WL6 0x01
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88 #define LCR_WL7 0x02
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89 #define LCR_WL8 0x03
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90 #define LCR_SB1 0x00 // Number of stop bits
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91 #define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words
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92 #define LCR_SB2 0x04
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93 #define LCR_PN 0x00 // Parity mode - none
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94 #define LCR_PE 0x0C // Parity mode - even
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95 #define LCR_PO 0x08 // Parity mode - odd
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96 #define LCR_PM 0x28 // Forced "mark" parity
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97 #define LCR_PS 0x38 // Forced "space" parity
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98 #define LCR_DL 0x80 // Enable baud rate latch
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99
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100 // Line Status Register
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101 #define LSR_RSR 0x01
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102 #define LSR_THE 0x20
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103
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104 // Modem Control Register
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105 #define MCR_DTR 0x01
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106 #define MCR_RTS 0x02
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107 #define MCR_INT 0x08 // Enable interrupts
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108
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109 // Interrupt status register
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110 #define ISR_Tx 0x02
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111 #define ISR_Rx 0x04
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112
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113 static unsigned char select_word_length[] = {
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114 LCR_WL5, // 5 bits / word (char)
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115 LCR_WL6,
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116 LCR_WL7,
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117 LCR_WL8
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118 };
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119
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120 static unsigned char select_stop_bits[] = {
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121 0,
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122 LCR_SB1, // 1 stop bit
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123 LCR_SB1_5, // 1.5 stop bit
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124 LCR_SB2 // 2 stop bits
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125 };
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126
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127 static unsigned char select_parity[] = {
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128 LCR_PN, // No parity
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129 LCR_PE, // Even parity
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130 LCR_PO, // Odd parity
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131 LCR_PM, // Mark parity
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132 LCR_PS, // Space parity
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133 };
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134
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135 // Baud rate values, based on raw 24MHz clock
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136
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137 static unsigned short select_baud[] = {
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138 0, // Unused
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139 10000*3, // 50
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140 6667*3, // 75
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141 4545*3, // 110
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142 3717*3, // 134.5
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143 3333*3, // 150
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diff changeset
144 0, // 200
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
145 1667*3, // 300
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
146 833*3, // 600
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
147 417*3, // 1200
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
148 277*3, // 1800
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
149 208*3, // 2400
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
150 139*3, // 3600
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
151 104*3, // 4800
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
152 69*3, // 7200
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
153 52*3, // 9600
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
154 (69*3)/2, // 14400
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
155 26*3, // 19200
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
156 13*3, // 38400
124
0ec04793409a Merge from eCos master repository on 2000-09-11-03:00:13-BST
jlarmour
parents: 82
diff changeset
157 26, // 57600
0ec04793409a Merge from eCos master repository on 2000-09-11-03:00:13-BST
jlarmour
parents: 82
diff changeset
158 13, // 115200
82
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
159 0, // 230400
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
160 };
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
161
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents:
diff changeset
162 #endif // CYGONCE_ARM_AEB_SERIAL_H