Mercurial > ecos
annotate packages/hal/arm/aeb/current/src/aeb_misc.c @ 3292:7f8e529b4d82 default tip
Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
| author | vae |
|---|---|
| date | Wed, 29 Apr 2015 23:31:48 +0000 |
| parents | 74dbf4c3f2e1 |
| children |
| rev | line source |
|---|---|
| 2 | 1 //========================================================================== |
| 2 // | |
| 3 // aeb_misc.c | |
| 4 // | |
| 5 // HAL misc board support code for ARM AEB-1 | |
| 6 // | |
| 7 //========================================================================== | |
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8 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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9 // ------------------------------------------- |
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10 // This file is part of eCos, the Embedded Configurable Operating System. |
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
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12 // |
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13 // eCos is free software; you can redistribute it and/or modify it under |
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14 // the terms of the GNU General Public License as published by the Free |
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15 // Software Foundation; either version 2 or (at your option) any later |
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16 // version. |
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17 // |
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 // for more details. |
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22 // |
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23 // You should have received a copy of the GNU General Public License |
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24 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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26 // |
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27 // As a special exception, if other files instantiate templates or use |
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28 // macros or inline functions from this file, or you compile this file |
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29 // and link it with other works to produce a work based on this file, |
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30 // this file does not by itself cause the resulting work to be covered by |
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31 // the GNU General Public License. However the source code for this file |
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32 // must still be made available in accordance with section (3) of the GNU |
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33 // General Public License v2. |
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34 // |
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35 // This exception does not invalidate any other reasons why a work based |
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36 // on this file might be covered by the GNU General Public License. |
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37 // ------------------------------------------- |
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38 // ####ECOSGPLCOPYRIGHTEND#### |
| 2 | 39 //========================================================================== |
| 40 //#####DESCRIPTIONBEGIN#### | |
| 41 // | |
| 42 // Author(s): gthomas | |
| 43 // Contributors: gthomas | |
| 44 // Date: 1999-02-20 | |
| 45 // Purpose: HAL board support | |
| 46 // Description: Implementations of HAL board interfaces | |
| 47 // | |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 50 //========================================================================*/ | |
| 51 | |
| 52 #include <pkgconf/hal.h> | |
| 53 | |
| 54 #include <cyg/infra/cyg_type.h> // base types | |
| 55 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 56 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 57 | |
| 58 #include <cyg/hal/hal_io.h> // IO macros | |
| 59 #include <cyg/hal/hal_arch.h> // Register state info | |
| 60 #include <cyg/hal/hal_diag.h> | |
| 61 #include <cyg/hal/hal_intr.h> // necessary? | |
| 62 #include <cyg/hal/hal_cache.h> | |
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63 #include <cyg/hal/hal_if.h> // calling interface |
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64 #include <cyg/hal/hal_misc.h> // helper functions |
| 2 | 65 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT |
| 66 #include <cyg/hal/drv_api.h> // HAL ISR support | |
| 67 #endif | |
| 68 | |
| 69 /*------------------------------------------------------------------------*/ | |
| 70 // On-board timer | |
| 71 /*------------------------------------------------------------------------*/ | |
| 72 | |
| 73 // Timer registers | |
| 74 #define CYG_DEVICE_TIMER0 ((volatile cyg_uint8 *)0xFFFF1800) | |
| 75 #define CYG_DEVICE_TIMER1 ((volatile cyg_uint8 *)0xFFFF1804) | |
| 76 #define CYG_DEVICE_TIMER2 ((volatile cyg_uint8 *)0xFFFF1808) | |
| 77 #define CYG_DEVICE_TIMER_CTL ((volatile cyg_uint8 *)0xFFFF180C) | |
| 78 #define CYG_DEVICE_IOCR ((volatile cyg_uint32 *)0xFFFFA410) | |
| 79 #define CYG_DEVICE_CPM_PCSR ((volatile cyg_uint32 *)0xFFFFAC04) | |
| 80 #define CYG_DEVICE_CPM_CT0CCR ((volatile cyg_uint32 *)0xFFFFAC18) | |
| 81 #define CYG_DEVICE_CPM_CT1CCR ((volatile cyg_uint32 *)0xFFFFAC1C) | |
| 82 #define CYG_DEVICE_CPM_CT2CCR ((volatile cyg_uint32 *)0xFFFFAC20) | |
| 83 | |
| 84 #define IOCR_CT0G (0x3<<9) | |
| 85 #define IOCR_CT0G_EXTERNAL (0x0<<9) | |
| 86 #define IOCR_CT0G_PWM0 (0x1<<9) | |
| 87 #define IOCR_CT0G_LOW (0x2<<9) | |
| 88 #define IOCR_CT0G_HIGH (0x3<<9) | |
| 89 | |
| 90 #define IOCR_CT1G (0x3<<11) | |
| 91 #define IOCR_CT1G_EXTERNAL (0x0<<11) | |
| 92 #define IOCR_CT1G_PWM0 (0x1<<11) | |
| 93 #define IOCR_CT1G_LOW (0x2<<11) | |
| 94 #define IOCR_CT1G_HIGH (0x3<<11) | |
| 95 | |
| 96 #define IOCR_CT2G (0x3<<13) | |
| 97 #define IOCR_CT2G_EXTERNAL (0x0<<13) | |
| 98 #define IOCR_CT2G_PWM0 (0x1<<13) | |
| 99 #define IOCR_CT2G_LOW (0x2<<13) | |
| 100 #define IOCR_CT2G_HIGH (0x3<<13) | |
| 101 | |
| 102 #define TIMER_CTL_TYPE (0x1<<0) | |
| 103 #define TIMER_CTL_TYPE_BIN (0x0<<0) | |
| 104 #define TIMER_CTL_TYPE_BCD (0x1<<0) | |
| 105 #define TIMER_CTL_MODE (0x7<<1) | |
| 106 #define TIMER_CTL_MODE_IOTC (0x0<<1) // Interrupt on terminal count | |
| 107 #define TIMER_CTL_MODE_HROS (0x1<<1) // Hardware retriggerable one-shot | |
| 108 #define TIMER_CTL_MODE_RG (0x2<<1) // Rate generator | |
| 109 #define TIMER_CTL_MODE_SWG (0x3<<1) // Square-wave generator | |
| 110 #define TIMER_CTL_MODE_STS (0x4<<1) // Software triggered strobe | |
| 111 #define TIMER_CTL_MODE_HTS (0x5<<1) // Hardware triggered strobe | |
| 112 #define TIMER_CTL_RW (0x3<<4) | |
| 113 #define TIMER_CTL_RW_LATCH (0x0<<4) // Counter latch | |
| 114 #define TIMER_CTL_RW_LSB (0x1<<4) | |
| 115 #define TIMER_CTL_RW_MSB (0x2<<4) | |
| 116 #define TIMER_CTL_RW_BOTH (0x3<<4) | |
| 117 #define TIMER_CTL_SC (0x3<<6) | |
| 118 #define TIMER_CTL_SC_CTR0 (0x0<<6) | |
| 119 #define TIMER_CTL_SC_CTR1 (0x1<<6) | |
| 120 #define TIMER_CTL_SC_CTR2 (0x2<<6) | |
| 121 #define TIMER_CTL_SC_RBC (0x3<<6) | |
| 122 | |
| 123 // Interrupt controller registers | |
| 124 #define CYG_DEVICE_ICTL_ICR0 ((volatile cyg_uint32 *)0xFFFFA800) | |
| 125 #define CYG_DEVICE_ICTL_ICR1 ((volatile cyg_uint32 *)0xFFFFA804) | |
| 126 #define CYG_DEVICE_ICTL_ICLR ((volatile cyg_uint32 *)0xFFFFA808) | |
| 127 #define CYG_DEVICE_ICTL_IRQER ((volatile cyg_uint32 *)0xFFFFA80C) | |
| 128 #define CYG_DEVICE_ICTL_FIQER ((volatile cyg_uint32 *)0xFFFFA810) | |
| 129 #define CYG_DEVICE_ICTL_IRQSR ((volatile cyg_uint32 *)0xFFFFA814) | |
| 130 #define CYG_DEVICE_ICTL_FIQSR ((volatile cyg_uint32 *)0xFFFFA818) | |
| 131 #define CYG_DEVICE_ICTL_IPR ((volatile cyg_uint32 *)0xFFFFA81C) | |
| 132 | |
| 133 #define ICTL_ICR0_CH0 (0x3<<0) | |
| 134 #define ICTL_ICR0_CH0_HL (0x1<<0) | |
| 135 #define ICTL_ICR0_CH0_HL_AL (0x0<<0) // Active low | |
| 136 #define ICTL_ICR0_CH0_HL_AH (0x1<<0) // Active high | |
| 137 #define ICTL_ICR0_CH0_EL (0x2<<0) | |
| 138 #define ICTL_ICR0_CH0_EL_LT (0x0<<0) // Level triggered | |
| 139 #define ICTL_ICR0_CH0_EL_ET (0x2<<0) // Edge triggered | |
| 140 #define ICTL_ICR0_CH1 (0x3<<2) | |
| 141 #define ICTL_ICR0_CH1_HL (0x1<<2) | |
| 142 #define ICTL_ICR0_CH1_HL_AL (0x0<<2) // Active low | |
| 143 #define ICTL_ICR0_CH1_HL_AH (0x1<<2) // Active high | |
| 144 #define ICTL_ICR0_CH1_EL (0x2<<2) | |
| 145 #define ICTL_ICR0_CH1_EL_LT (0x0<<2) // Level triggered | |
| 146 #define ICTL_ICR0_CH1_EL_ET (0x2<<2) // Edge triggered | |
| 147 #define ICTL_ICR0_CH2 (0x3<<4) | |
| 148 #define ICTL_ICR0_CH2_HL (0x1<<4) | |
| 149 #define ICTL_ICR0_CH2_HL_AL (0x0<<4) // Active low | |
| 150 #define ICTL_ICR0_CH2_HL_AH (0x1<<4) // Active high | |
| 151 #define ICTL_ICR0_CH2_EL (0x2<<4) | |
| 152 #define ICTL_ICR0_CH2_EL_LT (0x0<<4) // Level triggered | |
| 153 #define ICTL_ICR0_CH2_EL_ET (0x2<<4) // Edge triggered | |
| 154 #define ICTL_ICR0_CH3 (0x3<<6) | |
| 155 #define ICTL_ICR0_CH3_HL (0x1<<6) | |
| 156 #define ICTL_ICR0_CH3_HL_AL (0x0<<6) // Active low | |
| 157 #define ICTL_ICR0_CH3_HL_AH (0x1<<6) // Active high | |
| 158 #define ICTL_ICR0_CH3_EL (0x2<<6) | |
| 159 #define ICTL_ICR0_CH3_EL_LT (0x0<<6) // Level triggered | |
| 160 #define ICTL_ICR0_CH3_EL_ET (0x2<<6) // Edge triggered | |
| 161 #define ICTL_ICR0_CH4 (0x3<<8) | |
| 162 #define ICTL_ICR0_CH4_HL (0x1<<8) | |
| 163 #define ICTL_ICR0_CH4_HL_AL (0x0<<8) // Active low | |
| 164 #define ICTL_ICR0_CH4_HL_AH (0x1<<8) // Active high | |
| 165 #define ICTL_ICR0_CH4_EL (0x2<<8) | |
| 166 #define ICTL_ICR0_CH4_EL_LT (0x0<<8) // Level triggered | |
| 167 #define ICTL_ICR0_CH4_EL_ET (0x2<<8) // Edge triggered | |
| 168 #define ICTL_ICR0_CH5 (0x3<<10) | |
| 169 #define ICTL_ICR0_CH5_HL (0x1<<10) | |
| 170 #define ICTL_ICR0_CH5_HL_AL (0x0<<10) // Active low | |
| 171 #define ICTL_ICR0_CH5_HL_AH (0x1<<10) // Active high | |
| 172 #define ICTL_ICR0_CH5_EL (0x2<<10) | |
| 173 #define ICTL_ICR0_CH5_EL_LT (0x0<<10) // Level triggered | |
| 174 #define ICTL_ICR0_CH5_EL_ET (0x2<<10) // Edge triggered | |
| 175 #define ICTL_ICR1_CH6 (0x1<<0) | |
| 176 #define ICTL_ICR1_CH6_HL (0x1<<0) | |
| 177 #define ICTL_ICR1_CH6_HL_AL (0x0<<0) // Active low | |
| 178 #define ICTL_ICR1_CH6_HL_AH (0x1<<0) // Active high | |
| 179 #define ICTL_ICR1_CH7 (0x1<<1) | |
| 180 #define ICTL_ICR1_CH7_HL (0x1<<1) | |
| 181 #define ICTL_ICR1_CH7_HL_AL (0x0<<1) // Active low | |
| 182 #define ICTL_ICR1_CH7_HL_AH (0x1<<1) // Active high | |
| 183 #define ICTL_ICR1_CH8 (0x1<<2) | |
| 184 #define ICTL_ICR1_CH8_HL (0x1<<2) | |
| 185 #define ICTL_ICR1_CH8_HL_AL (0x0<<2) // Active low | |
| 186 #define ICTL_ICR1_CH8_HL_AH (0x1<<2) // Active high | |
| 187 | |
| 188 // Clock control registers | |
| 189 #define PCSR_CT0CS (1<<3) | |
| 190 #define PCSR_CT1CS (1<<4) | |
| 191 #define PCSR_CT2CS (1<<5) | |
| 192 #define CT_X16 16 | |
| 193 | |
| 194 #undef _TIMERS_TESTING | |
| 195 #ifdef _TIMERS_TESTING | |
| 196 static void aeb_setup_timer1(cyg_uint32 period); | |
| 197 #endif | |
| 198 | |
| 199 static cyg_uint32 _period; | |
| 200 | |
| 201 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 202 static cyg_interrupt abort_interrupt; | |
| 203 static cyg_handle_t abort_interrupt_handle; | |
| 204 | |
| 205 // This ISR is called only for the Abort button interrupt | |
| 206 static int | |
| 207 aeb_abort_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) | |
| 208 { | |
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209 cyg_hal_user_break((CYG_ADDRWORD*)regs); |
| 2 | 210 cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT0); |
| 211 return 0; // No need to run DSR | |
| 212 } | |
| 213 #endif | |
| 214 | |
| 215 void hal_clock_initialize(cyg_uint32 period) | |
| 216 { | |
| 217 cyg_uint32 iocr; | |
| 218 | |
| 219 // Set counter GATE input low (0) to halt counter while it's being setup | |
| 220 HAL_READ_UINT32(CYG_DEVICE_IOCR, iocr); | |
| 221 iocr = (iocr & ~IOCR_CT0G) | IOCR_CT0G_LOW; | |
| 222 HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr); | |
| 223 | |
| 224 // Scale timer0 clock | |
| 225 HAL_WRITE_UINT32(CYG_DEVICE_CPM_CT0CCR, CT_X16); | |
| 226 | |
| 227 // Initialize counter, mode 2 = rate generator | |
| 228 HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL, | |
| 229 TIMER_CTL_TYPE_BIN| | |
| 230 TIMER_CTL_MODE_RG| | |
| 231 TIMER_CTL_RW_BOTH| | |
| 232 TIMER_CTL_SC_CTR0); | |
| 233 HAL_WRITE_UINT8(CYG_DEVICE_TIMER0, (period & 0xFF)); // LSB | |
| 234 HAL_WRITE_UINT8(CYG_DEVICE_TIMER0, ((period >> 8) & 0xFF)); // MSB | |
| 235 // Enable timer | |
| 236 iocr = (iocr & ~IOCR_CT0G) | IOCR_CT0G_HIGH; | |
| 237 HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr); | |
| 238 _period = period; | |
| 239 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 240 cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0, | |
| 241 99, // Priority | |
| 242 0, // Data item passed to interrupt handler | |
| 243 aeb_abort_isr, | |
| 244 0, | |
| 245 &abort_interrupt_handle, | |
| 246 &abort_interrupt); | |
| 247 cyg_drv_interrupt_attach(abort_interrupt_handle); | |
| 248 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0); | |
| 249 #endif | |
| 250 #ifdef _TIMERS_TESTING | |
| 251 aeb_setup_timer1(period/10); | |
| 252 #endif | |
| 253 } | |
| 254 | |
| 255 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) | |
| 256 { | |
| 257 _period = period; | |
| 258 } | |
| 259 | |
| 260 void hal_clock_read(cyg_uint32 *pvalue) | |
| 261 { | |
| 262 cyg_uint32 value; | |
| 263 cyg_uint8 reg; | |
| 264 do { | |
| 265 HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL, | |
| 266 TIMER_CTL_RW_LATCH|TIMER_CTL_SC_CTR0); | |
| 267 HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // LSB | |
| 268 value = reg; | |
| 269 HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // MSB | |
| 270 value |= (reg << 8); | |
| 271 } while (value <= 2); // Hardware malfunction? | |
| 272 *pvalue = _period - (value & 0xFFFF); // Note: counter is only 16 bits | |
| 273 // and decreases | |
| 274 } | |
| 275 | |
| 276 void hal_hardware_init(void) | |
| 277 { | |
| 278 // Any hardware/platform initialization that needs to be done. | |
| 279 // Set all unknowns as edge triggered | |
| 280 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR0, | |
| 281 ICTL_ICR0_CH0_HL_AL|ICTL_ICR0_CH0_EL_ET| | |
| 282 ICTL_ICR0_CH1_HL_AL|ICTL_ICR0_CH1_EL_ET| | |
| 283 ICTL_ICR0_CH2_HL_AL|ICTL_ICR0_CH2_EL_ET| | |
| 284 ICTL_ICR0_CH3_HL_AL|ICTL_ICR0_CH3_EL_ET| | |
| 285 ICTL_ICR0_CH4_HL_AL|ICTL_ICR0_CH4_EL_ET| | |
| 286 ICTL_ICR0_CH5_HL_AL|ICTL_ICR0_CH5_EL_ET); | |
| 287 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR1, | |
| 288 ICTL_ICR1_CH6_HL_AL| | |
| 289 ICTL_ICR1_CH7_HL_AL| | |
| 290 ICTL_ICR1_CH8_HL_AL); | |
| 291 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, 0xFFFF); // CLear all interrupts | |
| 292 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, 0x0000); // All disabled | |
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293 // Clear and initialize cache |
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294 HAL_UCACHE_INVALIDATE_ALL(); |
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295 HAL_UCACHE_ENABLE(); |
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296 |
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297 // Set up eCos/ROM interfaces |
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298 hal_if_init(); |
| 2 | 299 } |
| 300 | |
| 301 // | |
| 302 // This routine is called to respond to a hardware interrupt (IRQ). It | |
| 303 // should interrogate the hardware and return the IRQ vector number. | |
| 304 | |
| 305 int hal_IRQ_handler(void) | |
| 306 { | |
| 307 // Do hardware-level IRQ handling | |
| 308 int irq_status, vector; | |
| 309 HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQSR, irq_status); | |
| 310 for (vector = 0; vector < 16; vector++) { | |
| 311 if (irq_status & (1<<vector)) return vector; | |
| 312 } | |
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313 return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen! |
| 2 | 314 } |
| 315 | |
| 316 // | |
| 317 // Interrupt control | |
| 318 // | |
| 319 | |
| 320 void hal_interrupt_mask(int vector) | |
| 321 { | |
| 322 cyg_uint32 mask, old_mask; | |
| 323 HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, mask); | |
| 324 old_mask = mask; | |
| 325 mask &= ~(1<<vector); | |
| 326 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, mask); | |
| 327 } | |
| 328 | |
| 329 #if 0 | |
| 330 void hal_interrupt_status(void) | |
| 331 { | |
| 332 int irq_status, irq_enable, ipr_value, timer_value; | |
| 333 cyg_uint8 reg; | |
| 334 HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // LSB | |
| 335 timer_value = reg; | |
| 336 HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // MSB | |
| 337 timer_value |= (reg << 8); | |
| 338 HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQSR, irq_status); | |
| 339 HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, irq_enable); | |
| 340 HAL_READ_UINT32(CYG_DEVICE_ICTL_IPR, ipr_value); | |
| 341 diag_printf("Interrupt: IRQ: %x.%x.%x, Timer: %x\n", irq_status, | |
| 342 irq_enable, ipr_value, timer_value); | |
| 343 } | |
| 344 #endif | |
| 345 | |
| 346 void hal_interrupt_unmask(int vector) | |
| 347 { | |
| 348 cyg_uint32 mask, old_mask; | |
| 349 HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, mask); | |
| 350 old_mask = mask; | |
| 351 mask |= (1<<vector); | |
| 352 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, mask); | |
| 353 } | |
| 354 | |
| 355 void hal_interrupt_acknowledge(int vector) | |
| 356 { | |
| 357 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, (1<<vector)); | |
| 358 } | |
| 359 | |
| 360 void hal_interrupt_configure(int vector, int level, int up) | |
| 361 { | |
| 362 // diag_printf("%s(%d,%d,%d)\n", __PRETTY_FUNCTION__, vector, level, up); | |
| 363 } | |
| 364 | |
| 365 void hal_interrupt_set_level(int vector, int level) | |
| 366 { | |
| 367 // diag_printf("%s(%d,%d)\n", __PRETTY_FUNCTION__, vector, level); | |
| 368 } | |
| 369 | |
| 370 void hal_show_IRQ(int vector, int data, int handler) | |
| 371 { | |
| 372 // diag_printf("IRQ - vector: %x, data: %x, handler: %x\n", vector, | |
| 373 // data, handler); | |
| 374 } | |
| 375 | |
| 376 #ifdef _TIMERS_TESTING | |
| 377 #include <cyg/hal/drv_api.h> // HAL ISR support | |
| 378 static cyg_interrupt timer1_interrupt; | |
| 379 static cyg_handle_t timer1_interrupt_handle; | |
| 380 static cyg_uint32 timer1_count; | |
| 381 | |
| 382 // This ISR is called only for the high speed timer under test | |
| 383 static int | |
| 384 aeb_timer1_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) | |
| 385 { | |
| 386 cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_TIMER1); | |
| 387 timer1_count++; | |
| 388 return 0; // No need to run DSR | |
| 389 } | |
| 390 | |
| 391 static void | |
| 392 aeb_setup_timer1(cyg_uint32 period) | |
| 393 { | |
| 394 cyg_uint32 iocr; | |
| 395 | |
| 396 // Set counter GATE input low (0) to halt counter while it's being setup | |
| 397 HAL_READ_UINT32(CYG_DEVICE_IOCR, iocr); | |
| 398 iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_LOW; | |
| 399 HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr); | |
| 400 | |
| 401 // Scale timer0 clock | |
| 402 HAL_WRITE_UINT32(CYG_DEVICE_CPM_CT1CCR, CT_X16); | |
| 403 | |
| 404 // Initialize counter, mode 2 = rate generator | |
| 405 HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL, | |
| 406 TIMER_CTL_TYPE_BIN| | |
| 407 TIMER_CTL_MODE_RG| | |
| 408 TIMER_CTL_RW_BOTH| | |
| 409 TIMER_CTL_SC_CTR1); | |
| 410 HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, (period & 0xFF)); // LSB | |
| 411 HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, ((period >> 8) & 0xFF)); // MSB | |
| 412 // Enable timer | |
| 413 iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_HIGH; | |
| 414 HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr); | |
| 415 cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_TIMER1, | |
| 416 99, // Priority | |
| 417 0, // Data item passed to interrupt handler | |
| 418 aeb_timer1_isr, | |
| 419 0, | |
| 420 &timer1_interrupt_handle, | |
| 421 &timer1_interrupt); | |
| 422 cyg_drv_interrupt_attach(timer1_interrupt_handle); | |
| 423 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TIMER1); | |
| 424 } | |
| 425 #endif | |
| 426 | |
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427 //----------------------------------------------------------------------------- |
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428 // Reset board (definitions from watchdog file aeb1.cxx) |
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429 |
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430 // Register definitions |
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431 #define CYGARC_REG_WATCHDOG_BASE 0xFFFFAC00 |
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432 #define CYGARC_REG_WATCHDOG_WDCTLR (CYGARC_REG_WATCHDOG_BASE+0x30) |
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433 #define CYGARC_REG_WATCHDOG_WDCNTR (CYGARC_REG_WATCHDOG_BASE+0x34) |
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434 |
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435 // Control register bits |
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436 #define CYGARC_REG_WATCHDOG_WDCTLR_EN 0x01 // enable |
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437 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_NMF 0x00 // non-maskable fiq |
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438 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_ER 0x04 // external reset |
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439 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR 0x06 // system reset |
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440 #define CYGARC_REG_WATCHDOG_WDCTLR_FRZ 0x08 // lock enable bit |
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441 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_MASK 0x70 // time out period |
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442 |
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443 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_17 0x00 // 2^17 |
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444 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_17_P 5242880 // = 5.2ms |
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445 |
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446 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_25 0x40 // 2^25 |
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447 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_25_P 1342177300 // = 1.3421773s |
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448 |
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449 void |
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450 hal_aeb_reset(void) |
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451 { |
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452 // Clear the watchdog counter. |
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453 HAL_WRITE_UINT32(CYGARC_REG_WATCHDOG_WDCNTR, 0); |
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454 |
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455 // Enable the watchdog with the smallest timeout. |
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456 HAL_WRITE_UINT8(CYGARC_REG_WATCHDOG_WDCTLR, |
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457 (CYGARC_REG_WATCHDOG_WDCTLR_TOP_17 |
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458 | CYGARC_REG_WATCHDOG_WDCTLR_FRZ |
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459 | CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR |
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460 | CYGARC_REG_WATCHDOG_WDCTLR_EN)); |
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461 |
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462 // Wait for it... |
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463 for(;;); |
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464 } |
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465 |
| 2 | 466 /*------------------------------------------------------------------------*/ |
| 467 // EOF hal_misc.c |