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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 74dbf4c3f2e1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #ifndef CYGONCE_HAL_ARCH_H
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2 #define CYGONCE_HAL_ARCH_H
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3
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4 //==========================================================================
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5 //
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6 // hal_arch.h
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7 //
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8 // Architecture specific abstractions
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9 //
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10 //==========================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //==========================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg, gthomas
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46 // Contributors: nickg, gthomas
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47 // Date: 2001-09-07
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48 // Purpose: Define architecture abstractions
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49 // Usage: #include <cyg/hal/hal_arch.h>
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50
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51 //
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52 //####DESCRIPTIONEND####
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53 //
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54 //==========================================================================
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55
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56 #include <pkgconf/hal.h> // To decide on stack usage
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57 #include <cyg/infra/cyg_type.h>
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58
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59 #if CYGINT_HAL_FRV_ARCH_FR500 != 0
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60 #define _NGPR 64
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61 #define _NFPR 64
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62 #elif CYGINT_HAL_FRV_ARCH_FR400 != 0
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63 #define _NGPR 32
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64 #define _NFPR 32
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65 #else
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66 #error No architecture defined?
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67 #endif
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68
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69 //--------------------------------------------------------------------------
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70 // Common "special" register definitions
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71
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72 // Processor status register
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73 #define _PSR_PIVL_SHIFT 3
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74 #define _PSR_PIVL_MASK (0xF<<(_PSR_PIVL_SHIFT)) // Interrupt mask level
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75 #define _PSR_S (1<<2) // Supervisor state
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76 #define _PSR_PS (1<<1) // Previous supervisor state
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77 #define _PSR_ET (1<<0) // Enable interrupts
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78 #define _PSR_CM (1<<13) // Enable conditionals
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79
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80 #define _PSR_INITIAL (_PSR_S|_PSR_PS|_PSR_ET|_PSR_CM) // Supervisor mode, exceptions
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81
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82 // Hardware status register
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83 #define _HSR0_FRN (1<<11)
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84 #define _HSR0_GRN (1<<10)
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85 #define _HSR0_ICE (1<<31) // Instruction cache enable
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86 #define _HSR0_DCE (1<<30) // Data cache enable
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87 #define _HSR0_IMMU (1<<26) // Instruction MMU enable
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88 #define _HSR0_DMMU (1<<25) // Data MMU enable
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89
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90 // Debug Control Register
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91 #define _DCR_EBE (1 << 30)
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92 #define _DCR_SE (1 << 29)
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93 #define _DCR_DRBE0 (1 << 19)
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94 #define _DCR_DWBE0 (1 << 18)
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95 #define _DCR_DDBE0 (1 << 17)
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96 #define _DCR_DRBE1 (1 << 16)
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97 #define _DCR_DWBE1 (1 << 15)
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98 #define _DCR_DDBE1 (1 << 14)
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99 #define _DCR_DRBE2 (1 << 13)
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100 #define _DCR_DWBE2 (1 << 12)
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101 #define _DCR_DDBE2 (1 << 11)
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102 #define _DCR_DRBE3 (1 << 10)
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103 #define _DCR_DWBE3 (1 << 9)
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104 #define _DCR_DDBE3 (1 << 8)
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105 #define _DCR_IBE0 (1 << 7)
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106 #define _DCR_IBCE0 (1 << 6)
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107 #define _DCR_IBE1 (1 << 5)
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108 #define _DCR_IBCE1 (1 << 4)
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109 #define _DCR_IBE2 (1 << 3)
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110 #define _DCR_IBCE2 (1 << 2)
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111 #define _DCR_IBE3 (1 << 1)
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112 #define _DCR_IBCE3 (1 << 0)
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113
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114 // Initial contents for special registers
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115
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116 #define _CCR_INITIAL 0
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117 #define _LCR_INITIAL 0
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118 #define _CCCR_INITIAL 0
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119
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120 //--------------------------------------------------------------------------
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121 //
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122 // Saved thread state
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123 //
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124 typedef struct
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125 {
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126 cyg_uint32 gpr[_NGPR]; // Saved general purpose registers
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127 cyg_uint32 pc; // Current [next] instruction location
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128 cyg_uint32 psr; // Processor status register
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129 cyg_uint32 lr; // Link register
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130 cyg_uint32 ccr; // Condition codes
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131 cyg_uint32 cccr;
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132 cyg_uint32 lcr;
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133 cyg_int32 vector; // Reason for last exception
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134 } HAL_SavedRegisters;
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135
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136 //-------------------------------------------------------------------------
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137 // Exception handling function.
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138 // This function is defined by the kernel according to this prototype. It is
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139 // invoked from the HAL to deal with any CPU exceptions that the HAL does
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140 // not want to deal with itself. It usually invokes the kernel's exception
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141 // delivery mechanism.
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142
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143 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
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144
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145 //-------------------------------------------------------------------------
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146 // Bit manipulation macros
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147
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148 externC int hal_lsbindex(int);
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149 externC int hal_msbindex(int);
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150
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151 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbindex(mask)
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152 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbindex(mask)
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153
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154 //-------------------------------------------------------------------------
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155 // Context Initialization
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156 // Initialize the context of a thread.
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157 // Arguments:
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158 // _sparg_ name of variable containing current sp, will be changed to new sp
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159 // _thread_ thread object address, passed as argument to entry point
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160 // _entry_ entry point address.
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161 // _id_ bit pattern used in initializing registers, for debugging.
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162
1746
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163 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
208
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164 CYG_MACRO_START \
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165 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_) &~15; \
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166 register HAL_SavedRegisters *_regs_; \
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167 int _i_; \
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168 _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \
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169 for( _i_ = 1; _i_ < _NGPR; _i_++) \
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170 (_regs_)->gpr[_i_] = (_id_)|_i_; \
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171 (_regs_)->gpr[8] = (CYG_WORD)(_thread_); /* R8 = arg1 = thread ptr */ \
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172 (_regs_)->gpr[1] = (CYG_WORD)(_sp_); /* SP = top of stack */ \
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173 (_regs_)->lr = (CYG_WORD)(_entry_); /* LR = entry point */ \
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174 (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = [initial] entry point */ \
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175 (_regs_)->psr = _PSR_INITIAL; /* PSR = Interrupt enabled */ \
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176 (_regs_)->ccr = _CCR_INITIAL; \
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177 (_regs_)->lcr = _LCR_INITIAL; \
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178 (_regs_)->ccr = _CCCR_INITIAL; \
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179 _sparg_ = (CYG_ADDRESS)_regs_; \
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180 CYG_MACRO_END
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181
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182 //--------------------------------------------------------------------------
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183 // Context switch macros.
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184 // The arguments are pointers to locations where the stack pointer
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185 // of the current thread is to be stored, and from where the sp of the
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186 // next thread is to be fetched.
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187
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188 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
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189 externC void hal_thread_load_context( CYG_ADDRESS to )
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190 __attribute__ ((noreturn));
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191
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192 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
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193 hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \
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194 (CYG_ADDRESS)_fspptr_);
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195
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196 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
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197 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
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198
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199 //--------------------------------------------------------------------------
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200 // Execution reorder barrier.
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201 // When optimizing the compiler can reorder code. In multithreaded systems
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202 // where the order of actions is vital, this can sometimes cause problems.
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203 // This macro may be inserted into places where reordering should not happen.
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204
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205 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
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206
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207 //--------------------------------------------------------------------------
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208 // Breakpoint support
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209 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
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210 // if executed.
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211 // HAL_BREAKINST is the value of the breakpoint instruction and
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212 // HAL_BREAKINST_SIZE is its size in bytes.
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213
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214 // The choices for breakpoints seem to be:
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215 // break 0x801000C0
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216 // tira gr0,#1 0xC0700001
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217 #ifdef CYGSEM_HAL_FRV_USE_BREAK_INSTRUCTION
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218 #define HAL_BREAKPOINT(_label_) \
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219 asm volatile (" .globl " #_label_ "\n" \
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220 #_label_":\tbreak\n" \
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221 );
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222
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223 #define HAL_BREAKINST 0x801000C0
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224 #else
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225 #define HAL_BREAKPOINT(_label_) \
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226 asm volatile (" .globl " #_label_ "\n" \
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227 #_label_":\ttira\tgr0,#1\n" \
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228 );
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229
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230 #define HAL_BREAKINST 0xC0700001
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231 #endif
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232 #define HAL_BREAKINST_SIZE 4
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233 #define HAL_BREAKINST_TYPE cyg_uint32
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234
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235 //--------------------------------------------------------------------------
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236 // Thread register state manipulation for GDB support.
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237
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238 // GDB expects the registers in this structure:
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239 // gr0..gr31, gr32..gr63 - 4 bytes each
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240 // fpr0..fpr31, fpr32..fpr63 - 4 bytes each
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241 // pc, psr, ccr, cccr - 4 bytes each
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242 // 14 <unused> - 4 bytes each
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243 // lr, lcr - 4 bytes each
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244
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245 // Translate a stack pointer as saved by the thread context macros above into
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246 // a pointer to a HAL_SavedRegisters structure.
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247 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
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248 (_regs_) = (HAL_SavedRegisters *)(_sp_)
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249
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250 // Copy a set of registers from a HAL_SavedRegisters structure into a
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251 // GDB ordered array.
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252 #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
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253 CYG_MACRO_START \
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254 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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255 int _i_; \
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256 \
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257 for( _i_ = 0; _i_ <= _NGPR; _i_++ ) \
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258 _regval_[_i_] = (_regs_)->gpr[_i_]; \
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259 _regval_[128] = (_regs_)->pc; \
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260 _regval_[129] = (_regs_)->psr; \
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261 _regval_[130] = (_regs_)->ccr; \
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262 _regval_[135] = (_regs_)->vector; \
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263 _regval_[145] = (_regs_)->lr; \
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264 _regval_[146] = (_regs_)->lcr; \
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265 CYG_MACRO_END
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266
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267 // Copy a GDB ordered array into a HAL_SavedRegisters structure.
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268 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
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269 CYG_MACRO_START \
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270 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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271 int _i_; \
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272 \
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273 for( _i_ = 0; _i_ <= _NGPR; _i_++ ) \
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274 (_regs_)->gpr[_i_] = _regval_[_i_]; \
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275 \
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276 (_regs_)->pc = _regval_[128]; \
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277 (_regs_)->psr = _regval_[129]; \
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278 (_regs_)->ccr = _regval_[130]; \
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279 (_regs_)->lr = _regval_[145]; \
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280 (_regs_)->lcr = _regval_[146]; \
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281 CYG_MACRO_END
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282
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283 //--------------------------------------------------------------------------
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284 // HAL setjmp
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285
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286 #define CYGARC_JMP_BUF_SIZE 0x110
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287
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288 typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
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289
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290 externC int hal_setjmp(hal_jmp_buf env);
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291 externC void hal_longjmp(hal_jmp_buf env, int val);
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292
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293 //--------------------------------------------------------------------------
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294 // Idle thread code.
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295 // This macro is called in the idle thread loop, and gives the HAL the
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296 // chance to insert code. Typical idle thread behaviour might be to halt the
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297 // processor.
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298
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299 externC void hal_idle_thread_action(cyg_uint32 loop_count);
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300
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301 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
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302
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303 //---------------------------------------------------------------------------
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304
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305 // Minimal and sensible stack sizes: the intention is that applications
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306 // will use these to provide a stack size in the first instance prior to
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307 // proper analysis. Idle thread stack should be this big.
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308
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309 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
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310 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
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311 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
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312
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313 // This is not a config option because it should not be adjusted except
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314 // under "enough rope" sort of disclaimers.
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315
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316 // A minimal, optimized stack frame, rounded up - no autos
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317 #define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 150)
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318
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319 // Stack needed for a context switch: this is implicit in the estimate for
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320 // interrupts so not explicitly used below:
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321 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 150)
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322
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323 // Interrupt + call to ISR, interrupt_end() and the DSR
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324 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
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325 ((4 * 150) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
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326
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327 // Space for the maximum number of nested interrupts, plus room to call functions
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328 #define CYGNUM_HAL_MAX_INTERRUPT_NESTING 4
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329
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330 #define CYGNUM_HAL_STACK_SIZE_MINIMUM \
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331 (CYGNUM_HAL_MAX_INTERRUPT_NESTING * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \
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332 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
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333
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334 #define CYGNUM_HAL_STACK_SIZE_TYPICAL \
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335 (CYGNUM_HAL_STACK_SIZE_MINIMUM + \
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336 16 * CYGNUM_HAL_STACK_FRAME_SIZE)
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337
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338
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339 //--------------------------------------------------------------------------
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340 // Macros for switching context between two eCos instances (jump from
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341 // code in ROM to code in RAM or vice versa).
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342 #define CYGARC_HAL_SAVE_GP()
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343 #define CYGARC_HAL_RESTORE_GP()
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344
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345 #endif // CYGONCE_HAL_ARCH_H
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346 // End of hal_arch.h