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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 74dbf4c3f2e1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 // #===========================================================================
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2 // #
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3 // # context.S
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4 // #
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5 // # FUJITSU context switch code
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6 // #
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7 // #===========================================================================
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8 // ####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later
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16 // version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License
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24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 //
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27 // As a special exception, if other files instantiate templates or use
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28 // macros or inline functions from this file, or you compile this file
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29 // and link it with other works to produce a work based on this file,
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30 // this file does not by itself cause the resulting work to be covered by
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31 // the GNU General Public License. However the source code for this file
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32 // must still be made available in accordance with section (3) of the GNU
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33 // General Public License v2.
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34 //
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35 // This exception does not invalidate any other reasons why a work based
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36 // on this file might be covered by the GNU General Public License.
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37 // -------------------------------------------
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38 // ####ECOSGPLCOPYRIGHTEND####
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39 // #===========================================================================
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40 // ######DESCRIPTIONBEGIN####
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41 // #
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42 // # Author(s): nickg, gthomas
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43 // # Contributors: nickg, gthomas
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44 // # Date: 1998-09-15
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45 // # Purpose: FUJITSU context switch code
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46 // # Description: This file contains implementations of the thread context
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47 // # switch routines. It also contains the longjmp() and setjmp()
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48 // # routines.
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49 // #
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50 // #####DESCRIPTIONEND####
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51 // #
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52 // #===========================================================================
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53
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54 #include <pkgconf/hal.h>
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55
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56 #include "frv.inc"
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57
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58 .text
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59
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60 // ----------------------------------------------------------------------------
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61 // hal_thread_switch_context(new, old)
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62 // Switch thread contexts
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63 // new = address of context of next thread to execute
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64 // old = address of context save location of current thread
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65 // thread state is saved on the current stack
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66
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67 .globl hal_thread_switch_context
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68 hal_thread_switch_context:
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69 subi sp,_TS_size,sp // Space for saved frame
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70 sti gr2,@(sp,_TS_GPR2) // Save registers
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71 sti gr3,@(sp,_TS_GPR3)
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72 sti gr4,@(sp,_TS_GPR4)
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73 sti gr5,@(sp,_TS_GPR5)
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74 sti gr6,@(sp,_TS_GPR6)
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75 sti gr7,@(sp,_TS_GPR7)
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76 sti gr8,@(sp,_TS_GPR8)
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77 sti gr9,@(sp,_TS_GPR9)
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78 sti gr10,@(sp,_TS_GPR10)
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79 sti gr11,@(sp,_TS_GPR11)
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80 sti gr12,@(sp,_TS_GPR12)
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81 sti gr13,@(sp,_TS_GPR13)
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82 sti gr14,@(sp,_TS_GPR14)
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83 sti gr15,@(sp,_TS_GPR15)
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84 sti gr16,@(sp,_TS_GPR16)
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85 sti gr17,@(sp,_TS_GPR17)
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86 sti gr18,@(sp,_TS_GPR18)
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87 sti gr19,@(sp,_TS_GPR19)
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88 sti gr20,@(sp,_TS_GPR20)
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89 sti gr21,@(sp,_TS_GPR21)
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95 sti gr27,@(sp,_TS_GPR27)
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98 sti gr30,@(sp,_TS_GPR30)
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99 sti gr31,@(sp,_TS_GPR31)
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100 #if _NGPR != 32
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101 #ifdef CYGINT_HAL_FRV_ARCH_FR400
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102 movsg HSR0,gr5
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103 srli gr5,#10,gr5
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104 andicc gr5,#1,gr0,icc0
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105 bne icc0,0,1f
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106 #endif
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133 sti gr58,@(sp,_TS_GPR58)
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134 sti gr59,@(sp,_TS_GPR59)
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135 sti gr60,@(sp,_TS_GPR60)
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136 sti gr61,@(sp,_TS_GPR61)
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137 sti gr62,@(sp,_TS_GPR62)
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138 sti gr63,@(sp,_TS_GPR63)
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139 1:
208
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140 #endif
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141 movsg psr,gr4
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142 sti gr4,@(sp,_TS_PSR)
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143 movsg lr,gr4
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144 sti gr4,@(sp,_TS_PC)
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145 movsg ccr,gr4
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146 sti gr4,@(sp,_TS_CCR)
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147 movsg lcr,gr4
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148 sti gr4,@(sp,_TS_LCR)
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149 movsg cccr,gr4
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150 sti gr4,@(sp,_TS_CCCR)
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151 addi sp,_TS_size,gr4
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152 sti gr4,@(sp,_TS_SP)
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153 sti sp,@(gr9,0) // Pointer to saved context
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154
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155 # Now load the destination thread by dropping through
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156 # to hal_thread_load_context
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157
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158 // ----------------------------------------------------------------------------
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159 // hal_thread_load_context(new)
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160 // Load thread context
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161 // new = address of context of next thread to execute
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162 // Note that this function is also the second half of
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163 // hal_thread_switch_context and is simply dropped into from it.
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164
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165 .globl hal_thread_load_context
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166 hal_thread_load_context:
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167 ldi @(gr8,0),sp // Saved context
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168 ldi @(sp,_TS_PSR),gr8
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169 setlos #~_PSR_ET,gr9 // Turn off exceptions
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170 and gr8,gr9,gr8
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171 setlos #_PSR_PS|_PSR_S,gr9 // Stay in supervisor mode
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172 or gr8,gr9,gr8
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173 movgs gr8,psr
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174 ldi @(sp,_TS_PC),gr8
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175 movgs gr8,pcsr
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176 ldi @(sp,_TS_CCR),gr8
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177 movgs gr8,ccr
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178 ldi @(sp,_TS_LCR),gr8
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179 movgs gr8,lcr
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180 ldi @(sp,_TS_CCCR),gr8
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181 movgs gr8,cccr
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182 #if _NGPR != 32
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183 #ifdef CYGINT_HAL_FRV_ARCH_FR400
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184 movsg HSR0,gr5
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185 srli gr5,#10,gr5
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186 andicc gr5,#1,gr0,icc0
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187 bne icc0,0,1f
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188 #endif
208
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189 ldi @(sp,_TS_GPR32),gr32
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190 ldi @(sp,_TS_GPR33),gr33
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191 ldi @(sp,_TS_GPR34),gr34
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192 ldi @(sp,_TS_GPR35),gr35
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193 ldi @(sp,_TS_GPR36),gr36
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194 ldi @(sp,_TS_GPR37),gr37
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195 ldi @(sp,_TS_GPR38),gr38
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196 ldi @(sp,_TS_GPR39),gr39
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197 ldi @(sp,_TS_GPR40),gr40
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198 ldi @(sp,_TS_GPR41),gr41
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199 ldi @(sp,_TS_GPR42),gr42
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200 ldi @(sp,_TS_GPR43),gr43
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201 ldi @(sp,_TS_GPR44),gr44
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202 ldi @(sp,_TS_GPR45),gr45
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203 ldi @(sp,_TS_GPR46),gr46
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204 ldi @(sp,_TS_GPR47),gr47
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205 ldi @(sp,_TS_GPR48),gr48
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206 ldi @(sp,_TS_GPR49),gr49
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207 ldi @(sp,_TS_GPR50),gr50
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208 ldi @(sp,_TS_GPR51),gr51
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209 ldi @(sp,_TS_GPR52),gr52
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210 ldi @(sp,_TS_GPR53),gr53
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211 ldi @(sp,_TS_GPR54),gr54
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212 ldi @(sp,_TS_GPR55),gr55
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213 ldi @(sp,_TS_GPR56),gr56
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214 ldi @(sp,_TS_GPR57),gr57
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215 ldi @(sp,_TS_GPR58),gr58
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216 ldi @(sp,_TS_GPR59),gr59
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217 ldi @(sp,_TS_GPR60),gr60
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218 ldi @(sp,_TS_GPR61),gr61
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219 ldi @(sp,_TS_GPR62),gr62
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220 ldi @(sp,_TS_GPR63),gr63
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221 1:
208
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222 #endif
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223 ldi @(sp,_TS_GPR2),gr2 // Restore registers
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224 ldi @(sp,_TS_GPR3),gr3
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225 ldi @(sp,_TS_GPR4),gr4
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226 ldi @(sp,_TS_GPR5),gr5
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227 ldi @(sp,_TS_GPR6),gr6
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228 ldi @(sp,_TS_GPR7),gr7
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229 ldi @(sp,_TS_GPR8),gr8
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230 ldi @(sp,_TS_GPR9),gr9
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231 ldi @(sp,_TS_GPR10),gr10
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232 ldi @(sp,_TS_GPR11),gr11
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233 ldi @(sp,_TS_GPR12),gr12
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234 ldi @(sp,_TS_GPR13),gr13
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235 ldi @(sp,_TS_GPR14),gr14
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236 ldi @(sp,_TS_GPR15),gr15
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237 ldi @(sp,_TS_GPR16),gr16
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238 ldi @(sp,_TS_GPR17),gr17
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239 ldi @(sp,_TS_GPR18),gr18
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240 ldi @(sp,_TS_GPR19),gr19
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241 ldi @(sp,_TS_GPR20),gr20
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242 ldi @(sp,_TS_GPR21),gr21
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243 ldi @(sp,_TS_GPR22),gr22
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244 ldi @(sp,_TS_GPR23),gr23
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245 ldi @(sp,_TS_GPR24),gr24
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246 ldi @(sp,_TS_GPR25),gr25
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247 ldi @(sp,_TS_GPR26),gr26
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248 ldi @(sp,_TS_GPR27),gr27
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249 ldi @(sp,_TS_GPR28),gr28
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250 ldi @(sp,_TS_GPR29),gr29
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251 ldi @(sp,_TS_GPR30),gr30
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252 ldi @(sp,_TS_GPR31),gr31
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253 ldi @(sp,_TS_SP),sp
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254 rett #0
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255
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256 // ----------------------------------------------------------------------------
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257 // HAL longjmp, setjmp implementations - based on newlib
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258 // Register jmpbuf offset
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259 // R16-R31 0x0-0x03c
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260 // R48-R63 0x40-0x7c
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261 // FR16-FR31 0x80-0xbc
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262 // FR48-FR63 0xc0-0xfc
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263 // LR 0x100
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264 // SP 0x104
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265 // FP 0x108
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266 //
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267 // R8 contains the pointer to jmpbuf
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268
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269 .text
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270 .global hal_setjmp
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271 .type hal_setjmp,@function
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272 hal_setjmp:
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273 stdi gr16, @(gr8,0)
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274 stdi gr18, @(gr8,8)
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jlarmour
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diff changeset
275 stdi gr20, @(gr8,16)
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jlarmour
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diff changeset
276 stdi gr22, @(gr8,24)
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jlarmour
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diff changeset
277 stdi gr24, @(gr8,32)
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jlarmour
parents:
diff changeset
278 stdi gr26, @(gr8,40)
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jlarmour
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diff changeset
279 stdi gr28, @(gr8,48)
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diff changeset
280 stdi gr30, @(gr8,56)
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diff changeset
281 #if _NGPR != 32
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diff changeset
282 #ifdef CYGINT_HAL_FRV_ARCH_FR400
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diff changeset
283 movsg HSR0,gr5
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diff changeset
284 srli gr5,#10,gr5
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diff changeset
285 andicc gr5,#1,gr0,icc0
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diff changeset
286 bne icc0,0,1f
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parents: 210
diff changeset
287 #endif
208
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diff changeset
288 stdi gr48, @(gr8,64)
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diff changeset
289 stdi gr50, @(gr8,72)
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diff changeset
290 stdi gr52, @(gr8,80)
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diff changeset
291 stdi gr54, @(gr8,88)
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diff changeset
292 stdi gr56, @(gr8,96)
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diff changeset
293 stdi gr58, @(gr8,104)
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diff changeset
294 stdi gr60, @(gr8,112)
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diff changeset
295 stdi gr62, @(gr8,120)
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diff changeset
296 1:
208
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297 #endif
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298
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299 #if _NFPR != 0
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diff changeset
300 stdfi fr16, @(gr8,128)
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jlarmour
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diff changeset
301 stdfi fr18, @(gr8,136)
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jlarmour
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diff changeset
302 stdfi fr20, @(gr8,144)
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jlarmour
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diff changeset
303 stdfi fr22, @(gr8,152)
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jlarmour
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diff changeset
304 stdfi fr24, @(gr8,160)
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jlarmour
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diff changeset
305 stdfi fr26, @(gr8,168)
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diff changeset
306 stdfi fr28, @(gr8,176)
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diff changeset
307 stdfi fr30, @(gr8,184)
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308 #if _NFPR != 32
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309 #ifdef CYGINT_HAL_FRV_ARCH_FR400
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310 movsg HSR0,gr5
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311 srli gr5,#11,gr5
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312 andicc gr5,#1,gr0,icc0
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313 bne icc0,0,1f
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diff changeset
314 #endif
208
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315 stdfi fr48, @(gr8,192)
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316 stdfi fr50, @(gr8,200)
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diff changeset
317 stdfi fr52, @(gr8,208)
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318 stdfi fr54, @(gr8,216)
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319 stdfi fr56, @(gr8,224)
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320 stdfi fr58, @(gr8,232)
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321 stdfi fr60, @(gr8,240)
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322 stdfi fr62, @(gr8,248)
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diff changeset
323 1:
208
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324 #endif
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325 #endif
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326
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327 movsg lr, gr4
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328 sti gr4, @(gr8,256)
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diff changeset
329 sti sp, @(gr8,260)
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330 sti fp, @(gr8,264)
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331
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332 mov gr0,gr8
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333 ret
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334 .Lend1:
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335 .size hal_setjmp,.Lend1-hal_setjmp
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336
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337 .global hal_longjmp
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338 .type hal_longjmp,@function
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339 hal_longjmp:
208
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340 #if _NFPR != 0
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341 lddfi @(gr8,128), fr16
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diff changeset
342 lddfi @(gr8,136), fr18
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343 lddfi @(gr8,144), fr20
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344 lddfi @(gr8,152), fr22
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345 lddfi @(gr8,160), fr24
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346 lddfi @(gr8,168), fr26
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347 lddfi @(gr8,176), fr28
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348 lddfi @(gr8,184), fr30
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349 #if _NFPR != 32
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350 #ifdef CYGINT_HAL_FRV_ARCH_FR400
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351 movsg HSR0,gr5
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352 srli gr5,#11,gr5
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diff changeset
353 andicc gr5,#1,gr0,icc0
f8c5906d7c6e Add FR-V ports for MB9309x boards.
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diff changeset
354 bne icc0,0,1f
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msalter
parents: 210
diff changeset
355 #endif
208
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jlarmour
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diff changeset
356 lddfi @(gr8,192), fr48
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jlarmour
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diff changeset
357 lddfi @(gr8,200), fr50
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jlarmour
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diff changeset
358 lddfi @(gr8,208), fr52
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jlarmour
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diff changeset
359 lddfi @(gr8,216), fr54
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jlarmour
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diff changeset
360 lddfi @(gr8,224), fr56
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jlarmour
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diff changeset
361 lddfi @(gr8,232), fr58
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jlarmour
parents:
diff changeset
362 lddfi @(gr8,240), fr60
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jlarmour
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diff changeset
363 lddfi @(gr8,248), fr62
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f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
364 1:
208
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jlarmour
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diff changeset
365 #endif
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diff changeset
366 #endif
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diff changeset
367
1746
f8c5906d7c6e Add FR-V ports for MB9309x boards.
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diff changeset
368 #if _NGPR != 32
f8c5906d7c6e Add FR-V ports for MB9309x boards.
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diff changeset
369 #ifdef CYGINT_HAL_FRV_ARCH_FR400
f8c5906d7c6e Add FR-V ports for MB9309x boards.
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diff changeset
370 movsg HSR0,gr5
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
371 srli gr5,#10,gr5
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
372 andicc gr5,#1,gr0,icc0
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
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diff changeset
373 bne icc0,0,1f
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
374 #endif
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
375 lddi @(gr8,64), gr48
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
376 lddi @(gr8,72), gr50
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
377 lddi @(gr8,80), gr52
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
378 lddi @(gr8,88), gr54
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
379 lddi @(gr8,96), gr56
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
380 lddi @(gr8,104), gr58
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
381 lddi @(gr8,112), gr60
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
382 lddi @(gr8,120), gr62
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
383 1:
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
384 #endif
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
385 lddi @(gr8,0), gr16
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
386 lddi @(gr8,8), gr18
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
387 lddi @(gr8,16), gr20
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
388 lddi @(gr8,24), gr22
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
389 lddi @(gr8,32), gr24
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
390 lddi @(gr8,40), gr26
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
391 lddi @(gr8,48), gr28
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
392 lddi @(gr8,56), gr30
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
393
f8c5906d7c6e Add FR-V ports for MB9309x boards.
msalter
parents: 210
diff changeset
394
208
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jlarmour
parents:
diff changeset
395 ldi @(gr8,256), gr4
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jlarmour
parents:
diff changeset
396 movgs gr4,lr
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jlarmour
parents:
diff changeset
397
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jlarmour
parents:
diff changeset
398 ldi @(gr8,260), sp
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jlarmour
parents:
diff changeset
399 ldi @(gr8,264), fp
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jlarmour
parents:
diff changeset
400
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jlarmour
parents:
diff changeset
401 # Value to return is in r9. If zero, return 1
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jlarmour
parents:
diff changeset
402 cmp gr9, gr0, icc0
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jlarmour
parents:
diff changeset
403 setlos #1, gr8
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jlarmour
parents:
diff changeset
404 ckne icc0, cc4
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jlarmour
parents:
diff changeset
405 cmov gr9, gr8, cc4, 1
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jlarmour
parents:
diff changeset
406 ret
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jlarmour
parents:
diff changeset
407 .Lend2:
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jlarmour
parents:
diff changeset
408 .size hal_longjmp,.Lend2-hal_longjmp2
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jlarmour
parents:
diff changeset
409
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jlarmour
parents:
diff changeset
410 // ----------------------------------------------------------------------------
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jlarmour
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diff changeset
411 // end of context.S