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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 74dbf4c3f2e1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 //==========================================================================
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2 //
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3 // var_misc.c
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4 //
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5 // HAL implementation miscellaneous functions
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6 //
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7 //==========================================================================
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8 // ####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later
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16 // version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License
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24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 //
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27 // As a special exception, if other files instantiate templates or use
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28 // macros or inline functions from this file, or you compile this file
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29 // and link it with other works to produce a work based on this file,
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30 // this file does not by itself cause the resulting work to be covered by
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31 // the GNU General Public License. However the source code for this file
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32 // must still be made available in accordance with section (3) of the GNU
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33 // General Public License v2.
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34 //
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35 // This exception does not invalidate any other reasons why a work based
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36 // on this file might be covered by the GNU General Public License.
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37 // -------------------------------------------
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38 // ####ECOSGPLCOPYRIGHTEND####
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39 //==========================================================================
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40 //#####DESCRIPTIONBEGIN####
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41 //
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42 // Author(s): jskov
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43 // Contributors: jskov, gthomas
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44 // Date: 2000-02-04
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45 // Purpose: HAL miscellaneous functions
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46 // Description: This file contains miscellaneous functions provided by the
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47 // HAL.
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //==========================================================================
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52
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53 #include <pkgconf/hal.h>
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54
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55 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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56 #include <cyg/hal/ppc_regs.h>
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57 #include <cyg/hal/quicc/ppc8xx.h>
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58 #include <cyg/infra/cyg_type.h> // types
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59 #include <cyg/infra/diag.h> // diag_printf
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60
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61 #include <cyg/hal/hal_mem.h> // some of the functions defined here
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62
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63 //--------------------------------------------------------------------------
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64 void
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65 hal_variant_init(void)
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66 {
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67 // Disable serialization
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68 {
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69 cyg_uint32 ictrl;
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70 CYGARC_MFSPR (ICTRL, ictrl);
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71 ictrl |= ICTRL_NOSERSHOW;
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72 CYGARC_MTSPR (ICTRL, ictrl);
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73 }
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74
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75 #ifndef CYGSEM_HAL_USE_ROM_MONITOR
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76 // Reset CPM
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77 _mpc8xx_reset_cpm();
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78 #endif
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79 }
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80
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81 //--------------------------------------------------------------------------
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82 // Variant specific idle thread action.
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83 bool
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84 hal_variant_idle_thread_action( cyg_uint32 count )
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85 {
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86 #if 0
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87 cyg_uint32 *psivec = (cyg_uint32*)CYGARC_REG_IMM_SIVEC ;
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88 cyg_uint32 *psimask = (cyg_uint32*)CYGARC_REG_IMM_SIMASK;
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89 cyg_uint32 *psipend = (cyg_uint32*)CYGARC_REG_IMM_SIPEND;
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90 cyg_uint16 *ptbscr = (cyg_uint16*)CYGARC_REG_IMM_TBSCR;
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91
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92 diag_printf( "TBSCR %04x, vec %d: sivec %08x, simask %08x, sipend %08x\n",
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93 (cyg_uint32)(*ptbscr), (*psivec)>>26, *psivec,
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94 *psimask, *psipend );
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95 #endif
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96
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97 // Let architecture idle thread action run
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98 return true;
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99 }
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100
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101 //---------------------------------------------------------------------------
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102 // Use MMU resources to map memory regions.
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103 // Takes and returns an int used to ID the MMU resource to use. This ID
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104 // is increased as resources are used and should be used for subsequent
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105 // invocations.
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106 //
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107 // The MPC8xx CPUs do not have BATs. Fortunately we don't currently
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108 // use the MMU, so we can simulate BATs by using the TLBs.
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109
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110 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \
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111 defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \
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112 defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) || \
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113 defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \
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114 defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \
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115 defined(CYGHWR_HAL_POWERPC_MPC8XX_866T) || \
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116 defined(CYGHWR_HAL_POWERPC_MPC8XX_862P)
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117 #define NUM_TLBS 32
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118 #elif defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
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119 #define NUM_TLBS 8
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120 #else
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121 #error Missing TLB information for this platform
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122 #endif
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123
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124 int
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125 cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys,
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126 cyg_int32 size, cyg_uint8 flags)
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127 {
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128 cyg_uint32 epn, rpn, twc, ctr = 0;
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129
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130 epn = (virt & MI_EPN_EPNMASK) | MI_EPN_EV;
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131 rpn = ((phys & MI_RPN_RPNMASK)
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132 | MI_RPN_PPRWRW | MI_RPN_LPS | MI_RPN_SH | MI_RPN_V);
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133 if (flags & CYGARC_MEMDESC_CI)
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134 rpn |= MI_RPN_CI;
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135
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136 twc = MI_TWC_PS8MB | MI_TWC_V;
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137 if (flags & CYGARC_MEMDESC_GUARDED)
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138 twc |= MI_TWC_G;
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139
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140 // Ignore attempts to use more than max_tlbs.
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141 while (id < NUM_TLBS && size > 0) {
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142 ctr = id << MI_CTR_INDX_SHIFT;
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143
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144 // Instruction TLB.
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145 CYGARC_MTSPR (MI_TWC, twc);
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146 CYGARC_MTSPR (MI_CTR, ctr);
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147 CYGARC_MTSPR (MI_EPN, epn);
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148 CYGARC_MTSPR (MI_RPN, rpn);
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149
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150 // Data TLB.
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151 {
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152 cyg_uint32 drpn;
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153
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154 // Need to mark data page as changed or an exception
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155 // will be generated on first write to the page.
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156 drpn = rpn | MD_RPN_CHANGED;
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157
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158 CYGARC_MTSPR (MD_TWC, twc);
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159 CYGARC_MTSPR (MD_CTR, ctr);
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160 CYGARC_MTSPR (MD_EPN, epn);
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161 CYGARC_MTSPR (MD_RPN, drpn);
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162 }
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163
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164 // Move to next 8MB block.
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165 size -= 8*1024*1024;
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166 epn += 8*1024*1024;
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167 rpn += 8*1024*1024;
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168 id++;
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169 }
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170
103
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171 // Make caches default disabled when MMU is disabled.
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172 CYGARC_MTSPR (MI_CTR, ctr | CYGARC_REG_MI_CTR_CIDEF);
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173 CYGARC_MTSPR (MD_CTR, ctr | CYGARC_REG_MD_CTR_CIDEF);
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174
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175 return id;
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176 }
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177
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178 // Initialize MMU to a sane (NOP) state.
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179 //
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180 // Initialize TLBs with 0, Valid bits unset.
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181 void
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182 cyg_hal_clear_MMU (void)
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183 {
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184 cyg_uint32 ctr = 0;
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185 int id;
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186
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187 CYGARC_MTSPR (M_CASID, 0);
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188
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189 for (id = 0; id < NUM_TLBS; id++) {
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190 ctr = id << MI_CTR_INDX_SHIFT;
103
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191
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192 // Instruction TLBs.
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193 CYGARC_MTSPR (MI_TWC, 0);
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194 CYGARC_MTSPR (MI_CTR, ctr);
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195 CYGARC_MTSPR (MI_EPN, 0);
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196 CYGARC_MTSPR (MI_RPN, 0);
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197 // Data TLBs.
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198 CYGARC_MTSPR (MD_TWC, 0);
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199 CYGARC_MTSPR (MD_CTR, ctr);
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200 CYGARC_MTSPR (MD_EPN, 0);
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201 CYGARC_MTSPR (MD_RPN, 0);
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202 }
103
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203
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204 // Make caches default disabled when MMU is disabled.
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205 CYGARC_MTSPR (MI_CTR, ctr | CYGARC_REG_MI_CTR_CIDEF);
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206 CYGARC_MTSPR (MD_CTR, ctr | CYGARC_REG_MD_CTR_CIDEF);
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207 }
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208
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209 #ifdef CYGPKG_PROFILE_GPROF
423
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210 //--------------------------------------------------------------------------
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211 //
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212 // Profiling support - uses a separate high-speed timer
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213 //
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214
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215 #include <cyg/hal/hal_arch.h>
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216 #include <cyg/hal/hal_intr.h>
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217 #include <cyg/hal/quicc/ppc8xx.h>
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218 #include <cyg/profile/profile.h>
423
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219
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220 // Can't rely on Cyg_Interrupt class being defined.
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221 #define Cyg_InterruptHANDLED 1
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222
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223 #define PIT_IRQ_LEVEL 4
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224 #define PIT_IRQ CYGNUM_HAL_INTERRUPT_SIU_LVL4
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225 #define ID_PIT 34512
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226
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227
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228 // Periodic timer ISR.
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229 static cyg_uint32
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230 isr_pit(CYG_ADDRWORD vector, CYG_ADDRWORD data, HAL_SavedRegisters *regs)
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231 {
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232
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233 HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_PIT);
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234 __profile_hit(regs->pc);
423
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235
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236 return Cyg_InterruptHANDLED;
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237 }
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238
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239 int
423
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240 hal_enable_profile_timer(int resolution)
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241 {
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242 // Run periodic timer interrupt for profile
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243 cyg_uint16 piscr;
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244 int period = resolution / 100;
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245
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246 // Attach pit arbiter.
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247 HAL_INTERRUPT_ATTACH (PIT_IRQ,
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248 &hal_arbitration_isr_pit, ID_PIT, 0);
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249 HAL_INTERRUPT_UNMASK (PIT_IRQ);
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250
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251 // Attach pit isr.
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252 HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit,
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253 ID_PIT, 0);
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254 HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, PIT_IRQ_LEVEL);
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255 HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);
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256
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257
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258 // Set period.
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259 HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC,
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260 (2*period) << CYGARC_REG_IMM_PITC_COUNT_SHIFT);
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261
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262 // Enable.
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263 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
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264 piscr |= CYGARC_REG_IMM_PISCR_PTE;
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265 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
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266
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267 return resolution;
423
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268 }
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269 #endif
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270
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271 //--------------------------------------------------------------------------
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272 // End of var_misc.c