//=============================================================================
//
//      mod_regs_cac.h
//
//      CAC (cache) Module register definitions
//
//=============================================================================
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//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   jskov
// Contributors:jskov
// Date:        2002-01-09
//              
//####DESCRIPTIONEND####
//
//=============================================================================

// Besides the below, cache sizes are defined in the CPU variant module
// headers (mod_76xx.h).

//--------------------------------------------------------------------------
// Cache registers
#define CYGARC_REG_CCR                  0xfffffe92

#define CYGARC_REG_CCR_W3               0xc0 // way affected
#define CYGARC_REG_CCR_W2               0x80
#define CYGARC_REG_CCR_W1               0x40
#define CYGARC_REG_CCR_W0               0x00
#define CYGARC_REG_CCR_WB               0x20 // write-back
#define CYGARC_REG_CCR_CP               0x10 // cache purge
#define CYGARC_REG_CCR_TW               0x08 // two-way mode
#define CYGARC_REG_CCR_OD               0x04 // operand replacement disable
#define CYGARC_REG_CCR_ID               0x02 // instruction replacement disable
#define CYGARC_REG_CCR_CE               0x01 // cache enable


//--------------------------------------------------------------------------
// Address array access
// Address part (base/top/step specified in mod file)
#define CYGARC_REG_CACHE_ADDRESS_ADDRESS 0x00000008 // compare address

// Data part
#define CYGARC_REG_CACHE_ADDRESS_TAG_Mask 0x1ffffc00
#define CYGARC_REG_CACHE_ADDRESS_U 0x00000002 // updated (contains dirty data)
#define CYGARC_REG_CACHE_ADDRESS_V 0x00000001 // valid
