#ifndef CYGONCE_HAL_VAR_IOCLKGAT_H
#define CYGONCE_HAL_VAR_IOCLKGAT_H
//===========================================================================
//
//      var_io_clkgat.h
//
//      Kinetis clock gating
//
//===========================================================================
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
// -------------------------------------------                              
// This file is part of eCos, the Embedded Configurable Operating System.   
// Copyright (C) 2013 Free Software Foundation, Inc.                        
//
// eCos is free software; you can redistribute it and/or modify it under    
// the terms of the GNU General Public License as published by the Free     
// Software Foundation; either version 2 or (at your option) any later      
// version.                                                                 
//
// eCos is distributed in the hope that it will be useful, but WITHOUT      
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
// for more details.                                                        
//
// You should have received a copy of the GNU General Public License        
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
//
// As a special exception, if other files instantiate templates or use      
// macros or inline functions from this file, or you compile this file      
// and link it with other works to produce a work based on this file,       
// this file does not by itself cause the resulting work to be covered by   
// the GNU General Public License. However the source code for this file    
// must still be made available in accordance with section (3) of the GNU   
// General Public License v2.                                               
//
// This exception does not invalidate any other reasons why a work based    
// on this file might be covered by the GNU General Public License.         
// -------------------------------------------                              
// ####ECOSGPLCOPYRIGHTEND####                                              
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
// Date:          2013-03-17
// Purpose:       Kinetis clock distribution macros
// Description:
// Usage:         This file is included by <cyg/hal/var_io.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================


//---------------------------------------------------------------------------
// Clock distribution

// SCGC1 Bit Fields
#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M            0x20
#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S            5
#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M           0x400
#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S           10
#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M           0x800
#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S           11

#define CYGHWR_HAL_KINETIS_SIM_SCGC_OSC1  \
        CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART4 \
        CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART5 \
        CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S)

// SCGC2 Bit Fields
#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M            0x1
#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S            0
#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_M            0x1000
#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S            12
#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M            0x2000
#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S            13

#define CYGHWR_HAL_KINETIS_SIM_SCGC_ENET \
        CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_DAC0 \
        CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_DAC1 \
        CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S)

// SCGC3 Bit Fields
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_M            0x1
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_S            0
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M            0x1
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S            0
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M        0x10
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S        4
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_M             0x100
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_S             8
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M            0x1000
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S            12
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M             0x4000
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S             14
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_M            0x8000
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_S            15
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M            0x20000
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S            17
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_M            0x40000
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_S            22
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M            0x1000000
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S            24
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM3_M            0x2000000
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM3_S            25
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M            0x8000000
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S            27
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_M            0x10000000
#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S            28

#define CYGHWR_HAL_KINETIS_SIM_SCGC_RNGA     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_RNGB     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXCAN1 \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_NFC      \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI2     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_DDR      \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_SAI1     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_SDHC     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_LCDC     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM2     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC1     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC3     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S)

// SCGC4 Bit Fields
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M             0x2
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S             1
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_M             0x4
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S             2
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_M            0x40
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S            6
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_M            0x80
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S            7
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_M           0x400
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S           10
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_M           0x800
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S           11
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_M           0x1000
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S           12
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_M           0x2000
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S           13
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_M          0x40000
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S          18
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_M             0x80000
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S             19
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_M            0x100000
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S            20
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M            0x10000000
#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S            28

#define CYGHWR_HAL_KINETIS_SIM_SCGC_EWM    \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_CMT    \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2C0   \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2C1   \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART0  \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART1  \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART2  \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART3  \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBOTG \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_CMP    \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_VREF   \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_LLWU   \
        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S)

// SCGC5 Bit Fields
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M         0x1
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S         0
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_M         0x2
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S         1
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_M          0x4
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_S          2
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_M        0x8
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_S        3
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_M             0x20
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S             5
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M           0x200
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S           9
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M           0x400
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S           10
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M           0x800
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S           11
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M           0x1000
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S           12
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M           0x2000
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S           13
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M           0x4000
#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S           14

#define CYGHWR_HAL_KINETIS_SIM_SCGC_LPTIMER   \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_REGFILE   \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_DRYICE    \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_DRYICESR  \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_TSI       \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTA     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTB     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTC     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTD     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTE     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTF     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S)

// SCGC6 Bit Fields
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M            0x1
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S            0
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M          0x2
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S          1
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_M         0x2
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S         1
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_M         0x4
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S         2
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_M        0x10
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S        4
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_M            0x1000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_S            12
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_M            0x2000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S            13
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_M             0x8000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S             15
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_M            0x8000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_S            15
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_M             0x40000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S             18
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_M           0x100000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_S           20
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_M          0x200000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S          21
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_M             0x400000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S             22
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_M             0x800000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S             23
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_M            0x1000000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S            24
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_M            0x2000000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S            25
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M            0x8000000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S            27
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M             0x20000000
#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S             29

#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTFL     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX   \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0  \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1  \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXCAN0 \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI0     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI1     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2S      \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_SAI0     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_CRC      \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBHS    \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBDCD   \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_PDB      \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_PIT      \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM0     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM1     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC0     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_RTC      \
        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S)

// SCGC7 Bit Fields
#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M         0x1
#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S         0
#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_M             0x2
#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S             1
#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M             0x4
#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S             2

#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXBUS \
        CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMA     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S)
#define CYGHWR_HAL_KINETIS_SIM_SCGC_MPU     \
        CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S)

//-----------------------------------------------------------------------------
// end of var_io_clkgat.h

#endif // CYGONCE_HAL_VAR_IOCLKGAT_H
