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Separate data and code caches, as well as text indentation suggested by Jifl. Fixes to cache and SDRAM CDL and functions Improved SDRAM controller support due to better manufacturer documentation: Configurable pad control. [Bugzilla 1001606]
author vae
date Sat, 03 Nov 2012 15:51:54 +0000
parents 9b3d0f81044b
children
comparison
equal deleted inserted replaced
3188:cb5a35f3fda4 3189:068fbe2304f1
76 Within a family and/or across families the chips are further differentiated by their features 76 Within a family and/or across families the chips are further differentiated by their features
77 such as: optional FPU, amount of memory, etc. The family member options are reflected in the 77 such as: optional FPU, amount of memory, etc. The family member options are reflected in the
78 controller naming scheme (see respective Freescale Kinetis product brief(s) and reference manual(s)). 78 controller naming scheme (see respective Freescale Kinetis product brief(s) and reference manual(s)).
79 The Kinetis part builder <literal>CYGHWR_HAL_CORTEXM_KINETIS</literal>, respects this naming scheme and 79 The Kinetis part builder <literal>CYGHWR_HAL_CORTEXM_KINETIS</literal>, respects this naming scheme and
80 enables the user to interactively configure eCos for the desired part by selecting 80 enables the user to interactively configure eCos for the desired part by selecting
81 the requested part's name segments. 81 the requested part name segments.
82 Based on user input, the CDL computes the part-specific eCos configuration. This includes calculation 82 Based on user input, the CDL computes the part-specific eCos configuration. This includes calculation
83 of on-chip FLASH and SRAM layout as well as the activation/deactivation of options such as FPU and 83 of on-chip FLASH and SRAM layout as well as the activation/deactivation of options such as FPU and
84 Ethernet. 84 Ethernet.
85 </para> 85 </para>
86 </refsect2> 86 </refsect2>
228 </para> 228 </para>
229 </refsect3> 229 </refsect3>
230 <refsect3 id="kinetis-var-memory-cache"><title>Cache</title> 230 <refsect3 id="kinetis-var-memory-cache"><title>Cache</title>
231 <para> 231 <para>
232 Kinetis members with operating frequencies of 120 MHz and 150 MHz are equipped with cache memory. 232 Kinetis members with operating frequencies of 120 MHz and 150 MHz are equipped with cache memory.
233 Due to the Harvard architecture, there are two unified cache memories connected to code 233 Due to the Harvard architecture, there are two cache memories connected to code
234 - <emphasis>PC</emphasis> and system - <emphasis>PS</emphasis> buses respectively. One of the 234 - <emphasis>PC</emphasis> and system - <emphasis>PS</emphasis> buses respectively.
235 issues with caching is operation with bus masters such as DMA, Ethernet controller, etc. 235 Although both modules can cache both instructions and data (unified caches), with the provided
236 In order to keep shared data such 236 memory they act as instruction (<emphasis>PC</emphasis>) and data (<emphasis>PS</emphasis>) caches.
237 as buffers and transfer descriptors synchronous, a part of cached data may have to be flushed 237 </para>
238 and/or invalidated. In some cases, an alternative can be the usage of non-cacheable memory 238 <para>
239 regions. <literal>CYGHWR_HAL_NON_CACHABLE</literal> provides for the configuration of non-cacheable 239 A common caching issue is sharing memory resources with bus masters such as DMA, Ethernet controller, etc.
240 memory. If some bus masters have provision for non-cacheable memory, such configuration options 240 In order to keep shared data such as buffers and transfer control descriptors consistent,
241 can be parented by <literal>CYGHWR_HAL_NON_CACHABLE</literal>. 241 cached data have to be flushed and/or invalidated. An alternative approach, used here is usage of
242 non-cachable memory for shared data. <literal>CYGHWR_HAL_NON_CACHABLE</literal> provides for
243 the configuration of non-cachable memory. If some bus masters have provision for non-cache able memory,
244 such configuration options can be parenthed by <literal>CYGHWR_HAL_NON_CACHABLE</literal>.
242 </para> 245 </para>
243 </refsect3> 246 </refsect3>
244 </refsect2> 247 </refsect2>
245 <refsect2 id="kinetis-var-startup"><title>Startup types</title> 248 <refsect2 id="kinetis-var-startup"><title>Startup types</title>
246 <para> 249 <para>