comparison packages/devs/eth/powerpc/fec/current/src/if_fec.c @ 382:0f9e057c8163

Mostly cosmetic cleanups. TS1000 FLASH package renamed. Remove some old cruft in Viper & TS1000 ports.
author gthomas
date Fri, 18 Oct 2002 16:56:52 +0000
parents 6279a5f6c86b
children 4982251f527c
comparison
equal deleted inserted replaced
381:6131849116d0 382:0f9e057c8163
206 cyg_drv_interrupt_acknowledge(FEC_ETH_INT); 206 cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
207 cyg_drv_interrupt_unmask(FEC_ETH_INT); 207 cyg_drv_interrupt_unmask(FEC_ETH_INT);
208 #endif 208 #endif
209 } 209 }
210 210
211 #ifdef CYGSEM_DEVS_ETH_POWERPC_FEC_RESET_PHY
211 // 212 //
212 // PHY unit access (via MII channel) 213 // PHY unit access (via MII channel)
213 // 214 //
214 static void 215 static void
215 phy_write(int reg, int addr, unsigned short data) 216 phy_write(int reg, int addr, unsigned short data)
238 } 239 }
239 } 240 }
240 *val = fec->MiiData & 0x0000FFFF; 241 *val = fec->MiiData & 0x0000FFFF;
241 return true; 242 return true;
242 } 243 }
244 #endif // CYGSEM_DEVS_ETH_POWERPC_FEC_RESET_PHY
243 245
244 // 246 //
245 // [re]Initialize the ethernet controller 247 // [re]Initialize the ethernet controller
246 // Done separately since shutting down the device requires a 248 // Done separately since shutting down the device requires a
247 // full reconfiguration when re-enabling. 249 // full reconfiguration when re-enabling.
392 { 394 {
393 struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance; 395 struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
394 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; 396 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
395 volatile EPPC *eppc = (volatile EPPC *)eppc_base(); 397 volatile EPPC *eppc = (volatile EPPC *)eppc_base();
396 volatile struct fec *fec = (volatile struct fec *)((unsigned char *)eppc + FEC_OFFSET); 398 volatile struct fec *fec = (volatile struct fec *)((unsigned char *)eppc + FEC_OFFSET);
399 int cache_state;
400 unsigned long proc_rev;
401 bool esa_ok;
402 #ifdef CYGSEM_DEVS_ETH_POWERPC_FEC_RESET_PHY
403 int phy_timeout = 5*1000; // Wait 5 seconds max for link to clear
404 bool phy_ok;
397 unsigned short phy_state = 0; 405 unsigned short phy_state = 0;
398 int cache_state; 406 #endif
399 int i;
400 unsigned long proc_rev;
401 bool esa_ok, phy_ok;
402 int phy_timeout = 5*1000; // Wait 5 seconds max for link to clear
403 407
404 // Ensure consistent state between cache and what the FEC sees 408 // Ensure consistent state between cache and what the FEC sees
405 HAL_DCACHE_IS_ENABLED(cache_state); 409 HAL_DCACHE_IS_ENABLED(cache_state);
406 if (cache_state) 410 if (cache_state)
407 HAL_DCACHE_SYNC(); 411 HAL_DCACHE_SYNC();
478 482
479 phy_ok = 0; 483 phy_ok = 0;
480 if (phy_read(PHY_BMSR, FEC_ETH_PHY, &phy_state)) { 484 if (phy_read(PHY_BMSR, FEC_ETH_PHY, &phy_state)) {
481 if ((phy_state & PHY_BMSR_LINK) != PHY_BMSR_LINK) { 485 if ((phy_state & PHY_BMSR_LINK) != PHY_BMSR_LINK) {
482 unsigned short reset_mode; 486 unsigned short reset_mode;
487 int i;
483 phy_write(PHY_BMCR, FEC_ETH_PHY, PHY_BMCR_RESET); 488 phy_write(PHY_BMCR, FEC_ETH_PHY, PHY_BMCR_RESET);
484 for (i = 0; i < 10; i++) { 489 for (i = 0; i < 10; i++) {
485 phy_ok = phy_read(PHY_BMCR, FEC_ETH_PHY, &phy_state); 490 phy_ok = phy_read(PHY_BMCR, FEC_ETH_PHY, &phy_state);
486 if (!phy_ok) break; 491 if (!phy_ok) break;
487 if (!(phy_state & PHY_BMCR_RESET)) break; 492 if (!(phy_state & PHY_BMCR_RESET)) break;