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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
3
4 //=============================================================================
5 //
6 // hal_cache.h
7 //
8 // HAL cache control API
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Cygnus eCos Public License
15 // Version 1.0 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://sourceware.cygnus.com/ecos
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Cygnus Operating System, released
25 // September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Cygnus. Portions created
28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
29 // -------------------------------------------
30 //
31 //####COPYRIGHTEND####
32 //=============================================================================
33 //#####DESCRIPTIONBEGIN####
34 //
35 // Author(s): nickg
36 // Contributors: nickg
37 // Date: 1998-02-17
38 // Purpose: Cache control API
39 // Description: The macros defined here provide the HAL APIs for handling
40 // cache control operations.
41 // Usage:
42 // #include <cyg/hal/hal_cache.h>
43 // ...
44 //
45 //
46 //####DESCRIPTIONEND####
47 //
48 //=============================================================================
49
50 #include <cyg/infra/cyg_type.h>
51
52 //=============================================================================
53 // MIPS simulator
54
55 #ifdef CYG_HAL_MIPS_SIM
56
57 //-----------------------------------------------------------------------------
58 // Cache dimensions
59
60 // Data cache
61 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
62 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
63 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
64
65 // Instruction cache
66 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
67 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
68 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
69
70 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
71 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
72
73 //-----------------------------------------------------------------------------
74 // Global control of data cache
75
76 // Enable the data cache
77 #define HAL_DCACHE_ENABLE()
78
79 // Disable the data cache
80 #define HAL_DCACHE_DISABLE()
81
82 // Invalidate the entire cache
83 #define HAL_DCACHE_INVALIDATE_ALL()
84
85 // Synchronize the contents of the cache with memory.
86 #define HAL_DCACHE_SYNC()
87
88 // Set the data cache refill burst size
89 //#define HAL_DCACHE_BURST_SIZE(_size_)
90
91 // Set the data cache write mode
92 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
93
94 //#define HAL_DCACHE_WRITETHRU_MODE 0
95 //#define HAL_DCACHE_WRITEBACK_MODE 1
96
97 // Load the contents of the given address range into the data cache
98 // and then lock the cache so that it stays there.
99 //#define HAL_DCACHE_LOCK(_base_, _size_)
100
101 // Undo a previous lock operation
102 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
103
104 //-----------------------------------------------------------------------------
105 // Data cache line control
106
107 // Allocate cache lines for the given address range without reading its
108 // contents from memory.
109 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
110
111 // Write dirty cache lines to memory and invalidate the cache entries
112 // for the given address range.
113 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
114
115 // Invalidate cache lines in the given range without writing to memory.
116 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
117
118 // Write dirty cache lines to memory for the given address range.
119 //#define HAL_DCACHE_STORE( _base_ , _size_ )
120
121 // Preread the given range into the cache with the intention of reading
122 // from it later.
123 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
124
125 // Preread the given range into the cache with the intention of writing
126 // to it later.
127 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
128
129 // Allocate and zero the cache lines associated with the given range.
130 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
131
132 //-----------------------------------------------------------------------------
133 // Global control of Instruction cache
134
135 // Enable the instruction cache
136 #define HAL_ICACHE_ENABLE()
137
138 // Disable the instruction cache
139 #define HAL_ICACHE_DISABLE()
140
141 // Invalidate the entire cache
142 #define HAL_ICACHE_INVALIDATE_ALL()
143
144 // Synchronize the contents of the cache with memory.
145 #define HAL_ICACHE_SYNC()
146
147 // Set the instruction cache refill burst size
148 //#define HAL_ICACHE_BURST_SIZE(_size_)
149
150 // Load the contents of the given address range into the instruction cache
151 // and then lock the cache so that it stays there.
152 //#define HAL_ICACHE_LOCK(_base_, _size_)
153
154 // Undo a previous lock operation
155 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
156
157 //-----------------------------------------------------------------------------
158 // Instruction cache line control
159
160 // Invalidate cache lines in the given range without writing to memory.
161 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
162
163 #endif
164
165
166 //=============================================================================
167 // Toshiba TX3904
168
169 #ifdef CYG_HAL_MIPS_TX3904
170
171 //-----------------------------------------------------------------------------
172 // Cache dimensions
173
174 // Data cache
175 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
176 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
177 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
178
179 // Instruction cache
180 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
181 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
182 #define HAL_ICACHE_WAYS 1 // Associativity of the cache
183
184 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
185 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
186
187 //-----------------------------------------------------------------------------
188 // Global control of data cache
189
190 // Enable the data cache
191 #define HAL_DCACHE_ENABLE() \
192 { \
193 asm volatile ("mfc0 $2,$3;" \
194 "ori $2,$2,0x0010;" \
195 "mtc0 $2,$3;" \
196 : \
197 : \
198 : "$2" \
199 ); \
200 \
201 }
202
203 // Disable the data cache
204 #define HAL_DCACHE_DISABLE() \
205 { \
206 asm volatile ("mfc0 $2,$3;" \
207 "la $3,0xFFFFFFEF;" \
208 "and $2,$2,$3;" \
209 "mtc0 $2,$3;" \
210 : \
211 : \
212 : "$2", "$3" \
213 ); \
214 \
215 }
216
217 // Invalidate the entire cache
218 // We do this by reading a word from each line to invalidate the current
219 // cache contents.
220 #define HAL_DCACHE_INVALIDATE_ALL() \
221 { \
222 extern char __ram_data_start; \
223 CYG_WORD *addr = (CYG_WORD *)&__ram_data_start; \
224 CYG_WORD sum = 0; \
225 int i; \
226 for( i = 0; i < HAL_DCACHE_SIZE; i += HAL_DCACHE_LINE_SIZE ) \
227 { \
228 sum += addr[i]; \
229 } \
230 }
231
232 // Synchronize the contents of the cache with memory.
233 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
234
235 // Set the data cache refill burst size
236 //#define HAL_DCACHE_BURST_SIZE(_size_)
237
238 // Set the data cache write mode
239 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
240
241 //#define HAL_DCACHE_WRITETHRU_MODE 0
242 //#define HAL_DCACHE_WRITEBACK_MODE 1
243
244 // Load the contents of the given address range into the data cache
245 // and then lock the cache so that it stays there.
246 #define HAL_DCACHE_LOCK(_base_, _size_) \
247 { \
248 asm volatile ("mfc0 $2,$7;" \
249 "ori $2,$2,0x0100;" \
250 "mtc0 $2,$7;" \
251 : \
252 : \
253 : "$2" \
254 ); \
255 }
256
257 // Undo a previous lock operation
258 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
259 { \
260 asm volatile ("mfc0 $2,$7;" \
261 "la $3,0xFFFFFEFF;" \
262 "and $2,$2,$3;" \
263 "mtc0 $2,$7;" \
264 : \
265 : \
266 : "$2", "$3" \
267 ); \
268 }
269
270 //-----------------------------------------------------------------------------
271 // Data cache line control
272
273 // Allocate cache lines for the given address range without reading its
274 // contents from memory.
275 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
276
277 // Write dirty cache lines to memory and invalidate the cache entries
278 // for the given address range.
279 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
280
281 // Invalidate cache lines in the given range without writing to memory.
282 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
283 { \
284 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
285 register CYG_WORD _size_ = (_asize_); \
286 HAL_DCACHE_DISABLE(); \
287 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
288 { \
289 asm volatile ("cache 17,0(%0)" : : "r"(addr) ); \
290 } \
291 HAL_DCACHE_ENABLE(); \
292 }
293
294 // Write dirty cache lines to memory for the given address range.
295 //#define HAL_DCACHE_STORE( _base_ , _size_ )
296
297 // Preread the given range into the cache with the intention of reading
298 // from it later.
299 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
300
301 // Preread the given range into the cache with the intention of writing
302 // to it later.
303 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
304
305 // Allocate and zero the cache lines associated with the given range.
306 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
307
308 //-----------------------------------------------------------------------------
309 // Global control of Instruction cache
310
311 // Enable the instruction cache
312 #define HAL_ICACHE_ENABLE() \
313 { \
314 asm volatile ("mfc0 $2,$3;" \
315 "ori $2,$2,0x0020;" \
316 "mtc0 $2,$3;" \
317 : \
318 : \
319 : "$2" \
320 ); \
321 \
322 }
323
324 // Disable the instruction cache
325 #define HAL_ICACHE_DISABLE() \
326 { \
327 asm volatile ("mfc0 $2,$3;" \
328 "la $3,0xFFFFFFDF;" \
329 "and $2,$2,$3;" \
330 "mtc0 $2,$3;" \
331 : \
332 : \
333 : "$2", "$3" \
334 ); \
335 \
336 }
337
338 // Invalidate the entire cache
339 #define HAL_ICACHE_INVALIDATE_ALL() \
340 { \
341 register CYG_ADDRESS addr; \
342 HAL_ICACHE_DISABLE(); \
343 for( addr = 0; addr < HAL_ICACHE_SIZE; addr += HAL_ICACHE_LINE_SIZE ) \
344 { \
345 asm volatile ("cache 0,0(%0)" : : "r"(addr) ); \
346 } \
347 HAL_ICACHE_ENABLE(); \
348 }
349
350 // Synchronize the contents of the cache with memory.
351 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
352
353 // Set the instruction cache refill burst size
354 //#define HAL_ICACHE_BURST_SIZE(_size_)
355
356 // Load the contents of the given address range into the instruction cache
357 // and then lock the cache so that it stays there.
358 #define HAL_ICACHE_LOCK(_base_, _size_) \
359 { \
360 asm volatile ("mfc0 $2,$7;" \
361 "ori $2,$2,0x0200;" \
362 "mtc0 $2,$7;" \
363 : \
364 : \
365 : "$2" \
366 ); \
367 }
368
369 // Undo a previous lock operation
370 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
371 { \
372 asm volatile ("mfc0 $2,$7;" \
373 "la $3,0xFFFFFDFF;" \
374 "and $2,$2,$3;" \
375 "mtc0 $2,$7;" \
376 : \
377 : \
378 : "$2", "$3" \
379 ); \
380 }
381
382 //-----------------------------------------------------------------------------
383 // Instruction cache line control
384
385 // Invalidate cache lines in the given range without writing to memory.
386 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
387 { \
388 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
389 register CYG_WORD _size_ = (_asize_); \
390 HAL_ICACHE_DISABLE(); \
391 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
392 { \
393 asm volatile ("cache 0,0(%0)" : : "r"(addr) ); \
394 } \
395 HAL_ICACHE_ENABLE(); \
396 }
397
398 #endif
399
400 //-----------------------------------------------------------------------------
401 #endif // ifndef CYGONCE_HAL_CACHE_H
402 // End of hal_cache.h